1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _ASM_X86_PROCESSOR_H 3 #define _ASM_X86_PROCESSOR_H 4 5 #include <asm/processor-flags.h> 6 7 /* Forward declaration, a strange C thing */ 8 struct task_struct; 9 struct mm_struct; 10 struct io_bitmap; 11 struct vm86; 12 13 #include <asm/math_emu.h> 14 #include <asm/segment.h> 15 #include <asm/types.h> 16 #include <uapi/asm/sigcontext.h> 17 #include <asm/current.h> 18 #include <asm/cpufeatures.h> 19 #include <asm/cpuid.h> 20 #include <asm/page.h> 21 #include <asm/pgtable_types.h> 22 #include <asm/percpu.h> 23 #include <asm/desc_defs.h> 24 #include <asm/nops.h> 25 #include <asm/special_insns.h> 26 #include <asm/fpu/types.h> 27 #include <asm/unwind_hints.h> 28 #include <asm/vmxfeatures.h> 29 #include <asm/vdso/processor.h> 30 #include <asm/shstk.h> 31 32 #include <linux/personality.h> 33 #include <linux/cache.h> 34 #include <linux/threads.h> 35 #include <linux/math64.h> 36 #include <linux/err.h> 37 #include <linux/irqflags.h> 38 #include <linux/mem_encrypt.h> 39 40 /* 41 * We handle most unaligned accesses in hardware. On the other hand 42 * unaligned DMA can be quite expensive on some Nehalem processors. 43 * 44 * Based on this we disable the IP header alignment in network drivers. 45 */ 46 #define NET_IP_ALIGN 0 47 48 #define HBP_NUM 4 49 50 /* 51 * These alignment constraints are for performance in the vSMP case, 52 * but in the task_struct case we must also meet hardware imposed 53 * alignment requirements of the FPU state: 54 */ 55 #ifdef CONFIG_X86_VSMP 56 # define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT) 57 # define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT) 58 #else 59 # define ARCH_MIN_TASKALIGN __alignof__(union fpregs_state) 60 # define ARCH_MIN_MMSTRUCT_ALIGN 0 61 #endif 62 63 enum tlb_infos { 64 ENTRIES, 65 NR_INFO 66 }; 67 68 extern u16 __read_mostly tlb_lli_4k[NR_INFO]; 69 extern u16 __read_mostly tlb_lli_2m[NR_INFO]; 70 extern u16 __read_mostly tlb_lli_4m[NR_INFO]; 71 extern u16 __read_mostly tlb_lld_4k[NR_INFO]; 72 extern u16 __read_mostly tlb_lld_2m[NR_INFO]; 73 extern u16 __read_mostly tlb_lld_4m[NR_INFO]; 74 extern u16 __read_mostly tlb_lld_1g[NR_INFO]; 75 76 /* 77 * CPU type and hardware bug flags. Kept separately for each CPU. 78 */ 79 80 struct cpuinfo_topology { 81 // Real APIC ID read from the local APIC 82 u32 apicid; 83 // The initial APIC ID provided by CPUID 84 u32 initial_apicid; 85 86 // Physical package ID 87 u32 pkg_id; 88 89 // Physical die ID on AMD, Relative on Intel 90 u32 die_id; 91 92 // Compute unit ID - AMD specific 93 u32 cu_id; 94 95 // Core ID relative to the package 96 u32 core_id; 97 98 // Logical ID mappings 99 u32 logical_pkg_id; 100 u32 logical_die_id; 101 u32 logical_core_id; 102 103 // AMD Node ID and Nodes per Package info 104 u32 amd_node_id; 105 106 // Cache level topology IDs 107 u32 llc_id; 108 u32 l2c_id; 109 110 // Hardware defined CPU-type 111 union { 112 u32 cpu_type; 113 struct { 114 // CPUID.1A.EAX[23-0] 115 u32 intel_native_model_id :24; 116 // CPUID.1A.EAX[31-24] 117 u32 intel_type :8; 118 }; 119 struct { 120 // CPUID 0x80000026.EBX 121 u32 amd_num_processors :16, 122 amd_power_eff_ranking :8, 123 amd_native_model_id :4, 124 amd_type :4; 125 }; 126 }; 127 }; 128 129 struct cpuinfo_x86 { 130 union { 131 /* 132 * The particular ordering (low-to-high) of (vendor, 133 * family, model) is done in case range of models, like 134 * it is usually done on AMD, need to be compared. 135 */ 136 struct { 137 __u8 x86_model; 138 /* CPU family */ 139 __u8 x86; 140 /* CPU vendor */ 141 __u8 x86_vendor; 142 __u8 x86_reserved; 143 }; 144 /* combined vendor, family, model */ 145 __u32 x86_vfm; 146 }; 147 __u8 x86_stepping; 148 #ifdef CONFIG_X86_64 149 /* Number of 4K pages in DTLB/ITLB combined(in pages): */ 150 int x86_tlbsize; 151 #endif 152 #ifdef CONFIG_X86_VMX_FEATURE_NAMES 153 __u32 vmx_capability[NVMXINTS]; 154 #endif 155 __u8 x86_virt_bits; 156 __u8 x86_phys_bits; 157 /* Max extended CPUID function supported: */ 158 __u32 extended_cpuid_level; 159 /* Maximum supported CPUID level, -1=no CPUID: */ 160 int cpuid_level; 161 /* 162 * Align to size of unsigned long because the x86_capability array 163 * is passed to bitops which require the alignment. Use unnamed 164 * union to enforce the array is aligned to size of unsigned long. 165 */ 166 union { 167 __u32 x86_capability[NCAPINTS + NBUGINTS]; 168 unsigned long x86_capability_alignment; 169 }; 170 char x86_vendor_id[16]; 171 char x86_model_id[64]; 172 struct cpuinfo_topology topo; 173 /* in KB - valid for CPUS which support this call: */ 174 unsigned int x86_cache_size; 175 int x86_cache_alignment; /* In bytes */ 176 /* Cache QoS architectural values, valid only on the BSP: */ 177 int x86_cache_max_rmid; /* max index */ 178 int x86_cache_occ_scale; /* scale to bytes */ 179 int x86_cache_mbm_width_offset; 180 int x86_power; 181 unsigned long loops_per_jiffy; 182 /* protected processor identification number */ 183 u64 ppin; 184 u16 x86_clflush_size; 185 /* number of cores as seen by the OS: */ 186 u16 booted_cores; 187 /* Index into per_cpu list: */ 188 u16 cpu_index; 189 /* Is SMT active on this core? */ 190 bool smt_active; 191 u32 microcode; 192 /* Address space bits used by the cache internally */ 193 u8 x86_cache_bits; 194 unsigned initialized : 1; 195 } __randomize_layout; 196 197 #define X86_VENDOR_INTEL 0 198 #define X86_VENDOR_CYRIX 1 199 #define X86_VENDOR_AMD 2 200 #define X86_VENDOR_UMC 3 201 #define X86_VENDOR_CENTAUR 5 202 #define X86_VENDOR_TRANSMETA 7 203 #define X86_VENDOR_NSC 8 204 #define X86_VENDOR_HYGON 9 205 #define X86_VENDOR_ZHAOXIN 10 206 #define X86_VENDOR_VORTEX 11 207 #define X86_VENDOR_NUM 12 208 209 #define X86_VENDOR_UNKNOWN 0xff 210 211 /* 212 * capabilities of CPUs 213 */ 214 extern struct cpuinfo_x86 boot_cpu_data; 215 extern struct cpuinfo_x86 new_cpu_data; 216 217 extern __u32 cpu_caps_cleared[NCAPINTS + NBUGINTS]; 218 extern __u32 cpu_caps_set[NCAPINTS + NBUGINTS]; 219 220 DECLARE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info); 221 #define cpu_data(cpu) per_cpu(cpu_info, cpu) 222 223 extern const struct seq_operations cpuinfo_op; 224 225 #define cache_line_size() (boot_cpu_data.x86_cache_alignment) 226 227 extern void cpu_detect(struct cpuinfo_x86 *c); 228 229 static inline unsigned long long l1tf_pfn_limit(void) 230 { 231 return BIT_ULL(boot_cpu_data.x86_cache_bits - 1 - PAGE_SHIFT); 232 } 233 234 void init_cpu_devs(void); 235 void get_cpu_vendor(struct cpuinfo_x86 *c); 236 extern void early_cpu_init(void); 237 extern void identify_secondary_cpu(struct cpuinfo_x86 *); 238 extern void print_cpu_info(struct cpuinfo_x86 *); 239 void print_cpu_msr(struct cpuinfo_x86 *); 240 241 /* 242 * Friendlier CR3 helpers. 243 */ 244 static inline unsigned long read_cr3_pa(void) 245 { 246 return __read_cr3() & CR3_ADDR_MASK; 247 } 248 249 static inline unsigned long native_read_cr3_pa(void) 250 { 251 return __native_read_cr3() & CR3_ADDR_MASK; 252 } 253 254 static inline void load_cr3(pgd_t *pgdir) 255 { 256 write_cr3(__sme_pa(pgdir)); 257 } 258 259 /* 260 * Note that while the legacy 'TSS' name comes from 'Task State Segment', 261 * on modern x86 CPUs the TSS also holds information important to 64-bit mode, 262 * unrelated to the task-switch mechanism: 263 */ 264 #ifdef CONFIG_X86_32 265 /* This is the TSS defined by the hardware. */ 266 struct x86_hw_tss { 267 unsigned short back_link, __blh; 268 unsigned long sp0; 269 unsigned short ss0, __ss0h; 270 unsigned long sp1; 271 272 /* 273 * We don't use ring 1, so ss1 is a convenient scratch space in 274 * the same cacheline as sp0. We use ss1 to cache the value in 275 * MSR_IA32_SYSENTER_CS. When we context switch 276 * MSR_IA32_SYSENTER_CS, we first check if the new value being 277 * written matches ss1, and, if it's not, then we wrmsr the new 278 * value and update ss1. 279 * 280 * The only reason we context switch MSR_IA32_SYSENTER_CS is 281 * that we set it to zero in vm86 tasks to avoid corrupting the 282 * stack if we were to go through the sysenter path from vm86 283 * mode. 284 */ 285 unsigned short ss1; /* MSR_IA32_SYSENTER_CS */ 286 287 unsigned short __ss1h; 288 unsigned long sp2; 289 unsigned short ss2, __ss2h; 290 unsigned long __cr3; 291 unsigned long ip; 292 unsigned long flags; 293 unsigned long ax; 294 unsigned long cx; 295 unsigned long dx; 296 unsigned long bx; 297 unsigned long sp; 298 unsigned long bp; 299 unsigned long si; 300 unsigned long di; 301 unsigned short es, __esh; 302 unsigned short cs, __csh; 303 unsigned short ss, __ssh; 304 unsigned short ds, __dsh; 305 unsigned short fs, __fsh; 306 unsigned short gs, __gsh; 307 unsigned short ldt, __ldth; 308 unsigned short trace; 309 unsigned short io_bitmap_base; 310 311 } __attribute__((packed)); 312 #else 313 struct x86_hw_tss { 314 u32 reserved1; 315 u64 sp0; 316 u64 sp1; 317 318 /* 319 * Since Linux does not use ring 2, the 'sp2' slot is unused by 320 * hardware. entry_SYSCALL_64 uses it as scratch space to stash 321 * the user RSP value. 322 */ 323 u64 sp2; 324 325 u64 reserved2; 326 u64 ist[7]; 327 u32 reserved3; 328 u32 reserved4; 329 u16 reserved5; 330 u16 io_bitmap_base; 331 332 } __attribute__((packed)); 333 #endif 334 335 /* 336 * IO-bitmap sizes: 337 */ 338 #define IO_BITMAP_BITS 65536 339 #define IO_BITMAP_BYTES (IO_BITMAP_BITS / BITS_PER_BYTE) 340 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES / sizeof(long)) 341 342 #define IO_BITMAP_OFFSET_VALID_MAP \ 343 (offsetof(struct tss_struct, io_bitmap.bitmap) - \ 344 offsetof(struct tss_struct, x86_tss)) 345 346 #define IO_BITMAP_OFFSET_VALID_ALL \ 347 (offsetof(struct tss_struct, io_bitmap.mapall) - \ 348 offsetof(struct tss_struct, x86_tss)) 349 350 #ifdef CONFIG_X86_IOPL_IOPERM 351 /* 352 * sizeof(unsigned long) coming from an extra "long" at the end of the 353 * iobitmap. The limit is inclusive, i.e. the last valid byte. 354 */ 355 # define __KERNEL_TSS_LIMIT \ 356 (IO_BITMAP_OFFSET_VALID_ALL + IO_BITMAP_BYTES + \ 357 sizeof(unsigned long) - 1) 358 #else 359 # define __KERNEL_TSS_LIMIT \ 360 (offsetof(struct tss_struct, x86_tss) + sizeof(struct x86_hw_tss) - 1) 361 #endif 362 363 /* Base offset outside of TSS_LIMIT so unpriviledged IO causes #GP */ 364 #define IO_BITMAP_OFFSET_INVALID (__KERNEL_TSS_LIMIT + 1) 365 366 struct entry_stack { 367 char stack[PAGE_SIZE]; 368 }; 369 370 struct entry_stack_page { 371 struct entry_stack stack; 372 } __aligned(PAGE_SIZE); 373 374 /* 375 * All IO bitmap related data stored in the TSS: 376 */ 377 struct x86_io_bitmap { 378 /* The sequence number of the last active bitmap. */ 379 u64 prev_sequence; 380 381 /* 382 * Store the dirty size of the last io bitmap offender. The next 383 * one will have to do the cleanup as the switch out to a non io 384 * bitmap user will just set x86_tss.io_bitmap_base to a value 385 * outside of the TSS limit. So for sane tasks there is no need to 386 * actually touch the io_bitmap at all. 387 */ 388 unsigned int prev_max; 389 390 /* 391 * The extra 1 is there because the CPU will access an 392 * additional byte beyond the end of the IO permission 393 * bitmap. The extra byte must be all 1 bits, and must 394 * be within the limit. 395 */ 396 unsigned long bitmap[IO_BITMAP_LONGS + 1]; 397 398 /* 399 * Special I/O bitmap to emulate IOPL(3). All bytes zero, 400 * except the additional byte at the end. 401 */ 402 unsigned long mapall[IO_BITMAP_LONGS + 1]; 403 }; 404 405 struct tss_struct { 406 /* 407 * The fixed hardware portion. This must not cross a page boundary 408 * at risk of violating the SDM's advice and potentially triggering 409 * errata. 410 */ 411 struct x86_hw_tss x86_tss; 412 413 struct x86_io_bitmap io_bitmap; 414 } __aligned(PAGE_SIZE); 415 416 DECLARE_PER_CPU_PAGE_ALIGNED(struct tss_struct, cpu_tss_rw); 417 418 /* Per CPU interrupt stacks */ 419 struct irq_stack { 420 char stack[IRQ_STACK_SIZE]; 421 } __aligned(IRQ_STACK_SIZE); 422 423 #ifdef CONFIG_X86_64 424 struct fixed_percpu_data { 425 /* 426 * GCC hardcodes the stack canary as %gs:40. Since the 427 * irq_stack is the object at %gs:0, we reserve the bottom 428 * 48 bytes of the irq stack for the canary. 429 * 430 * Once we are willing to require -mstack-protector-guard-symbol= 431 * support for x86_64 stackprotector, we can get rid of this. 432 */ 433 char gs_base[40]; 434 unsigned long stack_canary; 435 }; 436 437 DECLARE_PER_CPU_FIRST(struct fixed_percpu_data, fixed_percpu_data) __visible; 438 DECLARE_INIT_PER_CPU(fixed_percpu_data); 439 440 static inline unsigned long cpu_kernelmode_gs_base(int cpu) 441 { 442 return (unsigned long)per_cpu(fixed_percpu_data.gs_base, cpu); 443 } 444 445 extern asmlinkage void entry_SYSCALL32_ignore(void); 446 447 /* Save actual FS/GS selectors and bases to current->thread */ 448 void current_save_fsgs(void); 449 #else /* X86_64 */ 450 #ifdef CONFIG_STACKPROTECTOR 451 DECLARE_PER_CPU(unsigned long, __stack_chk_guard); 452 #endif 453 #endif /* !X86_64 */ 454 455 struct perf_event; 456 457 struct thread_struct { 458 /* Cached TLS descriptors: */ 459 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES]; 460 #ifdef CONFIG_X86_32 461 unsigned long sp0; 462 #endif 463 unsigned long sp; 464 #ifdef CONFIG_X86_32 465 unsigned long sysenter_cs; 466 #else 467 unsigned short es; 468 unsigned short ds; 469 unsigned short fsindex; 470 unsigned short gsindex; 471 #endif 472 473 #ifdef CONFIG_X86_64 474 unsigned long fsbase; 475 unsigned long gsbase; 476 #else 477 /* 478 * XXX: this could presumably be unsigned short. Alternatively, 479 * 32-bit kernels could be taught to use fsindex instead. 480 */ 481 unsigned long fs; 482 unsigned long gs; 483 #endif 484 485 /* Save middle states of ptrace breakpoints */ 486 struct perf_event *ptrace_bps[HBP_NUM]; 487 /* Debug status used for traps, single steps, etc... */ 488 unsigned long virtual_dr6; 489 /* Keep track of the exact dr7 value set by the user */ 490 unsigned long ptrace_dr7; 491 /* Fault info: */ 492 unsigned long cr2; 493 unsigned long trap_nr; 494 unsigned long error_code; 495 #ifdef CONFIG_VM86 496 /* Virtual 86 mode info */ 497 struct vm86 *vm86; 498 #endif 499 /* IO permissions: */ 500 struct io_bitmap *io_bitmap; 501 502 /* 503 * IOPL. Privilege level dependent I/O permission which is 504 * emulated via the I/O bitmap to prevent user space from disabling 505 * interrupts. 506 */ 507 unsigned long iopl_emul; 508 509 unsigned int iopl_warn:1; 510 511 /* 512 * Protection Keys Register for Userspace. Loaded immediately on 513 * context switch. Store it in thread_struct to avoid a lookup in 514 * the tasks's FPU xstate buffer. This value is only valid when a 515 * task is scheduled out. For 'current' the authoritative source of 516 * PKRU is the hardware itself. 517 */ 518 u32 pkru; 519 520 #ifdef CONFIG_X86_USER_SHADOW_STACK 521 unsigned long features; 522 unsigned long features_locked; 523 524 struct thread_shstk shstk; 525 #endif 526 527 /* Floating point and extended processor state */ 528 struct fpu fpu; 529 /* 530 * WARNING: 'fpu' is dynamically-sized. It *MUST* be at 531 * the end. 532 */ 533 }; 534 535 extern void fpu_thread_struct_whitelist(unsigned long *offset, unsigned long *size); 536 537 static inline void arch_thread_struct_whitelist(unsigned long *offset, 538 unsigned long *size) 539 { 540 fpu_thread_struct_whitelist(offset, size); 541 } 542 543 static inline void 544 native_load_sp0(unsigned long sp0) 545 { 546 this_cpu_write(cpu_tss_rw.x86_tss.sp0, sp0); 547 } 548 549 static __always_inline void native_swapgs(void) 550 { 551 #ifdef CONFIG_X86_64 552 asm volatile("swapgs" ::: "memory"); 553 #endif 554 } 555 556 static __always_inline unsigned long current_top_of_stack(void) 557 { 558 /* 559 * We can't read directly from tss.sp0: sp0 on x86_32 is special in 560 * and around vm86 mode and sp0 on x86_64 is special because of the 561 * entry trampoline. 562 */ 563 if (IS_ENABLED(CONFIG_USE_X86_SEG_SUPPORT)) 564 return this_cpu_read_const(const_pcpu_hot.top_of_stack); 565 566 return this_cpu_read_stable(pcpu_hot.top_of_stack); 567 } 568 569 static __always_inline bool on_thread_stack(void) 570 { 571 return (unsigned long)(current_top_of_stack() - 572 current_stack_pointer) < THREAD_SIZE; 573 } 574 575 #ifdef CONFIG_PARAVIRT_XXL 576 #include <asm/paravirt.h> 577 #else 578 579 static inline void load_sp0(unsigned long sp0) 580 { 581 native_load_sp0(sp0); 582 } 583 584 #endif /* CONFIG_PARAVIRT_XXL */ 585 586 unsigned long __get_wchan(struct task_struct *p); 587 588 extern void select_idle_routine(void); 589 extern void amd_e400_c1e_apic_setup(void); 590 591 extern unsigned long boot_option_idle_override; 592 593 enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_NOMWAIT, 594 IDLE_POLL}; 595 596 extern void enable_sep_cpu(void); 597 598 599 /* Defined in head.S */ 600 extern struct desc_ptr early_gdt_descr; 601 602 extern void switch_gdt_and_percpu_base(int); 603 extern void load_direct_gdt(int); 604 extern void load_fixmap_gdt(int); 605 extern void cpu_init(void); 606 extern void cpu_init_exception_handling(bool boot_cpu); 607 extern void cpu_init_replace_early_idt(void); 608 extern void cr4_init(void); 609 610 extern void set_task_blockstep(struct task_struct *task, bool on); 611 612 /* Boot loader type from the setup header: */ 613 extern int bootloader_type; 614 extern int bootloader_version; 615 616 extern char ignore_fpu_irq; 617 618 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1 619 #define ARCH_HAS_PREFETCHW 620 621 #ifdef CONFIG_X86_32 622 # define BASE_PREFETCH "" 623 # define ARCH_HAS_PREFETCH 624 #else 625 # define BASE_PREFETCH "prefetcht0 %1" 626 #endif 627 628 /* 629 * Prefetch instructions for Pentium III (+) and AMD Athlon (+) 630 * 631 * It's not worth to care about 3dnow prefetches for the K6 632 * because they are microcoded there and very slow. 633 */ 634 static inline void prefetch(const void *x) 635 { 636 alternative_input(BASE_PREFETCH, "prefetchnta %1", 637 X86_FEATURE_XMM, 638 "m" (*(const char *)x)); 639 } 640 641 /* 642 * 3dnow prefetch to get an exclusive cache line. 643 * Useful for spinlocks to avoid one state transition in the 644 * cache coherency protocol: 645 */ 646 static __always_inline void prefetchw(const void *x) 647 { 648 alternative_input(BASE_PREFETCH, "prefetchw %1", 649 X86_FEATURE_3DNOWPREFETCH, 650 "m" (*(const char *)x)); 651 } 652 653 #define TOP_OF_INIT_STACK ((unsigned long)&init_stack + sizeof(init_stack) - \ 654 TOP_OF_KERNEL_STACK_PADDING) 655 656 #define task_top_of_stack(task) ((unsigned long)(task_pt_regs(task) + 1)) 657 658 #define task_pt_regs(task) \ 659 ({ \ 660 unsigned long __ptr = (unsigned long)task_stack_page(task); \ 661 __ptr += THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING; \ 662 ((struct pt_regs *)__ptr) - 1; \ 663 }) 664 665 #ifdef CONFIG_X86_32 666 #define INIT_THREAD { \ 667 .sp0 = TOP_OF_INIT_STACK, \ 668 .sysenter_cs = __KERNEL_CS, \ 669 } 670 671 #define KSTK_ESP(task) (task_pt_regs(task)->sp) 672 673 #else 674 extern unsigned long __top_init_kernel_stack[]; 675 676 #define INIT_THREAD { \ 677 .sp = (unsigned long)&__top_init_kernel_stack, \ 678 } 679 680 extern unsigned long KSTK_ESP(struct task_struct *task); 681 682 #endif /* CONFIG_X86_64 */ 683 684 extern void start_thread(struct pt_regs *regs, unsigned long new_ip, 685 unsigned long new_sp); 686 687 /* 688 * This decides where the kernel will search for a free chunk of vm 689 * space during mmap's. 690 */ 691 #define __TASK_UNMAPPED_BASE(task_size) (PAGE_ALIGN(task_size / 3)) 692 #define TASK_UNMAPPED_BASE __TASK_UNMAPPED_BASE(TASK_SIZE_LOW) 693 694 #define KSTK_EIP(task) (task_pt_regs(task)->ip) 695 696 /* Get/set a process' ability to use the timestamp counter instruction */ 697 #define GET_TSC_CTL(adr) get_tsc_mode((adr)) 698 #define SET_TSC_CTL(val) set_tsc_mode((val)) 699 700 extern int get_tsc_mode(unsigned long adr); 701 extern int set_tsc_mode(unsigned int val); 702 703 DECLARE_PER_CPU(u64, msr_misc_features_shadow); 704 705 static inline u32 per_cpu_llc_id(unsigned int cpu) 706 { 707 return per_cpu(cpu_info.topo.llc_id, cpu); 708 } 709 710 static inline u32 per_cpu_l2c_id(unsigned int cpu) 711 { 712 return per_cpu(cpu_info.topo.l2c_id, cpu); 713 } 714 715 #ifdef CONFIG_CPU_SUP_AMD 716 /* 717 * Issue a DIV 0/1 insn to clear any division data from previous DIV 718 * operations. 719 */ 720 static __always_inline void amd_clear_divider(void) 721 { 722 asm volatile(ALTERNATIVE("", "div %2\n\t", X86_BUG_DIV0) 723 :: "a" (0), "d" (0), "r" (1)); 724 } 725 726 extern void amd_check_microcode(void); 727 #else 728 static inline void amd_clear_divider(void) { } 729 static inline void amd_check_microcode(void) { } 730 #endif 731 732 extern unsigned long arch_align_stack(unsigned long sp); 733 void free_init_pages(const char *what, unsigned long begin, unsigned long end); 734 extern void free_kernel_image_pages(const char *what, void *begin, void *end); 735 736 void default_idle(void); 737 #ifdef CONFIG_XEN 738 bool xen_set_default_idle(void); 739 #else 740 #define xen_set_default_idle 0 741 #endif 742 743 void __noreturn stop_this_cpu(void *dummy); 744 void microcode_check(struct cpuinfo_x86 *prev_info); 745 void store_cpu_caps(struct cpuinfo_x86 *info); 746 747 enum l1tf_mitigations { 748 L1TF_MITIGATION_OFF, 749 L1TF_MITIGATION_FLUSH_NOWARN, 750 L1TF_MITIGATION_FLUSH, 751 L1TF_MITIGATION_FLUSH_NOSMT, 752 L1TF_MITIGATION_FULL, 753 L1TF_MITIGATION_FULL_FORCE 754 }; 755 756 extern enum l1tf_mitigations l1tf_mitigation; 757 758 enum mds_mitigations { 759 MDS_MITIGATION_OFF, 760 MDS_MITIGATION_FULL, 761 MDS_MITIGATION_VMWERV, 762 }; 763 764 extern bool gds_ucode_mitigated(void); 765 766 /* 767 * Make previous memory operations globally visible before 768 * a WRMSR. 769 * 770 * MFENCE makes writes visible, but only affects load/store 771 * instructions. WRMSR is unfortunately not a load/store 772 * instruction and is unaffected by MFENCE. The LFENCE ensures 773 * that the WRMSR is not reordered. 774 * 775 * Most WRMSRs are full serializing instructions themselves and 776 * do not require this barrier. This is only required for the 777 * IA32_TSC_DEADLINE and X2APIC MSRs. 778 */ 779 static inline void weak_wrmsr_fence(void) 780 { 781 alternative("mfence; lfence", "", ALT_NOT(X86_FEATURE_APIC_MSRS_FENCE)); 782 } 783 784 #endif /* _ASM_X86_PROCESSOR_H */ 785