1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _ASM_X86_PROCESSOR_H 3 #define _ASM_X86_PROCESSOR_H 4 5 #include <asm/processor-flags.h> 6 7 /* Forward declaration, a strange C thing */ 8 struct task_struct; 9 struct mm_struct; 10 struct vm86; 11 12 #include <asm/math_emu.h> 13 #include <asm/segment.h> 14 #include <asm/types.h> 15 #include <uapi/asm/sigcontext.h> 16 #include <asm/current.h> 17 #include <asm/cpufeatures.h> 18 #include <asm/page.h> 19 #include <asm/pgtable_types.h> 20 #include <asm/percpu.h> 21 #include <asm/msr.h> 22 #include <asm/desc_defs.h> 23 #include <asm/nops.h> 24 #include <asm/special_insns.h> 25 #include <asm/fpu/types.h> 26 #include <asm/unwind_hints.h> 27 28 #include <linux/personality.h> 29 #include <linux/cache.h> 30 #include <linux/threads.h> 31 #include <linux/math64.h> 32 #include <linux/err.h> 33 #include <linux/irqflags.h> 34 #include <linux/mem_encrypt.h> 35 36 /* 37 * We handle most unaligned accesses in hardware. On the other hand 38 * unaligned DMA can be quite expensive on some Nehalem processors. 39 * 40 * Based on this we disable the IP header alignment in network drivers. 41 */ 42 #define NET_IP_ALIGN 0 43 44 #define HBP_NUM 4 45 /* 46 * Default implementation of macro that returns current 47 * instruction pointer ("program counter"). 48 */ 49 static inline void *current_text_addr(void) 50 { 51 void *pc; 52 53 asm volatile("mov $1f, %0; 1:":"=r" (pc)); 54 55 return pc; 56 } 57 58 /* 59 * These alignment constraints are for performance in the vSMP case, 60 * but in the task_struct case we must also meet hardware imposed 61 * alignment requirements of the FPU state: 62 */ 63 #ifdef CONFIG_X86_VSMP 64 # define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT) 65 # define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT) 66 #else 67 # define ARCH_MIN_TASKALIGN __alignof__(union fpregs_state) 68 # define ARCH_MIN_MMSTRUCT_ALIGN 0 69 #endif 70 71 enum tlb_infos { 72 ENTRIES, 73 NR_INFO 74 }; 75 76 extern u16 __read_mostly tlb_lli_4k[NR_INFO]; 77 extern u16 __read_mostly tlb_lli_2m[NR_INFO]; 78 extern u16 __read_mostly tlb_lli_4m[NR_INFO]; 79 extern u16 __read_mostly tlb_lld_4k[NR_INFO]; 80 extern u16 __read_mostly tlb_lld_2m[NR_INFO]; 81 extern u16 __read_mostly tlb_lld_4m[NR_INFO]; 82 extern u16 __read_mostly tlb_lld_1g[NR_INFO]; 83 84 /* 85 * CPU type and hardware bug flags. Kept separately for each CPU. 86 * Members of this structure are referenced in head_32.S, so think twice 87 * before touching them. [mj] 88 */ 89 90 struct cpuinfo_x86 { 91 __u8 x86; /* CPU family */ 92 __u8 x86_vendor; /* CPU vendor */ 93 __u8 x86_model; 94 __u8 x86_stepping; 95 #ifdef CONFIG_X86_64 96 /* Number of 4K pages in DTLB/ITLB combined(in pages): */ 97 int x86_tlbsize; 98 #endif 99 __u8 x86_virt_bits; 100 __u8 x86_phys_bits; 101 /* CPUID returned core id bits: */ 102 __u8 x86_coreid_bits; 103 __u8 cu_id; 104 /* Max extended CPUID function supported: */ 105 __u32 extended_cpuid_level; 106 /* Maximum supported CPUID level, -1=no CPUID: */ 107 int cpuid_level; 108 __u32 x86_capability[NCAPINTS + NBUGINTS]; 109 char x86_vendor_id[16]; 110 char x86_model_id[64]; 111 /* in KB - valid for CPUS which support this call: */ 112 unsigned int x86_cache_size; 113 int x86_cache_alignment; /* In bytes */ 114 /* Cache QoS architectural values: */ 115 int x86_cache_max_rmid; /* max index */ 116 int x86_cache_occ_scale; /* scale to bytes */ 117 int x86_power; 118 unsigned long loops_per_jiffy; 119 /* cpuid returned max cores value: */ 120 u16 x86_max_cores; 121 u16 apicid; 122 u16 initial_apicid; 123 u16 x86_clflush_size; 124 /* number of cores as seen by the OS: */ 125 u16 booted_cores; 126 /* Physical processor id: */ 127 u16 phys_proc_id; 128 /* Logical processor id: */ 129 u16 logical_proc_id; 130 /* Core id: */ 131 u16 cpu_core_id; 132 /* Index into per_cpu list: */ 133 u16 cpu_index; 134 u32 microcode; 135 /* Address space bits used by the cache internally */ 136 u8 x86_cache_bits; 137 unsigned initialized : 1; 138 } __randomize_layout; 139 140 struct cpuid_regs { 141 u32 eax, ebx, ecx, edx; 142 }; 143 144 enum cpuid_regs_idx { 145 CPUID_EAX = 0, 146 CPUID_EBX, 147 CPUID_ECX, 148 CPUID_EDX, 149 }; 150 151 #define X86_VENDOR_INTEL 0 152 #define X86_VENDOR_CYRIX 1 153 #define X86_VENDOR_AMD 2 154 #define X86_VENDOR_UMC 3 155 #define X86_VENDOR_CENTAUR 5 156 #define X86_VENDOR_TRANSMETA 7 157 #define X86_VENDOR_NSC 8 158 #define X86_VENDOR_HYGON 9 159 #define X86_VENDOR_NUM 10 160 161 #define X86_VENDOR_UNKNOWN 0xff 162 163 /* 164 * capabilities of CPUs 165 */ 166 extern struct cpuinfo_x86 boot_cpu_data; 167 extern struct cpuinfo_x86 new_cpu_data; 168 169 extern struct x86_hw_tss doublefault_tss; 170 extern __u32 cpu_caps_cleared[NCAPINTS + NBUGINTS]; 171 extern __u32 cpu_caps_set[NCAPINTS + NBUGINTS]; 172 173 #ifdef CONFIG_SMP 174 DECLARE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info); 175 #define cpu_data(cpu) per_cpu(cpu_info, cpu) 176 #else 177 #define cpu_info boot_cpu_data 178 #define cpu_data(cpu) boot_cpu_data 179 #endif 180 181 extern const struct seq_operations cpuinfo_op; 182 183 #define cache_line_size() (boot_cpu_data.x86_cache_alignment) 184 185 extern void cpu_detect(struct cpuinfo_x86 *c); 186 187 static inline unsigned long long l1tf_pfn_limit(void) 188 { 189 return BIT_ULL(boot_cpu_data.x86_cache_bits - 1 - PAGE_SHIFT); 190 } 191 192 extern void early_cpu_init(void); 193 extern void identify_boot_cpu(void); 194 extern void identify_secondary_cpu(struct cpuinfo_x86 *); 195 extern void print_cpu_info(struct cpuinfo_x86 *); 196 void print_cpu_msr(struct cpuinfo_x86 *); 197 198 #ifdef CONFIG_X86_32 199 extern int have_cpuid_p(void); 200 #else 201 static inline int have_cpuid_p(void) 202 { 203 return 1; 204 } 205 #endif 206 static inline void native_cpuid(unsigned int *eax, unsigned int *ebx, 207 unsigned int *ecx, unsigned int *edx) 208 { 209 /* ecx is often an input as well as an output. */ 210 asm volatile("cpuid" 211 : "=a" (*eax), 212 "=b" (*ebx), 213 "=c" (*ecx), 214 "=d" (*edx) 215 : "0" (*eax), "2" (*ecx) 216 : "memory"); 217 } 218 219 #define native_cpuid_reg(reg) \ 220 static inline unsigned int native_cpuid_##reg(unsigned int op) \ 221 { \ 222 unsigned int eax = op, ebx, ecx = 0, edx; \ 223 \ 224 native_cpuid(&eax, &ebx, &ecx, &edx); \ 225 \ 226 return reg; \ 227 } 228 229 /* 230 * Native CPUID functions returning a single datum. 231 */ 232 native_cpuid_reg(eax) 233 native_cpuid_reg(ebx) 234 native_cpuid_reg(ecx) 235 native_cpuid_reg(edx) 236 237 /* 238 * Friendlier CR3 helpers. 239 */ 240 static inline unsigned long read_cr3_pa(void) 241 { 242 return __read_cr3() & CR3_ADDR_MASK; 243 } 244 245 static inline unsigned long native_read_cr3_pa(void) 246 { 247 return __native_read_cr3() & CR3_ADDR_MASK; 248 } 249 250 static inline void load_cr3(pgd_t *pgdir) 251 { 252 write_cr3(__sme_pa(pgdir)); 253 } 254 255 /* 256 * Note that while the legacy 'TSS' name comes from 'Task State Segment', 257 * on modern x86 CPUs the TSS also holds information important to 64-bit mode, 258 * unrelated to the task-switch mechanism: 259 */ 260 #ifdef CONFIG_X86_32 261 /* This is the TSS defined by the hardware. */ 262 struct x86_hw_tss { 263 unsigned short back_link, __blh; 264 unsigned long sp0; 265 unsigned short ss0, __ss0h; 266 unsigned long sp1; 267 268 /* 269 * We don't use ring 1, so ss1 is a convenient scratch space in 270 * the same cacheline as sp0. We use ss1 to cache the value in 271 * MSR_IA32_SYSENTER_CS. When we context switch 272 * MSR_IA32_SYSENTER_CS, we first check if the new value being 273 * written matches ss1, and, if it's not, then we wrmsr the new 274 * value and update ss1. 275 * 276 * The only reason we context switch MSR_IA32_SYSENTER_CS is 277 * that we set it to zero in vm86 tasks to avoid corrupting the 278 * stack if we were to go through the sysenter path from vm86 279 * mode. 280 */ 281 unsigned short ss1; /* MSR_IA32_SYSENTER_CS */ 282 283 unsigned short __ss1h; 284 unsigned long sp2; 285 unsigned short ss2, __ss2h; 286 unsigned long __cr3; 287 unsigned long ip; 288 unsigned long flags; 289 unsigned long ax; 290 unsigned long cx; 291 unsigned long dx; 292 unsigned long bx; 293 unsigned long sp; 294 unsigned long bp; 295 unsigned long si; 296 unsigned long di; 297 unsigned short es, __esh; 298 unsigned short cs, __csh; 299 unsigned short ss, __ssh; 300 unsigned short ds, __dsh; 301 unsigned short fs, __fsh; 302 unsigned short gs, __gsh; 303 unsigned short ldt, __ldth; 304 unsigned short trace; 305 unsigned short io_bitmap_base; 306 307 } __attribute__((packed)); 308 #else 309 struct x86_hw_tss { 310 u32 reserved1; 311 u64 sp0; 312 313 /* 314 * We store cpu_current_top_of_stack in sp1 so it's always accessible. 315 * Linux does not use ring 1, so sp1 is not otherwise needed. 316 */ 317 u64 sp1; 318 319 /* 320 * Since Linux does not use ring 2, the 'sp2' slot is unused by 321 * hardware. entry_SYSCALL_64 uses it as scratch space to stash 322 * the user RSP value. 323 */ 324 u64 sp2; 325 326 u64 reserved2; 327 u64 ist[7]; 328 u32 reserved3; 329 u32 reserved4; 330 u16 reserved5; 331 u16 io_bitmap_base; 332 333 } __attribute__((packed)); 334 #endif 335 336 /* 337 * IO-bitmap sizes: 338 */ 339 #define IO_BITMAP_BITS 65536 340 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8) 341 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long)) 342 #define IO_BITMAP_OFFSET (offsetof(struct tss_struct, io_bitmap) - offsetof(struct tss_struct, x86_tss)) 343 #define INVALID_IO_BITMAP_OFFSET 0x8000 344 345 struct entry_stack { 346 unsigned long words[64]; 347 }; 348 349 struct entry_stack_page { 350 struct entry_stack stack; 351 } __aligned(PAGE_SIZE); 352 353 struct tss_struct { 354 /* 355 * The fixed hardware portion. This must not cross a page boundary 356 * at risk of violating the SDM's advice and potentially triggering 357 * errata. 358 */ 359 struct x86_hw_tss x86_tss; 360 361 /* 362 * The extra 1 is there because the CPU will access an 363 * additional byte beyond the end of the IO permission 364 * bitmap. The extra byte must be all 1 bits, and must 365 * be within the limit. 366 */ 367 unsigned long io_bitmap[IO_BITMAP_LONGS + 1]; 368 } __aligned(PAGE_SIZE); 369 370 DECLARE_PER_CPU_PAGE_ALIGNED(struct tss_struct, cpu_tss_rw); 371 372 /* 373 * sizeof(unsigned long) coming from an extra "long" at the end 374 * of the iobitmap. 375 * 376 * -1? seg base+limit should be pointing to the address of the 377 * last valid byte 378 */ 379 #define __KERNEL_TSS_LIMIT \ 380 (IO_BITMAP_OFFSET + IO_BITMAP_BYTES + sizeof(unsigned long) - 1) 381 382 #ifdef CONFIG_X86_32 383 DECLARE_PER_CPU(unsigned long, cpu_current_top_of_stack); 384 #else 385 /* The RO copy can't be accessed with this_cpu_xyz(), so use the RW copy. */ 386 #define cpu_current_top_of_stack cpu_tss_rw.x86_tss.sp1 387 #endif 388 389 /* 390 * Save the original ist values for checking stack pointers during debugging 391 */ 392 struct orig_ist { 393 unsigned long ist[7]; 394 }; 395 396 #ifdef CONFIG_X86_64 397 DECLARE_PER_CPU(struct orig_ist, orig_ist); 398 399 union irq_stack_union { 400 char irq_stack[IRQ_STACK_SIZE]; 401 /* 402 * GCC hardcodes the stack canary as %gs:40. Since the 403 * irq_stack is the object at %gs:0, we reserve the bottom 404 * 48 bytes of the irq stack for the canary. 405 */ 406 struct { 407 char gs_base[40]; 408 unsigned long stack_canary; 409 }; 410 }; 411 412 DECLARE_PER_CPU_FIRST(union irq_stack_union, irq_stack_union) __visible; 413 DECLARE_INIT_PER_CPU(irq_stack_union); 414 415 static inline unsigned long cpu_kernelmode_gs_base(int cpu) 416 { 417 return (unsigned long)per_cpu(irq_stack_union.gs_base, cpu); 418 } 419 420 DECLARE_PER_CPU(char *, irq_stack_ptr); 421 DECLARE_PER_CPU(unsigned int, irq_count); 422 extern asmlinkage void ignore_sysret(void); 423 424 #if IS_ENABLED(CONFIG_KVM) 425 /* Save actual FS/GS selectors and bases to current->thread */ 426 void save_fsgs_for_kvm(void); 427 #endif 428 #else /* X86_64 */ 429 #ifdef CONFIG_STACKPROTECTOR 430 /* 431 * Make sure stack canary segment base is cached-aligned: 432 * "For Intel Atom processors, avoid non zero segment base address 433 * that is not aligned to cache line boundary at all cost." 434 * (Optim Ref Manual Assembly/Compiler Coding Rule 15.) 435 */ 436 struct stack_canary { 437 char __pad[20]; /* canary at %gs:20 */ 438 unsigned long canary; 439 }; 440 DECLARE_PER_CPU_ALIGNED(struct stack_canary, stack_canary); 441 #endif 442 /* 443 * per-CPU IRQ handling stacks 444 */ 445 struct irq_stack { 446 u32 stack[THREAD_SIZE/sizeof(u32)]; 447 } __aligned(THREAD_SIZE); 448 449 DECLARE_PER_CPU(struct irq_stack *, hardirq_stack); 450 DECLARE_PER_CPU(struct irq_stack *, softirq_stack); 451 #endif /* X86_64 */ 452 453 extern unsigned int fpu_kernel_xstate_size; 454 extern unsigned int fpu_user_xstate_size; 455 456 struct perf_event; 457 458 typedef struct { 459 unsigned long seg; 460 } mm_segment_t; 461 462 struct thread_struct { 463 /* Cached TLS descriptors: */ 464 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES]; 465 #ifdef CONFIG_X86_32 466 unsigned long sp0; 467 #endif 468 unsigned long sp; 469 #ifdef CONFIG_X86_32 470 unsigned long sysenter_cs; 471 #else 472 unsigned short es; 473 unsigned short ds; 474 unsigned short fsindex; 475 unsigned short gsindex; 476 #endif 477 478 #ifdef CONFIG_X86_64 479 unsigned long fsbase; 480 unsigned long gsbase; 481 #else 482 /* 483 * XXX: this could presumably be unsigned short. Alternatively, 484 * 32-bit kernels could be taught to use fsindex instead. 485 */ 486 unsigned long fs; 487 unsigned long gs; 488 #endif 489 490 /* Save middle states of ptrace breakpoints */ 491 struct perf_event *ptrace_bps[HBP_NUM]; 492 /* Debug status used for traps, single steps, etc... */ 493 unsigned long debugreg6; 494 /* Keep track of the exact dr7 value set by the user */ 495 unsigned long ptrace_dr7; 496 /* Fault info: */ 497 unsigned long cr2; 498 unsigned long trap_nr; 499 unsigned long error_code; 500 #ifdef CONFIG_VM86 501 /* Virtual 86 mode info */ 502 struct vm86 *vm86; 503 #endif 504 /* IO permissions: */ 505 unsigned long *io_bitmap_ptr; 506 unsigned long iopl; 507 /* Max allowed port in the bitmap, in bytes: */ 508 unsigned io_bitmap_max; 509 510 mm_segment_t addr_limit; 511 512 unsigned int sig_on_uaccess_err:1; 513 unsigned int uaccess_err:1; /* uaccess failed */ 514 515 /* Floating point and extended processor state */ 516 struct fpu fpu; 517 /* 518 * WARNING: 'fpu' is dynamically-sized. It *MUST* be at 519 * the end. 520 */ 521 }; 522 523 /* Whitelist the FPU state from the task_struct for hardened usercopy. */ 524 static inline void arch_thread_struct_whitelist(unsigned long *offset, 525 unsigned long *size) 526 { 527 *offset = offsetof(struct thread_struct, fpu.state); 528 *size = fpu_kernel_xstate_size; 529 } 530 531 /* 532 * Thread-synchronous status. 533 * 534 * This is different from the flags in that nobody else 535 * ever touches our thread-synchronous status, so we don't 536 * have to worry about atomic accesses. 537 */ 538 #define TS_COMPAT 0x0002 /* 32bit syscall active (64BIT)*/ 539 540 /* 541 * Set IOPL bits in EFLAGS from given mask 542 */ 543 static inline void native_set_iopl_mask(unsigned mask) 544 { 545 #ifdef CONFIG_X86_32 546 unsigned int reg; 547 548 asm volatile ("pushfl;" 549 "popl %0;" 550 "andl %1, %0;" 551 "orl %2, %0;" 552 "pushl %0;" 553 "popfl" 554 : "=&r" (reg) 555 : "i" (~X86_EFLAGS_IOPL), "r" (mask)); 556 #endif 557 } 558 559 static inline void 560 native_load_sp0(unsigned long sp0) 561 { 562 this_cpu_write(cpu_tss_rw.x86_tss.sp0, sp0); 563 } 564 565 static inline void native_swapgs(void) 566 { 567 #ifdef CONFIG_X86_64 568 asm volatile("swapgs" ::: "memory"); 569 #endif 570 } 571 572 static inline unsigned long current_top_of_stack(void) 573 { 574 /* 575 * We can't read directly from tss.sp0: sp0 on x86_32 is special in 576 * and around vm86 mode and sp0 on x86_64 is special because of the 577 * entry trampoline. 578 */ 579 return this_cpu_read_stable(cpu_current_top_of_stack); 580 } 581 582 static inline bool on_thread_stack(void) 583 { 584 return (unsigned long)(current_top_of_stack() - 585 current_stack_pointer) < THREAD_SIZE; 586 } 587 588 #ifdef CONFIG_PARAVIRT_XXL 589 #include <asm/paravirt.h> 590 #else 591 #define __cpuid native_cpuid 592 593 static inline void load_sp0(unsigned long sp0) 594 { 595 native_load_sp0(sp0); 596 } 597 598 #define set_iopl_mask native_set_iopl_mask 599 #endif /* CONFIG_PARAVIRT_XXL */ 600 601 /* Free all resources held by a thread. */ 602 extern void release_thread(struct task_struct *); 603 604 unsigned long get_wchan(struct task_struct *p); 605 606 /* 607 * Generic CPUID function 608 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx 609 * resulting in stale register contents being returned. 610 */ 611 static inline void cpuid(unsigned int op, 612 unsigned int *eax, unsigned int *ebx, 613 unsigned int *ecx, unsigned int *edx) 614 { 615 *eax = op; 616 *ecx = 0; 617 __cpuid(eax, ebx, ecx, edx); 618 } 619 620 /* Some CPUID calls want 'count' to be placed in ecx */ 621 static inline void cpuid_count(unsigned int op, int count, 622 unsigned int *eax, unsigned int *ebx, 623 unsigned int *ecx, unsigned int *edx) 624 { 625 *eax = op; 626 *ecx = count; 627 __cpuid(eax, ebx, ecx, edx); 628 } 629 630 /* 631 * CPUID functions returning a single datum 632 */ 633 static inline unsigned int cpuid_eax(unsigned int op) 634 { 635 unsigned int eax, ebx, ecx, edx; 636 637 cpuid(op, &eax, &ebx, &ecx, &edx); 638 639 return eax; 640 } 641 642 static inline unsigned int cpuid_ebx(unsigned int op) 643 { 644 unsigned int eax, ebx, ecx, edx; 645 646 cpuid(op, &eax, &ebx, &ecx, &edx); 647 648 return ebx; 649 } 650 651 static inline unsigned int cpuid_ecx(unsigned int op) 652 { 653 unsigned int eax, ebx, ecx, edx; 654 655 cpuid(op, &eax, &ebx, &ecx, &edx); 656 657 return ecx; 658 } 659 660 static inline unsigned int cpuid_edx(unsigned int op) 661 { 662 unsigned int eax, ebx, ecx, edx; 663 664 cpuid(op, &eax, &ebx, &ecx, &edx); 665 666 return edx; 667 } 668 669 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */ 670 static __always_inline void rep_nop(void) 671 { 672 asm volatile("rep; nop" ::: "memory"); 673 } 674 675 static __always_inline void cpu_relax(void) 676 { 677 rep_nop(); 678 } 679 680 /* 681 * This function forces the icache and prefetched instruction stream to 682 * catch up with reality in two very specific cases: 683 * 684 * a) Text was modified using one virtual address and is about to be executed 685 * from the same physical page at a different virtual address. 686 * 687 * b) Text was modified on a different CPU, may subsequently be 688 * executed on this CPU, and you want to make sure the new version 689 * gets executed. This generally means you're calling this in a IPI. 690 * 691 * If you're calling this for a different reason, you're probably doing 692 * it wrong. 693 */ 694 static inline void sync_core(void) 695 { 696 /* 697 * There are quite a few ways to do this. IRET-to-self is nice 698 * because it works on every CPU, at any CPL (so it's compatible 699 * with paravirtualization), and it never exits to a hypervisor. 700 * The only down sides are that it's a bit slow (it seems to be 701 * a bit more than 2x slower than the fastest options) and that 702 * it unmasks NMIs. The "push %cs" is needed because, in 703 * paravirtual environments, __KERNEL_CS may not be a valid CS 704 * value when we do IRET directly. 705 * 706 * In case NMI unmasking or performance ever becomes a problem, 707 * the next best option appears to be MOV-to-CR2 and an 708 * unconditional jump. That sequence also works on all CPUs, 709 * but it will fault at CPL3 (i.e. Xen PV). 710 * 711 * CPUID is the conventional way, but it's nasty: it doesn't 712 * exist on some 486-like CPUs, and it usually exits to a 713 * hypervisor. 714 * 715 * Like all of Linux's memory ordering operations, this is a 716 * compiler barrier as well. 717 */ 718 #ifdef CONFIG_X86_32 719 asm volatile ( 720 "pushfl\n\t" 721 "pushl %%cs\n\t" 722 "pushl $1f\n\t" 723 "iret\n\t" 724 "1:" 725 : ASM_CALL_CONSTRAINT : : "memory"); 726 #else 727 unsigned int tmp; 728 729 asm volatile ( 730 UNWIND_HINT_SAVE 731 "mov %%ss, %0\n\t" 732 "pushq %q0\n\t" 733 "pushq %%rsp\n\t" 734 "addq $8, (%%rsp)\n\t" 735 "pushfq\n\t" 736 "mov %%cs, %0\n\t" 737 "pushq %q0\n\t" 738 "pushq $1f\n\t" 739 "iretq\n\t" 740 UNWIND_HINT_RESTORE 741 "1:" 742 : "=&r" (tmp), ASM_CALL_CONSTRAINT : : "cc", "memory"); 743 #endif 744 } 745 746 extern void select_idle_routine(const struct cpuinfo_x86 *c); 747 extern void amd_e400_c1e_apic_setup(void); 748 749 extern unsigned long boot_option_idle_override; 750 751 enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_NOMWAIT, 752 IDLE_POLL}; 753 754 extern void enable_sep_cpu(void); 755 extern int sysenter_setup(void); 756 757 void early_trap_pf_init(void); 758 759 /* Defined in head.S */ 760 extern struct desc_ptr early_gdt_descr; 761 762 extern void switch_to_new_gdt(int); 763 extern void load_direct_gdt(int); 764 extern void load_fixmap_gdt(int); 765 extern void load_percpu_segment(int); 766 extern void cpu_init(void); 767 768 static inline unsigned long get_debugctlmsr(void) 769 { 770 unsigned long debugctlmsr = 0; 771 772 #ifndef CONFIG_X86_DEBUGCTLMSR 773 if (boot_cpu_data.x86 < 6) 774 return 0; 775 #endif 776 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr); 777 778 return debugctlmsr; 779 } 780 781 static inline void update_debugctlmsr(unsigned long debugctlmsr) 782 { 783 #ifndef CONFIG_X86_DEBUGCTLMSR 784 if (boot_cpu_data.x86 < 6) 785 return; 786 #endif 787 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr); 788 } 789 790 extern void set_task_blockstep(struct task_struct *task, bool on); 791 792 /* Boot loader type from the setup header: */ 793 extern int bootloader_type; 794 extern int bootloader_version; 795 796 extern char ignore_fpu_irq; 797 798 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1 799 #define ARCH_HAS_PREFETCHW 800 #define ARCH_HAS_SPINLOCK_PREFETCH 801 802 #ifdef CONFIG_X86_32 803 # define BASE_PREFETCH "" 804 # define ARCH_HAS_PREFETCH 805 #else 806 # define BASE_PREFETCH "prefetcht0 %P1" 807 #endif 808 809 /* 810 * Prefetch instructions for Pentium III (+) and AMD Athlon (+) 811 * 812 * It's not worth to care about 3dnow prefetches for the K6 813 * because they are microcoded there and very slow. 814 */ 815 static inline void prefetch(const void *x) 816 { 817 alternative_input(BASE_PREFETCH, "prefetchnta %P1", 818 X86_FEATURE_XMM, 819 "m" (*(const char *)x)); 820 } 821 822 /* 823 * 3dnow prefetch to get an exclusive cache line. 824 * Useful for spinlocks to avoid one state transition in the 825 * cache coherency protocol: 826 */ 827 static inline void prefetchw(const void *x) 828 { 829 alternative_input(BASE_PREFETCH, "prefetchw %P1", 830 X86_FEATURE_3DNOWPREFETCH, 831 "m" (*(const char *)x)); 832 } 833 834 static inline void spin_lock_prefetch(const void *x) 835 { 836 prefetchw(x); 837 } 838 839 #define TOP_OF_INIT_STACK ((unsigned long)&init_stack + sizeof(init_stack) - \ 840 TOP_OF_KERNEL_STACK_PADDING) 841 842 #define task_top_of_stack(task) ((unsigned long)(task_pt_regs(task) + 1)) 843 844 #define task_pt_regs(task) \ 845 ({ \ 846 unsigned long __ptr = (unsigned long)task_stack_page(task); \ 847 __ptr += THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING; \ 848 ((struct pt_regs *)__ptr) - 1; \ 849 }) 850 851 #ifdef CONFIG_X86_32 852 /* 853 * User space process size: 3GB (default). 854 */ 855 #define IA32_PAGE_OFFSET PAGE_OFFSET 856 #define TASK_SIZE PAGE_OFFSET 857 #define TASK_SIZE_LOW TASK_SIZE 858 #define TASK_SIZE_MAX TASK_SIZE 859 #define DEFAULT_MAP_WINDOW TASK_SIZE 860 #define STACK_TOP TASK_SIZE 861 #define STACK_TOP_MAX STACK_TOP 862 863 #define INIT_THREAD { \ 864 .sp0 = TOP_OF_INIT_STACK, \ 865 .sysenter_cs = __KERNEL_CS, \ 866 .io_bitmap_ptr = NULL, \ 867 .addr_limit = KERNEL_DS, \ 868 } 869 870 #define KSTK_ESP(task) (task_pt_regs(task)->sp) 871 872 #else 873 /* 874 * User space process size. This is the first address outside the user range. 875 * There are a few constraints that determine this: 876 * 877 * On Intel CPUs, if a SYSCALL instruction is at the highest canonical 878 * address, then that syscall will enter the kernel with a 879 * non-canonical return address, and SYSRET will explode dangerously. 880 * We avoid this particular problem by preventing anything executable 881 * from being mapped at the maximum canonical address. 882 * 883 * On AMD CPUs in the Ryzen family, there's a nasty bug in which the 884 * CPUs malfunction if they execute code from the highest canonical page. 885 * They'll speculate right off the end of the canonical space, and 886 * bad things happen. This is worked around in the same way as the 887 * Intel problem. 888 * 889 * With page table isolation enabled, we map the LDT in ... [stay tuned] 890 */ 891 #define TASK_SIZE_MAX ((1UL << __VIRTUAL_MASK_SHIFT) - PAGE_SIZE) 892 893 #define DEFAULT_MAP_WINDOW ((1UL << 47) - PAGE_SIZE) 894 895 /* This decides where the kernel will search for a free chunk of vm 896 * space during mmap's. 897 */ 898 #define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? \ 899 0xc0000000 : 0xFFFFe000) 900 901 #define TASK_SIZE_LOW (test_thread_flag(TIF_ADDR32) ? \ 902 IA32_PAGE_OFFSET : DEFAULT_MAP_WINDOW) 903 #define TASK_SIZE (test_thread_flag(TIF_ADDR32) ? \ 904 IA32_PAGE_OFFSET : TASK_SIZE_MAX) 905 #define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_ADDR32)) ? \ 906 IA32_PAGE_OFFSET : TASK_SIZE_MAX) 907 908 #define STACK_TOP TASK_SIZE_LOW 909 #define STACK_TOP_MAX TASK_SIZE_MAX 910 911 #define INIT_THREAD { \ 912 .addr_limit = KERNEL_DS, \ 913 } 914 915 extern unsigned long KSTK_ESP(struct task_struct *task); 916 917 #endif /* CONFIG_X86_64 */ 918 919 extern void start_thread(struct pt_regs *regs, unsigned long new_ip, 920 unsigned long new_sp); 921 922 /* 923 * This decides where the kernel will search for a free chunk of vm 924 * space during mmap's. 925 */ 926 #define __TASK_UNMAPPED_BASE(task_size) (PAGE_ALIGN(task_size / 3)) 927 #define TASK_UNMAPPED_BASE __TASK_UNMAPPED_BASE(TASK_SIZE_LOW) 928 929 #define KSTK_EIP(task) (task_pt_regs(task)->ip) 930 931 /* Get/set a process' ability to use the timestamp counter instruction */ 932 #define GET_TSC_CTL(adr) get_tsc_mode((adr)) 933 #define SET_TSC_CTL(val) set_tsc_mode((val)) 934 935 extern int get_tsc_mode(unsigned long adr); 936 extern int set_tsc_mode(unsigned int val); 937 938 DECLARE_PER_CPU(u64, msr_misc_features_shadow); 939 940 /* Register/unregister a process' MPX related resource */ 941 #define MPX_ENABLE_MANAGEMENT() mpx_enable_management() 942 #define MPX_DISABLE_MANAGEMENT() mpx_disable_management() 943 944 #ifdef CONFIG_X86_INTEL_MPX 945 extern int mpx_enable_management(void); 946 extern int mpx_disable_management(void); 947 #else 948 static inline int mpx_enable_management(void) 949 { 950 return -EINVAL; 951 } 952 static inline int mpx_disable_management(void) 953 { 954 return -EINVAL; 955 } 956 #endif /* CONFIG_X86_INTEL_MPX */ 957 958 #ifdef CONFIG_CPU_SUP_AMD 959 extern u16 amd_get_nb_id(int cpu); 960 extern u32 amd_get_nodes_per_socket(void); 961 #else 962 static inline u16 amd_get_nb_id(int cpu) { return 0; } 963 static inline u32 amd_get_nodes_per_socket(void) { return 0; } 964 #endif 965 966 static inline uint32_t hypervisor_cpuid_base(const char *sig, uint32_t leaves) 967 { 968 uint32_t base, eax, signature[3]; 969 970 for (base = 0x40000000; base < 0x40010000; base += 0x100) { 971 cpuid(base, &eax, &signature[0], &signature[1], &signature[2]); 972 973 if (!memcmp(sig, signature, 12) && 974 (leaves == 0 || ((eax - base) >= leaves))) 975 return base; 976 } 977 978 return 0; 979 } 980 981 extern unsigned long arch_align_stack(unsigned long sp); 982 extern void free_init_pages(char *what, unsigned long begin, unsigned long end); 983 extern void free_kernel_image_pages(void *begin, void *end); 984 985 void default_idle(void); 986 #ifdef CONFIG_XEN 987 bool xen_set_default_idle(void); 988 #else 989 #define xen_set_default_idle 0 990 #endif 991 992 void stop_this_cpu(void *dummy); 993 void df_debug(struct pt_regs *regs, long error_code); 994 void microcode_check(void); 995 996 enum l1tf_mitigations { 997 L1TF_MITIGATION_OFF, 998 L1TF_MITIGATION_FLUSH_NOWARN, 999 L1TF_MITIGATION_FLUSH, 1000 L1TF_MITIGATION_FLUSH_NOSMT, 1001 L1TF_MITIGATION_FULL, 1002 L1TF_MITIGATION_FULL_FORCE 1003 }; 1004 1005 extern enum l1tf_mitigations l1tf_mitigation; 1006 1007 #endif /* _ASM_X86_PROCESSOR_H */ 1008