1 #ifndef _ASM_X86_PROCESSOR_H 2 #define _ASM_X86_PROCESSOR_H 3 4 #include <asm/processor-flags.h> 5 6 /* Forward declaration, a strange C thing */ 7 struct task_struct; 8 struct mm_struct; 9 struct vm86; 10 11 #include <asm/math_emu.h> 12 #include <asm/segment.h> 13 #include <asm/types.h> 14 #include <uapi/asm/sigcontext.h> 15 #include <asm/current.h> 16 #include <asm/cpufeature.h> 17 #include <asm/page.h> 18 #include <asm/pgtable_types.h> 19 #include <asm/percpu.h> 20 #include <asm/msr.h> 21 #include <asm/desc_defs.h> 22 #include <asm/nops.h> 23 #include <asm/special_insns.h> 24 #include <asm/fpu/types.h> 25 26 #include <linux/personality.h> 27 #include <linux/cpumask.h> 28 #include <linux/cache.h> 29 #include <linux/threads.h> 30 #include <linux/math64.h> 31 #include <linux/err.h> 32 #include <linux/irqflags.h> 33 34 /* 35 * We handle most unaligned accesses in hardware. On the other hand 36 * unaligned DMA can be quite expensive on some Nehalem processors. 37 * 38 * Based on this we disable the IP header alignment in network drivers. 39 */ 40 #define NET_IP_ALIGN 0 41 42 #define HBP_NUM 4 43 /* 44 * Default implementation of macro that returns current 45 * instruction pointer ("program counter"). 46 */ 47 static inline void *current_text_addr(void) 48 { 49 void *pc; 50 51 asm volatile("mov $1f, %0; 1:":"=r" (pc)); 52 53 return pc; 54 } 55 56 /* 57 * These alignment constraints are for performance in the vSMP case, 58 * but in the task_struct case we must also meet hardware imposed 59 * alignment requirements of the FPU state: 60 */ 61 #ifdef CONFIG_X86_VSMP 62 # define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT) 63 # define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT) 64 #else 65 # define ARCH_MIN_TASKALIGN __alignof__(union fpregs_state) 66 # define ARCH_MIN_MMSTRUCT_ALIGN 0 67 #endif 68 69 enum tlb_infos { 70 ENTRIES, 71 NR_INFO 72 }; 73 74 extern u16 __read_mostly tlb_lli_4k[NR_INFO]; 75 extern u16 __read_mostly tlb_lli_2m[NR_INFO]; 76 extern u16 __read_mostly tlb_lli_4m[NR_INFO]; 77 extern u16 __read_mostly tlb_lld_4k[NR_INFO]; 78 extern u16 __read_mostly tlb_lld_2m[NR_INFO]; 79 extern u16 __read_mostly tlb_lld_4m[NR_INFO]; 80 extern u16 __read_mostly tlb_lld_1g[NR_INFO]; 81 82 /* 83 * CPU type and hardware bug flags. Kept separately for each CPU. 84 * Members of this structure are referenced in head.S, so think twice 85 * before touching them. [mj] 86 */ 87 88 struct cpuinfo_x86 { 89 __u8 x86; /* CPU family */ 90 __u8 x86_vendor; /* CPU vendor */ 91 __u8 x86_model; 92 __u8 x86_mask; 93 #ifdef CONFIG_X86_32 94 char wp_works_ok; /* It doesn't on 386's */ 95 96 /* Problems on some 486Dx4's and old 386's: */ 97 char rfu; 98 char pad0; 99 char pad1; 100 #else 101 /* Number of 4K pages in DTLB/ITLB combined(in pages): */ 102 int x86_tlbsize; 103 #endif 104 __u8 x86_virt_bits; 105 __u8 x86_phys_bits; 106 /* CPUID returned core id bits: */ 107 __u8 x86_coreid_bits; 108 /* Max extended CPUID function supported: */ 109 __u32 extended_cpuid_level; 110 /* Maximum supported CPUID level, -1=no CPUID: */ 111 int cpuid_level; 112 __u32 x86_capability[NCAPINTS + NBUGINTS]; 113 char x86_vendor_id[16]; 114 char x86_model_id[64]; 115 /* in KB - valid for CPUS which support this call: */ 116 int x86_cache_size; 117 int x86_cache_alignment; /* In bytes */ 118 /* Cache QoS architectural values: */ 119 int x86_cache_max_rmid; /* max index */ 120 int x86_cache_occ_scale; /* scale to bytes */ 121 int x86_power; 122 unsigned long loops_per_jiffy; 123 /* cpuid returned max cores value: */ 124 u16 x86_max_cores; 125 u16 apicid; 126 u16 initial_apicid; 127 u16 x86_clflush_size; 128 /* number of cores as seen by the OS: */ 129 u16 booted_cores; 130 /* Physical processor id: */ 131 u16 phys_proc_id; 132 /* Core id: */ 133 u16 cpu_core_id; 134 /* Compute unit id */ 135 u8 compute_unit_id; 136 /* Index into per_cpu list: */ 137 u16 cpu_index; 138 u32 microcode; 139 }; 140 141 #define X86_VENDOR_INTEL 0 142 #define X86_VENDOR_CYRIX 1 143 #define X86_VENDOR_AMD 2 144 #define X86_VENDOR_UMC 3 145 #define X86_VENDOR_CENTAUR 5 146 #define X86_VENDOR_TRANSMETA 7 147 #define X86_VENDOR_NSC 8 148 #define X86_VENDOR_NUM 9 149 150 #define X86_VENDOR_UNKNOWN 0xff 151 152 /* 153 * capabilities of CPUs 154 */ 155 extern struct cpuinfo_x86 boot_cpu_data; 156 extern struct cpuinfo_x86 new_cpu_data; 157 158 extern struct tss_struct doublefault_tss; 159 extern __u32 cpu_caps_cleared[NCAPINTS]; 160 extern __u32 cpu_caps_set[NCAPINTS]; 161 162 #ifdef CONFIG_SMP 163 DECLARE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info); 164 #define cpu_data(cpu) per_cpu(cpu_info, cpu) 165 #else 166 #define cpu_info boot_cpu_data 167 #define cpu_data(cpu) boot_cpu_data 168 #endif 169 170 extern const struct seq_operations cpuinfo_op; 171 172 #define cache_line_size() (boot_cpu_data.x86_cache_alignment) 173 174 extern void cpu_detect(struct cpuinfo_x86 *c); 175 176 extern void early_cpu_init(void); 177 extern void identify_boot_cpu(void); 178 extern void identify_secondary_cpu(struct cpuinfo_x86 *); 179 extern void print_cpu_info(struct cpuinfo_x86 *); 180 void print_cpu_msr(struct cpuinfo_x86 *); 181 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c); 182 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c); 183 extern void init_amd_cacheinfo(struct cpuinfo_x86 *c); 184 185 extern void detect_extended_topology(struct cpuinfo_x86 *c); 186 extern void detect_ht(struct cpuinfo_x86 *c); 187 188 #ifdef CONFIG_X86_32 189 extern int have_cpuid_p(void); 190 #else 191 static inline int have_cpuid_p(void) 192 { 193 return 1; 194 } 195 #endif 196 static inline void native_cpuid(unsigned int *eax, unsigned int *ebx, 197 unsigned int *ecx, unsigned int *edx) 198 { 199 /* ecx is often an input as well as an output. */ 200 asm volatile("cpuid" 201 : "=a" (*eax), 202 "=b" (*ebx), 203 "=c" (*ecx), 204 "=d" (*edx) 205 : "0" (*eax), "2" (*ecx) 206 : "memory"); 207 } 208 209 static inline void load_cr3(pgd_t *pgdir) 210 { 211 write_cr3(__pa(pgdir)); 212 } 213 214 #ifdef CONFIG_X86_32 215 /* This is the TSS defined by the hardware. */ 216 struct x86_hw_tss { 217 unsigned short back_link, __blh; 218 unsigned long sp0; 219 unsigned short ss0, __ss0h; 220 unsigned long sp1; 221 222 /* 223 * We don't use ring 1, so ss1 is a convenient scratch space in 224 * the same cacheline as sp0. We use ss1 to cache the value in 225 * MSR_IA32_SYSENTER_CS. When we context switch 226 * MSR_IA32_SYSENTER_CS, we first check if the new value being 227 * written matches ss1, and, if it's not, then we wrmsr the new 228 * value and update ss1. 229 * 230 * The only reason we context switch MSR_IA32_SYSENTER_CS is 231 * that we set it to zero in vm86 tasks to avoid corrupting the 232 * stack if we were to go through the sysenter path from vm86 233 * mode. 234 */ 235 unsigned short ss1; /* MSR_IA32_SYSENTER_CS */ 236 237 unsigned short __ss1h; 238 unsigned long sp2; 239 unsigned short ss2, __ss2h; 240 unsigned long __cr3; 241 unsigned long ip; 242 unsigned long flags; 243 unsigned long ax; 244 unsigned long cx; 245 unsigned long dx; 246 unsigned long bx; 247 unsigned long sp; 248 unsigned long bp; 249 unsigned long si; 250 unsigned long di; 251 unsigned short es, __esh; 252 unsigned short cs, __csh; 253 unsigned short ss, __ssh; 254 unsigned short ds, __dsh; 255 unsigned short fs, __fsh; 256 unsigned short gs, __gsh; 257 unsigned short ldt, __ldth; 258 unsigned short trace; 259 unsigned short io_bitmap_base; 260 261 } __attribute__((packed)); 262 #else 263 struct x86_hw_tss { 264 u32 reserved1; 265 u64 sp0; 266 u64 sp1; 267 u64 sp2; 268 u64 reserved2; 269 u64 ist[7]; 270 u32 reserved3; 271 u32 reserved4; 272 u16 reserved5; 273 u16 io_bitmap_base; 274 275 } __attribute__((packed)) ____cacheline_aligned; 276 #endif 277 278 /* 279 * IO-bitmap sizes: 280 */ 281 #define IO_BITMAP_BITS 65536 282 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8) 283 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long)) 284 #define IO_BITMAP_OFFSET offsetof(struct tss_struct, io_bitmap) 285 #define INVALID_IO_BITMAP_OFFSET 0x8000 286 287 struct tss_struct { 288 /* 289 * The hardware state: 290 */ 291 struct x86_hw_tss x86_tss; 292 293 /* 294 * The extra 1 is there because the CPU will access an 295 * additional byte beyond the end of the IO permission 296 * bitmap. The extra byte must be all 1 bits, and must 297 * be within the limit. 298 */ 299 unsigned long io_bitmap[IO_BITMAP_LONGS + 1]; 300 301 /* 302 * Space for the temporary SYSENTER stack: 303 */ 304 unsigned long SYSENTER_stack[64]; 305 306 } ____cacheline_aligned; 307 308 DECLARE_PER_CPU_SHARED_ALIGNED(struct tss_struct, cpu_tss); 309 310 #ifdef CONFIG_X86_32 311 DECLARE_PER_CPU(unsigned long, cpu_current_top_of_stack); 312 #endif 313 314 /* 315 * Save the original ist values for checking stack pointers during debugging 316 */ 317 struct orig_ist { 318 unsigned long ist[7]; 319 }; 320 321 #ifdef CONFIG_X86_64 322 DECLARE_PER_CPU(struct orig_ist, orig_ist); 323 324 union irq_stack_union { 325 char irq_stack[IRQ_STACK_SIZE]; 326 /* 327 * GCC hardcodes the stack canary as %gs:40. Since the 328 * irq_stack is the object at %gs:0, we reserve the bottom 329 * 48 bytes of the irq stack for the canary. 330 */ 331 struct { 332 char gs_base[40]; 333 unsigned long stack_canary; 334 }; 335 }; 336 337 DECLARE_PER_CPU_FIRST(union irq_stack_union, irq_stack_union) __visible; 338 DECLARE_INIT_PER_CPU(irq_stack_union); 339 340 DECLARE_PER_CPU(char *, irq_stack_ptr); 341 DECLARE_PER_CPU(unsigned int, irq_count); 342 extern asmlinkage void ignore_sysret(void); 343 #else /* X86_64 */ 344 #ifdef CONFIG_CC_STACKPROTECTOR 345 /* 346 * Make sure stack canary segment base is cached-aligned: 347 * "For Intel Atom processors, avoid non zero segment base address 348 * that is not aligned to cache line boundary at all cost." 349 * (Optim Ref Manual Assembly/Compiler Coding Rule 15.) 350 */ 351 struct stack_canary { 352 char __pad[20]; /* canary at %gs:20 */ 353 unsigned long canary; 354 }; 355 DECLARE_PER_CPU_ALIGNED(struct stack_canary, stack_canary); 356 #endif 357 /* 358 * per-CPU IRQ handling stacks 359 */ 360 struct irq_stack { 361 u32 stack[THREAD_SIZE/sizeof(u32)]; 362 } __aligned(THREAD_SIZE); 363 364 DECLARE_PER_CPU(struct irq_stack *, hardirq_stack); 365 DECLARE_PER_CPU(struct irq_stack *, softirq_stack); 366 #endif /* X86_64 */ 367 368 extern unsigned int xstate_size; 369 370 struct perf_event; 371 372 struct thread_struct { 373 /* Cached TLS descriptors: */ 374 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES]; 375 unsigned long sp0; 376 unsigned long sp; 377 #ifdef CONFIG_X86_32 378 unsigned long sysenter_cs; 379 #else 380 unsigned short es; 381 unsigned short ds; 382 unsigned short fsindex; 383 unsigned short gsindex; 384 #endif 385 #ifdef CONFIG_X86_32 386 unsigned long ip; 387 #endif 388 #ifdef CONFIG_X86_64 389 unsigned long fs; 390 #endif 391 unsigned long gs; 392 393 /* Save middle states of ptrace breakpoints */ 394 struct perf_event *ptrace_bps[HBP_NUM]; 395 /* Debug status used for traps, single steps, etc... */ 396 unsigned long debugreg6; 397 /* Keep track of the exact dr7 value set by the user */ 398 unsigned long ptrace_dr7; 399 /* Fault info: */ 400 unsigned long cr2; 401 unsigned long trap_nr; 402 unsigned long error_code; 403 #ifdef CONFIG_VM86 404 /* Virtual 86 mode info */ 405 struct vm86 *vm86; 406 #endif 407 /* IO permissions: */ 408 unsigned long *io_bitmap_ptr; 409 unsigned long iopl; 410 /* Max allowed port in the bitmap, in bytes: */ 411 unsigned io_bitmap_max; 412 413 /* Floating point and extended processor state */ 414 struct fpu fpu; 415 /* 416 * WARNING: 'fpu' is dynamically-sized. It *MUST* be at 417 * the end. 418 */ 419 }; 420 421 /* 422 * Set IOPL bits in EFLAGS from given mask 423 */ 424 static inline void native_set_iopl_mask(unsigned mask) 425 { 426 #ifdef CONFIG_X86_32 427 unsigned int reg; 428 429 asm volatile ("pushfl;" 430 "popl %0;" 431 "andl %1, %0;" 432 "orl %2, %0;" 433 "pushl %0;" 434 "popfl" 435 : "=&r" (reg) 436 : "i" (~X86_EFLAGS_IOPL), "r" (mask)); 437 #endif 438 } 439 440 static inline void 441 native_load_sp0(struct tss_struct *tss, struct thread_struct *thread) 442 { 443 tss->x86_tss.sp0 = thread->sp0; 444 #ifdef CONFIG_X86_32 445 /* Only happens when SEP is enabled, no need to test "SEP"arately: */ 446 if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) { 447 tss->x86_tss.ss1 = thread->sysenter_cs; 448 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0); 449 } 450 #endif 451 } 452 453 static inline void native_swapgs(void) 454 { 455 #ifdef CONFIG_X86_64 456 asm volatile("swapgs" ::: "memory"); 457 #endif 458 } 459 460 static inline unsigned long current_top_of_stack(void) 461 { 462 #ifdef CONFIG_X86_64 463 return this_cpu_read_stable(cpu_tss.x86_tss.sp0); 464 #else 465 /* sp0 on x86_32 is special in and around vm86 mode. */ 466 return this_cpu_read_stable(cpu_current_top_of_stack); 467 #endif 468 } 469 470 #ifdef CONFIG_PARAVIRT 471 #include <asm/paravirt.h> 472 #else 473 #define __cpuid native_cpuid 474 #define paravirt_enabled() 0 475 #define paravirt_has(x) 0 476 477 static inline void load_sp0(struct tss_struct *tss, 478 struct thread_struct *thread) 479 { 480 native_load_sp0(tss, thread); 481 } 482 483 #define set_iopl_mask native_set_iopl_mask 484 #endif /* CONFIG_PARAVIRT */ 485 486 typedef struct { 487 unsigned long seg; 488 } mm_segment_t; 489 490 491 /* Free all resources held by a thread. */ 492 extern void release_thread(struct task_struct *); 493 494 unsigned long get_wchan(struct task_struct *p); 495 496 /* 497 * Generic CPUID function 498 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx 499 * resulting in stale register contents being returned. 500 */ 501 static inline void cpuid(unsigned int op, 502 unsigned int *eax, unsigned int *ebx, 503 unsigned int *ecx, unsigned int *edx) 504 { 505 *eax = op; 506 *ecx = 0; 507 __cpuid(eax, ebx, ecx, edx); 508 } 509 510 /* Some CPUID calls want 'count' to be placed in ecx */ 511 static inline void cpuid_count(unsigned int op, int count, 512 unsigned int *eax, unsigned int *ebx, 513 unsigned int *ecx, unsigned int *edx) 514 { 515 *eax = op; 516 *ecx = count; 517 __cpuid(eax, ebx, ecx, edx); 518 } 519 520 /* 521 * CPUID functions returning a single datum 522 */ 523 static inline unsigned int cpuid_eax(unsigned int op) 524 { 525 unsigned int eax, ebx, ecx, edx; 526 527 cpuid(op, &eax, &ebx, &ecx, &edx); 528 529 return eax; 530 } 531 532 static inline unsigned int cpuid_ebx(unsigned int op) 533 { 534 unsigned int eax, ebx, ecx, edx; 535 536 cpuid(op, &eax, &ebx, &ecx, &edx); 537 538 return ebx; 539 } 540 541 static inline unsigned int cpuid_ecx(unsigned int op) 542 { 543 unsigned int eax, ebx, ecx, edx; 544 545 cpuid(op, &eax, &ebx, &ecx, &edx); 546 547 return ecx; 548 } 549 550 static inline unsigned int cpuid_edx(unsigned int op) 551 { 552 unsigned int eax, ebx, ecx, edx; 553 554 cpuid(op, &eax, &ebx, &ecx, &edx); 555 556 return edx; 557 } 558 559 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */ 560 static __always_inline void rep_nop(void) 561 { 562 asm volatile("rep; nop" ::: "memory"); 563 } 564 565 static __always_inline void cpu_relax(void) 566 { 567 rep_nop(); 568 } 569 570 #define cpu_relax_lowlatency() cpu_relax() 571 572 /* Stop speculative execution and prefetching of modified code. */ 573 static inline void sync_core(void) 574 { 575 int tmp; 576 577 #ifdef CONFIG_M486 578 /* 579 * Do a CPUID if available, otherwise do a jump. The jump 580 * can conveniently enough be the jump around CPUID. 581 */ 582 asm volatile("cmpl %2,%1\n\t" 583 "jl 1f\n\t" 584 "cpuid\n" 585 "1:" 586 : "=a" (tmp) 587 : "rm" (boot_cpu_data.cpuid_level), "ri" (0), "0" (1) 588 : "ebx", "ecx", "edx", "memory"); 589 #else 590 /* 591 * CPUID is a barrier to speculative execution. 592 * Prefetched instructions are automatically 593 * invalidated when modified. 594 */ 595 asm volatile("cpuid" 596 : "=a" (tmp) 597 : "0" (1) 598 : "ebx", "ecx", "edx", "memory"); 599 #endif 600 } 601 602 extern void select_idle_routine(const struct cpuinfo_x86 *c); 603 extern void init_amd_e400_c1e_mask(void); 604 605 extern unsigned long boot_option_idle_override; 606 extern bool amd_e400_c1e_detected; 607 608 enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_NOMWAIT, 609 IDLE_POLL}; 610 611 extern void enable_sep_cpu(void); 612 extern int sysenter_setup(void); 613 614 extern void early_trap_init(void); 615 void early_trap_pf_init(void); 616 617 /* Defined in head.S */ 618 extern struct desc_ptr early_gdt_descr; 619 620 extern void cpu_set_gdt(int); 621 extern void switch_to_new_gdt(int); 622 extern void load_percpu_segment(int); 623 extern void cpu_init(void); 624 625 static inline unsigned long get_debugctlmsr(void) 626 { 627 unsigned long debugctlmsr = 0; 628 629 #ifndef CONFIG_X86_DEBUGCTLMSR 630 if (boot_cpu_data.x86 < 6) 631 return 0; 632 #endif 633 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr); 634 635 return debugctlmsr; 636 } 637 638 static inline void update_debugctlmsr(unsigned long debugctlmsr) 639 { 640 #ifndef CONFIG_X86_DEBUGCTLMSR 641 if (boot_cpu_data.x86 < 6) 642 return; 643 #endif 644 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr); 645 } 646 647 extern void set_task_blockstep(struct task_struct *task, bool on); 648 649 /* Boot loader type from the setup header: */ 650 extern int bootloader_type; 651 extern int bootloader_version; 652 653 extern char ignore_fpu_irq; 654 655 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1 656 #define ARCH_HAS_PREFETCHW 657 #define ARCH_HAS_SPINLOCK_PREFETCH 658 659 #ifdef CONFIG_X86_32 660 # define BASE_PREFETCH "" 661 # define ARCH_HAS_PREFETCH 662 #else 663 # define BASE_PREFETCH "prefetcht0 %P1" 664 #endif 665 666 /* 667 * Prefetch instructions for Pentium III (+) and AMD Athlon (+) 668 * 669 * It's not worth to care about 3dnow prefetches for the K6 670 * because they are microcoded there and very slow. 671 */ 672 static inline void prefetch(const void *x) 673 { 674 alternative_input(BASE_PREFETCH, "prefetchnta %P1", 675 X86_FEATURE_XMM, 676 "m" (*(const char *)x)); 677 } 678 679 /* 680 * 3dnow prefetch to get an exclusive cache line. 681 * Useful for spinlocks to avoid one state transition in the 682 * cache coherency protocol: 683 */ 684 static inline void prefetchw(const void *x) 685 { 686 alternative_input(BASE_PREFETCH, "prefetchw %P1", 687 X86_FEATURE_3DNOWPREFETCH, 688 "m" (*(const char *)x)); 689 } 690 691 static inline void spin_lock_prefetch(const void *x) 692 { 693 prefetchw(x); 694 } 695 696 #define TOP_OF_INIT_STACK ((unsigned long)&init_stack + sizeof(init_stack) - \ 697 TOP_OF_KERNEL_STACK_PADDING) 698 699 #ifdef CONFIG_X86_32 700 /* 701 * User space process size: 3GB (default). 702 */ 703 #define TASK_SIZE PAGE_OFFSET 704 #define TASK_SIZE_MAX TASK_SIZE 705 #define STACK_TOP TASK_SIZE 706 #define STACK_TOP_MAX STACK_TOP 707 708 #define INIT_THREAD { \ 709 .sp0 = TOP_OF_INIT_STACK, \ 710 .sysenter_cs = __KERNEL_CS, \ 711 .io_bitmap_ptr = NULL, \ 712 } 713 714 extern unsigned long thread_saved_pc(struct task_struct *tsk); 715 716 /* 717 * TOP_OF_KERNEL_STACK_PADDING reserves 8 bytes on top of the ring0 stack. 718 * This is necessary to guarantee that the entire "struct pt_regs" 719 * is accessible even if the CPU haven't stored the SS/ESP registers 720 * on the stack (interrupt gate does not save these registers 721 * when switching to the same priv ring). 722 * Therefore beware: accessing the ss/esp fields of the 723 * "struct pt_regs" is possible, but they may contain the 724 * completely wrong values. 725 */ 726 #define task_pt_regs(task) \ 727 ({ \ 728 unsigned long __ptr = (unsigned long)task_stack_page(task); \ 729 __ptr += THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING; \ 730 ((struct pt_regs *)__ptr) - 1; \ 731 }) 732 733 #define KSTK_ESP(task) (task_pt_regs(task)->sp) 734 735 #else 736 /* 737 * User space process size. 47bits minus one guard page. The guard 738 * page is necessary on Intel CPUs: if a SYSCALL instruction is at 739 * the highest possible canonical userspace address, then that 740 * syscall will enter the kernel with a non-canonical return 741 * address, and SYSRET will explode dangerously. We avoid this 742 * particular problem by preventing anything from being mapped 743 * at the maximum canonical address. 744 */ 745 #define TASK_SIZE_MAX ((1UL << 47) - PAGE_SIZE) 746 747 /* This decides where the kernel will search for a free chunk of vm 748 * space during mmap's. 749 */ 750 #define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? \ 751 0xc0000000 : 0xFFFFe000) 752 753 #define TASK_SIZE (test_thread_flag(TIF_ADDR32) ? \ 754 IA32_PAGE_OFFSET : TASK_SIZE_MAX) 755 #define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_ADDR32)) ? \ 756 IA32_PAGE_OFFSET : TASK_SIZE_MAX) 757 758 #define STACK_TOP TASK_SIZE 759 #define STACK_TOP_MAX TASK_SIZE_MAX 760 761 #define INIT_THREAD { \ 762 .sp0 = TOP_OF_INIT_STACK \ 763 } 764 765 /* 766 * Return saved PC of a blocked thread. 767 * What is this good for? it will be always the scheduler or ret_from_fork. 768 */ 769 #define thread_saved_pc(t) READ_ONCE_NOCHECK(*(unsigned long *)((t)->thread.sp - 8)) 770 771 #define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.sp0 - 1) 772 extern unsigned long KSTK_ESP(struct task_struct *task); 773 774 #endif /* CONFIG_X86_64 */ 775 776 extern void start_thread(struct pt_regs *regs, unsigned long new_ip, 777 unsigned long new_sp); 778 779 /* 780 * This decides where the kernel will search for a free chunk of vm 781 * space during mmap's. 782 */ 783 #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3)) 784 785 #define KSTK_EIP(task) (task_pt_regs(task)->ip) 786 787 /* Get/set a process' ability to use the timestamp counter instruction */ 788 #define GET_TSC_CTL(adr) get_tsc_mode((adr)) 789 #define SET_TSC_CTL(val) set_tsc_mode((val)) 790 791 extern int get_tsc_mode(unsigned long adr); 792 extern int set_tsc_mode(unsigned int val); 793 794 /* Register/unregister a process' MPX related resource */ 795 #define MPX_ENABLE_MANAGEMENT() mpx_enable_management() 796 #define MPX_DISABLE_MANAGEMENT() mpx_disable_management() 797 798 #ifdef CONFIG_X86_INTEL_MPX 799 extern int mpx_enable_management(void); 800 extern int mpx_disable_management(void); 801 #else 802 static inline int mpx_enable_management(void) 803 { 804 return -EINVAL; 805 } 806 static inline int mpx_disable_management(void) 807 { 808 return -EINVAL; 809 } 810 #endif /* CONFIG_X86_INTEL_MPX */ 811 812 extern u16 amd_get_nb_id(int cpu); 813 extern u32 amd_get_nodes_per_socket(void); 814 815 static inline uint32_t hypervisor_cpuid_base(const char *sig, uint32_t leaves) 816 { 817 uint32_t base, eax, signature[3]; 818 819 for (base = 0x40000000; base < 0x40010000; base += 0x100) { 820 cpuid(base, &eax, &signature[0], &signature[1], &signature[2]); 821 822 if (!memcmp(sig, signature, 12) && 823 (leaves == 0 || ((eax - base) >= leaves))) 824 return base; 825 } 826 827 return 0; 828 } 829 830 extern unsigned long arch_align_stack(unsigned long sp); 831 extern void free_init_pages(char *what, unsigned long begin, unsigned long end); 832 833 void default_idle(void); 834 #ifdef CONFIG_XEN 835 bool xen_set_default_idle(void); 836 #else 837 #define xen_set_default_idle 0 838 #endif 839 840 void stop_this_cpu(void *dummy); 841 void df_debug(struct pt_regs *regs, long error_code); 842 #endif /* _ASM_X86_PROCESSOR_H */ 843