1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _ASM_X86_PROCESSOR_H 3 #define _ASM_X86_PROCESSOR_H 4 5 #include <asm/processor-flags.h> 6 7 /* Forward declaration, a strange C thing */ 8 struct task_struct; 9 struct mm_struct; 10 struct io_bitmap; 11 struct vm86; 12 13 #include <asm/math_emu.h> 14 #include <asm/segment.h> 15 #include <asm/types.h> 16 #include <uapi/asm/sigcontext.h> 17 #include <asm/current.h> 18 #include <asm/cpufeatures.h> 19 #include <asm/cpuid.h> 20 #include <asm/page.h> 21 #include <asm/pgtable_types.h> 22 #include <asm/percpu.h> 23 #include <asm/desc_defs.h> 24 #include <asm/nops.h> 25 #include <asm/special_insns.h> 26 #include <asm/fpu/types.h> 27 #include <asm/unwind_hints.h> 28 #include <asm/vmxfeatures.h> 29 #include <asm/vdso/processor.h> 30 #include <asm/shstk.h> 31 32 #include <linux/personality.h> 33 #include <linux/cache.h> 34 #include <linux/threads.h> 35 #include <linux/math64.h> 36 #include <linux/err.h> 37 #include <linux/irqflags.h> 38 #include <linux/mem_encrypt.h> 39 40 /* 41 * We handle most unaligned accesses in hardware. On the other hand 42 * unaligned DMA can be quite expensive on some Nehalem processors. 43 * 44 * Based on this we disable the IP header alignment in network drivers. 45 */ 46 #define NET_IP_ALIGN 0 47 48 #define HBP_NUM 4 49 50 /* 51 * These alignment constraints are for performance in the vSMP case, 52 * but in the task_struct case we must also meet hardware imposed 53 * alignment requirements of the FPU state: 54 */ 55 #ifdef CONFIG_X86_VSMP 56 # define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT) 57 # define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT) 58 #else 59 # define ARCH_MIN_TASKALIGN __alignof__(union fpregs_state) 60 # define ARCH_MIN_MMSTRUCT_ALIGN 0 61 #endif 62 63 enum tlb_infos { 64 ENTRIES, 65 NR_INFO 66 }; 67 68 extern u16 __read_mostly tlb_lli_4k[NR_INFO]; 69 extern u16 __read_mostly tlb_lli_2m[NR_INFO]; 70 extern u16 __read_mostly tlb_lli_4m[NR_INFO]; 71 extern u16 __read_mostly tlb_lld_4k[NR_INFO]; 72 extern u16 __read_mostly tlb_lld_2m[NR_INFO]; 73 extern u16 __read_mostly tlb_lld_4m[NR_INFO]; 74 extern u16 __read_mostly tlb_lld_1g[NR_INFO]; 75 76 /* 77 * CPU type and hardware bug flags. Kept separately for each CPU. 78 */ 79 80 struct cpuinfo_topology { 81 // Real APIC ID read from the local APIC 82 u32 apicid; 83 // The initial APIC ID provided by CPUID 84 u32 initial_apicid; 85 86 // Physical package ID 87 u32 pkg_id; 88 89 // Physical die ID on AMD, Relative on Intel 90 u32 die_id; 91 92 // Compute unit ID - AMD specific 93 u32 cu_id; 94 95 // Core ID relative to the package 96 u32 core_id; 97 98 // Logical ID mappings 99 u32 logical_pkg_id; 100 u32 logical_die_id; 101 102 // AMD Node ID and Nodes per Package info 103 u32 amd_node_id; 104 105 // Cache level topology IDs 106 u32 llc_id; 107 u32 l2c_id; 108 }; 109 110 struct cpuinfo_x86 { 111 __u8 x86; /* CPU family */ 112 __u8 x86_vendor; /* CPU vendor */ 113 __u8 x86_model; 114 __u8 x86_stepping; 115 #ifdef CONFIG_X86_64 116 /* Number of 4K pages in DTLB/ITLB combined(in pages): */ 117 int x86_tlbsize; 118 #endif 119 #ifdef CONFIG_X86_VMX_FEATURE_NAMES 120 __u32 vmx_capability[NVMXINTS]; 121 #endif 122 __u8 x86_virt_bits; 123 __u8 x86_phys_bits; 124 /* Max extended CPUID function supported: */ 125 __u32 extended_cpuid_level; 126 /* Maximum supported CPUID level, -1=no CPUID: */ 127 int cpuid_level; 128 /* 129 * Align to size of unsigned long because the x86_capability array 130 * is passed to bitops which require the alignment. Use unnamed 131 * union to enforce the array is aligned to size of unsigned long. 132 */ 133 union { 134 __u32 x86_capability[NCAPINTS + NBUGINTS]; 135 unsigned long x86_capability_alignment; 136 }; 137 char x86_vendor_id[16]; 138 char x86_model_id[64]; 139 struct cpuinfo_topology topo; 140 /* in KB - valid for CPUS which support this call: */ 141 unsigned int x86_cache_size; 142 int x86_cache_alignment; /* In bytes */ 143 /* Cache QoS architectural values, valid only on the BSP: */ 144 int x86_cache_max_rmid; /* max index */ 145 int x86_cache_occ_scale; /* scale to bytes */ 146 int x86_cache_mbm_width_offset; 147 int x86_power; 148 unsigned long loops_per_jiffy; 149 /* protected processor identification number */ 150 u64 ppin; 151 u16 x86_clflush_size; 152 /* number of cores as seen by the OS: */ 153 u16 booted_cores; 154 /* Index into per_cpu list: */ 155 u16 cpu_index; 156 /* Is SMT active on this core? */ 157 bool smt_active; 158 u32 microcode; 159 /* Address space bits used by the cache internally */ 160 u8 x86_cache_bits; 161 unsigned initialized : 1; 162 } __randomize_layout; 163 164 #define X86_VENDOR_INTEL 0 165 #define X86_VENDOR_CYRIX 1 166 #define X86_VENDOR_AMD 2 167 #define X86_VENDOR_UMC 3 168 #define X86_VENDOR_CENTAUR 5 169 #define X86_VENDOR_TRANSMETA 7 170 #define X86_VENDOR_NSC 8 171 #define X86_VENDOR_HYGON 9 172 #define X86_VENDOR_ZHAOXIN 10 173 #define X86_VENDOR_VORTEX 11 174 #define X86_VENDOR_NUM 12 175 176 #define X86_VENDOR_UNKNOWN 0xff 177 178 /* 179 * capabilities of CPUs 180 */ 181 extern struct cpuinfo_x86 boot_cpu_data; 182 extern struct cpuinfo_x86 new_cpu_data; 183 184 extern __u32 cpu_caps_cleared[NCAPINTS + NBUGINTS]; 185 extern __u32 cpu_caps_set[NCAPINTS + NBUGINTS]; 186 187 DECLARE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info); 188 #define cpu_data(cpu) per_cpu(cpu_info, cpu) 189 190 extern const struct seq_operations cpuinfo_op; 191 192 #define cache_line_size() (boot_cpu_data.x86_cache_alignment) 193 194 extern void cpu_detect(struct cpuinfo_x86 *c); 195 196 static inline unsigned long long l1tf_pfn_limit(void) 197 { 198 return BIT_ULL(boot_cpu_data.x86_cache_bits - 1 - PAGE_SHIFT); 199 } 200 201 extern void early_cpu_init(void); 202 extern void identify_secondary_cpu(struct cpuinfo_x86 *); 203 extern void print_cpu_info(struct cpuinfo_x86 *); 204 void print_cpu_msr(struct cpuinfo_x86 *); 205 206 /* 207 * Friendlier CR3 helpers. 208 */ 209 static inline unsigned long read_cr3_pa(void) 210 { 211 return __read_cr3() & CR3_ADDR_MASK; 212 } 213 214 static inline unsigned long native_read_cr3_pa(void) 215 { 216 return __native_read_cr3() & CR3_ADDR_MASK; 217 } 218 219 static inline void load_cr3(pgd_t *pgdir) 220 { 221 write_cr3(__sme_pa(pgdir)); 222 } 223 224 /* 225 * Note that while the legacy 'TSS' name comes from 'Task State Segment', 226 * on modern x86 CPUs the TSS also holds information important to 64-bit mode, 227 * unrelated to the task-switch mechanism: 228 */ 229 #ifdef CONFIG_X86_32 230 /* This is the TSS defined by the hardware. */ 231 struct x86_hw_tss { 232 unsigned short back_link, __blh; 233 unsigned long sp0; 234 unsigned short ss0, __ss0h; 235 unsigned long sp1; 236 237 /* 238 * We don't use ring 1, so ss1 is a convenient scratch space in 239 * the same cacheline as sp0. We use ss1 to cache the value in 240 * MSR_IA32_SYSENTER_CS. When we context switch 241 * MSR_IA32_SYSENTER_CS, we first check if the new value being 242 * written matches ss1, and, if it's not, then we wrmsr the new 243 * value and update ss1. 244 * 245 * The only reason we context switch MSR_IA32_SYSENTER_CS is 246 * that we set it to zero in vm86 tasks to avoid corrupting the 247 * stack if we were to go through the sysenter path from vm86 248 * mode. 249 */ 250 unsigned short ss1; /* MSR_IA32_SYSENTER_CS */ 251 252 unsigned short __ss1h; 253 unsigned long sp2; 254 unsigned short ss2, __ss2h; 255 unsigned long __cr3; 256 unsigned long ip; 257 unsigned long flags; 258 unsigned long ax; 259 unsigned long cx; 260 unsigned long dx; 261 unsigned long bx; 262 unsigned long sp; 263 unsigned long bp; 264 unsigned long si; 265 unsigned long di; 266 unsigned short es, __esh; 267 unsigned short cs, __csh; 268 unsigned short ss, __ssh; 269 unsigned short ds, __dsh; 270 unsigned short fs, __fsh; 271 unsigned short gs, __gsh; 272 unsigned short ldt, __ldth; 273 unsigned short trace; 274 unsigned short io_bitmap_base; 275 276 } __attribute__((packed)); 277 #else 278 struct x86_hw_tss { 279 u32 reserved1; 280 u64 sp0; 281 u64 sp1; 282 283 /* 284 * Since Linux does not use ring 2, the 'sp2' slot is unused by 285 * hardware. entry_SYSCALL_64 uses it as scratch space to stash 286 * the user RSP value. 287 */ 288 u64 sp2; 289 290 u64 reserved2; 291 u64 ist[7]; 292 u32 reserved3; 293 u32 reserved4; 294 u16 reserved5; 295 u16 io_bitmap_base; 296 297 } __attribute__((packed)); 298 #endif 299 300 /* 301 * IO-bitmap sizes: 302 */ 303 #define IO_BITMAP_BITS 65536 304 #define IO_BITMAP_BYTES (IO_BITMAP_BITS / BITS_PER_BYTE) 305 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES / sizeof(long)) 306 307 #define IO_BITMAP_OFFSET_VALID_MAP \ 308 (offsetof(struct tss_struct, io_bitmap.bitmap) - \ 309 offsetof(struct tss_struct, x86_tss)) 310 311 #define IO_BITMAP_OFFSET_VALID_ALL \ 312 (offsetof(struct tss_struct, io_bitmap.mapall) - \ 313 offsetof(struct tss_struct, x86_tss)) 314 315 #ifdef CONFIG_X86_IOPL_IOPERM 316 /* 317 * sizeof(unsigned long) coming from an extra "long" at the end of the 318 * iobitmap. The limit is inclusive, i.e. the last valid byte. 319 */ 320 # define __KERNEL_TSS_LIMIT \ 321 (IO_BITMAP_OFFSET_VALID_ALL + IO_BITMAP_BYTES + \ 322 sizeof(unsigned long) - 1) 323 #else 324 # define __KERNEL_TSS_LIMIT \ 325 (offsetof(struct tss_struct, x86_tss) + sizeof(struct x86_hw_tss) - 1) 326 #endif 327 328 /* Base offset outside of TSS_LIMIT so unpriviledged IO causes #GP */ 329 #define IO_BITMAP_OFFSET_INVALID (__KERNEL_TSS_LIMIT + 1) 330 331 struct entry_stack { 332 char stack[PAGE_SIZE]; 333 }; 334 335 struct entry_stack_page { 336 struct entry_stack stack; 337 } __aligned(PAGE_SIZE); 338 339 /* 340 * All IO bitmap related data stored in the TSS: 341 */ 342 struct x86_io_bitmap { 343 /* The sequence number of the last active bitmap. */ 344 u64 prev_sequence; 345 346 /* 347 * Store the dirty size of the last io bitmap offender. The next 348 * one will have to do the cleanup as the switch out to a non io 349 * bitmap user will just set x86_tss.io_bitmap_base to a value 350 * outside of the TSS limit. So for sane tasks there is no need to 351 * actually touch the io_bitmap at all. 352 */ 353 unsigned int prev_max; 354 355 /* 356 * The extra 1 is there because the CPU will access an 357 * additional byte beyond the end of the IO permission 358 * bitmap. The extra byte must be all 1 bits, and must 359 * be within the limit. 360 */ 361 unsigned long bitmap[IO_BITMAP_LONGS + 1]; 362 363 /* 364 * Special I/O bitmap to emulate IOPL(3). All bytes zero, 365 * except the additional byte at the end. 366 */ 367 unsigned long mapall[IO_BITMAP_LONGS + 1]; 368 }; 369 370 struct tss_struct { 371 /* 372 * The fixed hardware portion. This must not cross a page boundary 373 * at risk of violating the SDM's advice and potentially triggering 374 * errata. 375 */ 376 struct x86_hw_tss x86_tss; 377 378 struct x86_io_bitmap io_bitmap; 379 } __aligned(PAGE_SIZE); 380 381 DECLARE_PER_CPU_PAGE_ALIGNED(struct tss_struct, cpu_tss_rw); 382 383 /* Per CPU interrupt stacks */ 384 struct irq_stack { 385 char stack[IRQ_STACK_SIZE]; 386 } __aligned(IRQ_STACK_SIZE); 387 388 #ifdef CONFIG_X86_64 389 struct fixed_percpu_data { 390 /* 391 * GCC hardcodes the stack canary as %gs:40. Since the 392 * irq_stack is the object at %gs:0, we reserve the bottom 393 * 48 bytes of the irq stack for the canary. 394 * 395 * Once we are willing to require -mstack-protector-guard-symbol= 396 * support for x86_64 stackprotector, we can get rid of this. 397 */ 398 char gs_base[40]; 399 unsigned long stack_canary; 400 }; 401 402 DECLARE_PER_CPU_FIRST(struct fixed_percpu_data, fixed_percpu_data) __visible; 403 DECLARE_INIT_PER_CPU(fixed_percpu_data); 404 405 static inline unsigned long cpu_kernelmode_gs_base(int cpu) 406 { 407 return (unsigned long)per_cpu(fixed_percpu_data.gs_base, cpu); 408 } 409 410 extern asmlinkage void entry_SYSCALL32_ignore(void); 411 412 /* Save actual FS/GS selectors and bases to current->thread */ 413 void current_save_fsgs(void); 414 #else /* X86_64 */ 415 #ifdef CONFIG_STACKPROTECTOR 416 DECLARE_PER_CPU(unsigned long, __stack_chk_guard); 417 #endif 418 #endif /* !X86_64 */ 419 420 struct perf_event; 421 422 struct thread_struct { 423 /* Cached TLS descriptors: */ 424 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES]; 425 #ifdef CONFIG_X86_32 426 unsigned long sp0; 427 #endif 428 unsigned long sp; 429 #ifdef CONFIG_X86_32 430 unsigned long sysenter_cs; 431 #else 432 unsigned short es; 433 unsigned short ds; 434 unsigned short fsindex; 435 unsigned short gsindex; 436 #endif 437 438 #ifdef CONFIG_X86_64 439 unsigned long fsbase; 440 unsigned long gsbase; 441 #else 442 /* 443 * XXX: this could presumably be unsigned short. Alternatively, 444 * 32-bit kernels could be taught to use fsindex instead. 445 */ 446 unsigned long fs; 447 unsigned long gs; 448 #endif 449 450 /* Save middle states of ptrace breakpoints */ 451 struct perf_event *ptrace_bps[HBP_NUM]; 452 /* Debug status used for traps, single steps, etc... */ 453 unsigned long virtual_dr6; 454 /* Keep track of the exact dr7 value set by the user */ 455 unsigned long ptrace_dr7; 456 /* Fault info: */ 457 unsigned long cr2; 458 unsigned long trap_nr; 459 unsigned long error_code; 460 #ifdef CONFIG_VM86 461 /* Virtual 86 mode info */ 462 struct vm86 *vm86; 463 #endif 464 /* IO permissions: */ 465 struct io_bitmap *io_bitmap; 466 467 /* 468 * IOPL. Privilege level dependent I/O permission which is 469 * emulated via the I/O bitmap to prevent user space from disabling 470 * interrupts. 471 */ 472 unsigned long iopl_emul; 473 474 unsigned int iopl_warn:1; 475 476 /* 477 * Protection Keys Register for Userspace. Loaded immediately on 478 * context switch. Store it in thread_struct to avoid a lookup in 479 * the tasks's FPU xstate buffer. This value is only valid when a 480 * task is scheduled out. For 'current' the authoritative source of 481 * PKRU is the hardware itself. 482 */ 483 u32 pkru; 484 485 #ifdef CONFIG_X86_USER_SHADOW_STACK 486 unsigned long features; 487 unsigned long features_locked; 488 489 struct thread_shstk shstk; 490 #endif 491 492 /* Floating point and extended processor state */ 493 struct fpu fpu; 494 /* 495 * WARNING: 'fpu' is dynamically-sized. It *MUST* be at 496 * the end. 497 */ 498 }; 499 500 extern void fpu_thread_struct_whitelist(unsigned long *offset, unsigned long *size); 501 502 static inline void arch_thread_struct_whitelist(unsigned long *offset, 503 unsigned long *size) 504 { 505 fpu_thread_struct_whitelist(offset, size); 506 } 507 508 static inline void 509 native_load_sp0(unsigned long sp0) 510 { 511 this_cpu_write(cpu_tss_rw.x86_tss.sp0, sp0); 512 } 513 514 static __always_inline void native_swapgs(void) 515 { 516 #ifdef CONFIG_X86_64 517 asm volatile("swapgs" ::: "memory"); 518 #endif 519 } 520 521 static __always_inline unsigned long current_top_of_stack(void) 522 { 523 /* 524 * We can't read directly from tss.sp0: sp0 on x86_32 is special in 525 * and around vm86 mode and sp0 on x86_64 is special because of the 526 * entry trampoline. 527 */ 528 if (IS_ENABLED(CONFIG_USE_X86_SEG_SUPPORT)) 529 return this_cpu_read_const(const_pcpu_hot.top_of_stack); 530 531 return this_cpu_read_stable(pcpu_hot.top_of_stack); 532 } 533 534 static __always_inline bool on_thread_stack(void) 535 { 536 return (unsigned long)(current_top_of_stack() - 537 current_stack_pointer) < THREAD_SIZE; 538 } 539 540 #ifdef CONFIG_PARAVIRT_XXL 541 #include <asm/paravirt.h> 542 #else 543 544 static inline void load_sp0(unsigned long sp0) 545 { 546 native_load_sp0(sp0); 547 } 548 549 #endif /* CONFIG_PARAVIRT_XXL */ 550 551 unsigned long __get_wchan(struct task_struct *p); 552 553 extern void select_idle_routine(void); 554 extern void amd_e400_c1e_apic_setup(void); 555 556 extern unsigned long boot_option_idle_override; 557 558 enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_NOMWAIT, 559 IDLE_POLL}; 560 561 extern void enable_sep_cpu(void); 562 563 564 /* Defined in head.S */ 565 extern struct desc_ptr early_gdt_descr; 566 567 extern void switch_gdt_and_percpu_base(int); 568 extern void load_direct_gdt(int); 569 extern void load_fixmap_gdt(int); 570 extern void cpu_init(void); 571 extern void cpu_init_exception_handling(void); 572 extern void cr4_init(void); 573 574 extern void set_task_blockstep(struct task_struct *task, bool on); 575 576 /* Boot loader type from the setup header: */ 577 extern int bootloader_type; 578 extern int bootloader_version; 579 580 extern char ignore_fpu_irq; 581 582 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1 583 #define ARCH_HAS_PREFETCHW 584 585 #ifdef CONFIG_X86_32 586 # define BASE_PREFETCH "" 587 # define ARCH_HAS_PREFETCH 588 #else 589 # define BASE_PREFETCH "prefetcht0 %P1" 590 #endif 591 592 /* 593 * Prefetch instructions for Pentium III (+) and AMD Athlon (+) 594 * 595 * It's not worth to care about 3dnow prefetches for the K6 596 * because they are microcoded there and very slow. 597 */ 598 static inline void prefetch(const void *x) 599 { 600 alternative_input(BASE_PREFETCH, "prefetchnta %P1", 601 X86_FEATURE_XMM, 602 "m" (*(const char *)x)); 603 } 604 605 /* 606 * 3dnow prefetch to get an exclusive cache line. 607 * Useful for spinlocks to avoid one state transition in the 608 * cache coherency protocol: 609 */ 610 static __always_inline void prefetchw(const void *x) 611 { 612 alternative_input(BASE_PREFETCH, "prefetchw %P1", 613 X86_FEATURE_3DNOWPREFETCH, 614 "m" (*(const char *)x)); 615 } 616 617 #define TOP_OF_INIT_STACK ((unsigned long)&init_stack + sizeof(init_stack) - \ 618 TOP_OF_KERNEL_STACK_PADDING) 619 620 #define task_top_of_stack(task) ((unsigned long)(task_pt_regs(task) + 1)) 621 622 #define task_pt_regs(task) \ 623 ({ \ 624 unsigned long __ptr = (unsigned long)task_stack_page(task); \ 625 __ptr += THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING; \ 626 ((struct pt_regs *)__ptr) - 1; \ 627 }) 628 629 #ifdef CONFIG_X86_32 630 #define INIT_THREAD { \ 631 .sp0 = TOP_OF_INIT_STACK, \ 632 .sysenter_cs = __KERNEL_CS, \ 633 } 634 635 #define KSTK_ESP(task) (task_pt_regs(task)->sp) 636 637 #else 638 extern unsigned long __end_init_task[]; 639 640 #define INIT_THREAD { \ 641 .sp = (unsigned long)&__end_init_task - \ 642 TOP_OF_KERNEL_STACK_PADDING - \ 643 sizeof(struct pt_regs), \ 644 } 645 646 extern unsigned long KSTK_ESP(struct task_struct *task); 647 648 #endif /* CONFIG_X86_64 */ 649 650 extern void start_thread(struct pt_regs *regs, unsigned long new_ip, 651 unsigned long new_sp); 652 653 /* 654 * This decides where the kernel will search for a free chunk of vm 655 * space during mmap's. 656 */ 657 #define __TASK_UNMAPPED_BASE(task_size) (PAGE_ALIGN(task_size / 3)) 658 #define TASK_UNMAPPED_BASE __TASK_UNMAPPED_BASE(TASK_SIZE_LOW) 659 660 #define KSTK_EIP(task) (task_pt_regs(task)->ip) 661 662 /* Get/set a process' ability to use the timestamp counter instruction */ 663 #define GET_TSC_CTL(adr) get_tsc_mode((adr)) 664 #define SET_TSC_CTL(val) set_tsc_mode((val)) 665 666 extern int get_tsc_mode(unsigned long adr); 667 extern int set_tsc_mode(unsigned int val); 668 669 DECLARE_PER_CPU(u64, msr_misc_features_shadow); 670 671 static inline u32 per_cpu_llc_id(unsigned int cpu) 672 { 673 return per_cpu(cpu_info.topo.llc_id, cpu); 674 } 675 676 static inline u32 per_cpu_l2c_id(unsigned int cpu) 677 { 678 return per_cpu(cpu_info.topo.l2c_id, cpu); 679 } 680 681 #ifdef CONFIG_CPU_SUP_AMD 682 extern u32 amd_get_highest_perf(void); 683 extern void amd_clear_divider(void); 684 extern void amd_check_microcode(void); 685 #else 686 static inline u32 amd_get_highest_perf(void) { return 0; } 687 static inline void amd_clear_divider(void) { } 688 static inline void amd_check_microcode(void) { } 689 #endif 690 691 extern unsigned long arch_align_stack(unsigned long sp); 692 void free_init_pages(const char *what, unsigned long begin, unsigned long end); 693 extern void free_kernel_image_pages(const char *what, void *begin, void *end); 694 695 void default_idle(void); 696 #ifdef CONFIG_XEN 697 bool xen_set_default_idle(void); 698 #else 699 #define xen_set_default_idle 0 700 #endif 701 702 void __noreturn stop_this_cpu(void *dummy); 703 void microcode_check(struct cpuinfo_x86 *prev_info); 704 void store_cpu_caps(struct cpuinfo_x86 *info); 705 706 enum l1tf_mitigations { 707 L1TF_MITIGATION_OFF, 708 L1TF_MITIGATION_FLUSH_NOWARN, 709 L1TF_MITIGATION_FLUSH, 710 L1TF_MITIGATION_FLUSH_NOSMT, 711 L1TF_MITIGATION_FULL, 712 L1TF_MITIGATION_FULL_FORCE 713 }; 714 715 extern enum l1tf_mitigations l1tf_mitigation; 716 717 enum mds_mitigations { 718 MDS_MITIGATION_OFF, 719 MDS_MITIGATION_FULL, 720 MDS_MITIGATION_VMWERV, 721 }; 722 723 extern bool gds_ucode_mitigated(void); 724 725 /* 726 * Make previous memory operations globally visible before 727 * a WRMSR. 728 * 729 * MFENCE makes writes visible, but only affects load/store 730 * instructions. WRMSR is unfortunately not a load/store 731 * instruction and is unaffected by MFENCE. The LFENCE ensures 732 * that the WRMSR is not reordered. 733 * 734 * Most WRMSRs are full serializing instructions themselves and 735 * do not require this barrier. This is only required for the 736 * IA32_TSC_DEADLINE and X2APIC MSRs. 737 */ 738 static inline void weak_wrmsr_fence(void) 739 { 740 alternative("mfence; lfence", "", ALT_NOT(X86_FEATURE_APIC_MSRS_FENCE)); 741 } 742 743 #endif /* _ASM_X86_PROCESSOR_H */ 744