1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _ASM_X86_PROCESSOR_H 3 #define _ASM_X86_PROCESSOR_H 4 5 #include <asm/processor-flags.h> 6 7 /* Forward declaration, a strange C thing */ 8 struct task_struct; 9 struct mm_struct; 10 struct io_bitmap; 11 struct vm86; 12 13 #include <asm/math_emu.h> 14 #include <asm/segment.h> 15 #include <asm/types.h> 16 #include <uapi/asm/sigcontext.h> 17 #include <asm/current.h> 18 #include <asm/cpufeatures.h> 19 #include <asm/cpuid.h> 20 #include <asm/page.h> 21 #include <asm/pgtable_types.h> 22 #include <asm/percpu.h> 23 #include <asm/msr.h> 24 #include <asm/desc_defs.h> 25 #include <asm/nops.h> 26 #include <asm/special_insns.h> 27 #include <asm/fpu/types.h> 28 #include <asm/unwind_hints.h> 29 #include <asm/vmxfeatures.h> 30 #include <asm/vdso/processor.h> 31 #include <asm/shstk.h> 32 33 #include <linux/personality.h> 34 #include <linux/cache.h> 35 #include <linux/threads.h> 36 #include <linux/math64.h> 37 #include <linux/err.h> 38 #include <linux/irqflags.h> 39 #include <linux/mem_encrypt.h> 40 41 /* 42 * We handle most unaligned accesses in hardware. On the other hand 43 * unaligned DMA can be quite expensive on some Nehalem processors. 44 * 45 * Based on this we disable the IP header alignment in network drivers. 46 */ 47 #define NET_IP_ALIGN 0 48 49 #define HBP_NUM 4 50 51 /* 52 * These alignment constraints are for performance in the vSMP case, 53 * but in the task_struct case we must also meet hardware imposed 54 * alignment requirements of the FPU state: 55 */ 56 #ifdef CONFIG_X86_VSMP 57 # define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT) 58 # define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT) 59 #else 60 # define ARCH_MIN_TASKALIGN __alignof__(union fpregs_state) 61 # define ARCH_MIN_MMSTRUCT_ALIGN 0 62 #endif 63 64 enum tlb_infos { 65 ENTRIES, 66 NR_INFO 67 }; 68 69 extern u16 __read_mostly tlb_lli_4k[NR_INFO]; 70 extern u16 __read_mostly tlb_lli_2m[NR_INFO]; 71 extern u16 __read_mostly tlb_lli_4m[NR_INFO]; 72 extern u16 __read_mostly tlb_lld_4k[NR_INFO]; 73 extern u16 __read_mostly tlb_lld_2m[NR_INFO]; 74 extern u16 __read_mostly tlb_lld_4m[NR_INFO]; 75 extern u16 __read_mostly tlb_lld_1g[NR_INFO]; 76 77 /* 78 * CPU type and hardware bug flags. Kept separately for each CPU. 79 */ 80 81 struct cpuinfo_topology { 82 // Real APIC ID read from the local APIC 83 u32 apicid; 84 // The initial APIC ID provided by CPUID 85 u32 initial_apicid; 86 87 // Physical package ID 88 u32 pkg_id; 89 90 // Physical die ID on AMD, Relative on Intel 91 u32 die_id; 92 93 // Compute unit ID - AMD specific 94 u32 cu_id; 95 96 // Core ID relative to the package 97 u32 core_id; 98 99 // Logical ID mappings 100 u32 logical_pkg_id; 101 u32 logical_die_id; 102 103 // Cache level topology IDs 104 u32 llc_id; 105 u32 l2c_id; 106 }; 107 108 struct cpuinfo_x86 { 109 __u8 x86; /* CPU family */ 110 __u8 x86_vendor; /* CPU vendor */ 111 __u8 x86_model; 112 __u8 x86_stepping; 113 #ifdef CONFIG_X86_64 114 /* Number of 4K pages in DTLB/ITLB combined(in pages): */ 115 int x86_tlbsize; 116 #endif 117 #ifdef CONFIG_X86_VMX_FEATURE_NAMES 118 __u32 vmx_capability[NVMXINTS]; 119 #endif 120 __u8 x86_virt_bits; 121 __u8 x86_phys_bits; 122 /* CPUID returned core id bits: */ 123 __u8 x86_coreid_bits; 124 /* Max extended CPUID function supported: */ 125 __u32 extended_cpuid_level; 126 /* Maximum supported CPUID level, -1=no CPUID: */ 127 int cpuid_level; 128 /* 129 * Align to size of unsigned long because the x86_capability array 130 * is passed to bitops which require the alignment. Use unnamed 131 * union to enforce the array is aligned to size of unsigned long. 132 */ 133 union { 134 __u32 x86_capability[NCAPINTS + NBUGINTS]; 135 unsigned long x86_capability_alignment; 136 }; 137 char x86_vendor_id[16]; 138 char x86_model_id[64]; 139 struct cpuinfo_topology topo; 140 /* in KB - valid for CPUS which support this call: */ 141 unsigned int x86_cache_size; 142 int x86_cache_alignment; /* In bytes */ 143 /* Cache QoS architectural values, valid only on the BSP: */ 144 int x86_cache_max_rmid; /* max index */ 145 int x86_cache_occ_scale; /* scale to bytes */ 146 int x86_cache_mbm_width_offset; 147 int x86_power; 148 unsigned long loops_per_jiffy; 149 /* protected processor identification number */ 150 u64 ppin; 151 /* cpuid returned max cores value: */ 152 u16 x86_max_cores; 153 u16 x86_clflush_size; 154 /* number of cores as seen by the OS: */ 155 u16 booted_cores; 156 /* Index into per_cpu list: */ 157 u16 cpu_index; 158 /* Is SMT active on this core? */ 159 bool smt_active; 160 u32 microcode; 161 /* Address space bits used by the cache internally */ 162 u8 x86_cache_bits; 163 unsigned initialized : 1; 164 } __randomize_layout; 165 166 #define X86_VENDOR_INTEL 0 167 #define X86_VENDOR_CYRIX 1 168 #define X86_VENDOR_AMD 2 169 #define X86_VENDOR_UMC 3 170 #define X86_VENDOR_CENTAUR 5 171 #define X86_VENDOR_TRANSMETA 7 172 #define X86_VENDOR_NSC 8 173 #define X86_VENDOR_HYGON 9 174 #define X86_VENDOR_ZHAOXIN 10 175 #define X86_VENDOR_VORTEX 11 176 #define X86_VENDOR_NUM 12 177 178 #define X86_VENDOR_UNKNOWN 0xff 179 180 /* 181 * capabilities of CPUs 182 */ 183 extern struct cpuinfo_x86 boot_cpu_data; 184 extern struct cpuinfo_x86 new_cpu_data; 185 186 extern __u32 cpu_caps_cleared[NCAPINTS + NBUGINTS]; 187 extern __u32 cpu_caps_set[NCAPINTS + NBUGINTS]; 188 189 #ifdef CONFIG_SMP 190 DECLARE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info); 191 #define cpu_data(cpu) per_cpu(cpu_info, cpu) 192 #else 193 #define cpu_info boot_cpu_data 194 #define cpu_data(cpu) boot_cpu_data 195 #endif 196 197 extern const struct seq_operations cpuinfo_op; 198 199 #define cache_line_size() (boot_cpu_data.x86_cache_alignment) 200 201 extern void cpu_detect(struct cpuinfo_x86 *c); 202 203 static inline unsigned long long l1tf_pfn_limit(void) 204 { 205 return BIT_ULL(boot_cpu_data.x86_cache_bits - 1 - PAGE_SHIFT); 206 } 207 208 extern void early_cpu_init(void); 209 extern void identify_secondary_cpu(struct cpuinfo_x86 *); 210 extern void print_cpu_info(struct cpuinfo_x86 *); 211 void print_cpu_msr(struct cpuinfo_x86 *); 212 213 /* 214 * Friendlier CR3 helpers. 215 */ 216 static inline unsigned long read_cr3_pa(void) 217 { 218 return __read_cr3() & CR3_ADDR_MASK; 219 } 220 221 static inline unsigned long native_read_cr3_pa(void) 222 { 223 return __native_read_cr3() & CR3_ADDR_MASK; 224 } 225 226 static inline void load_cr3(pgd_t *pgdir) 227 { 228 write_cr3(__sme_pa(pgdir)); 229 } 230 231 /* 232 * Note that while the legacy 'TSS' name comes from 'Task State Segment', 233 * on modern x86 CPUs the TSS also holds information important to 64-bit mode, 234 * unrelated to the task-switch mechanism: 235 */ 236 #ifdef CONFIG_X86_32 237 /* This is the TSS defined by the hardware. */ 238 struct x86_hw_tss { 239 unsigned short back_link, __blh; 240 unsigned long sp0; 241 unsigned short ss0, __ss0h; 242 unsigned long sp1; 243 244 /* 245 * We don't use ring 1, so ss1 is a convenient scratch space in 246 * the same cacheline as sp0. We use ss1 to cache the value in 247 * MSR_IA32_SYSENTER_CS. When we context switch 248 * MSR_IA32_SYSENTER_CS, we first check if the new value being 249 * written matches ss1, and, if it's not, then we wrmsr the new 250 * value and update ss1. 251 * 252 * The only reason we context switch MSR_IA32_SYSENTER_CS is 253 * that we set it to zero in vm86 tasks to avoid corrupting the 254 * stack if we were to go through the sysenter path from vm86 255 * mode. 256 */ 257 unsigned short ss1; /* MSR_IA32_SYSENTER_CS */ 258 259 unsigned short __ss1h; 260 unsigned long sp2; 261 unsigned short ss2, __ss2h; 262 unsigned long __cr3; 263 unsigned long ip; 264 unsigned long flags; 265 unsigned long ax; 266 unsigned long cx; 267 unsigned long dx; 268 unsigned long bx; 269 unsigned long sp; 270 unsigned long bp; 271 unsigned long si; 272 unsigned long di; 273 unsigned short es, __esh; 274 unsigned short cs, __csh; 275 unsigned short ss, __ssh; 276 unsigned short ds, __dsh; 277 unsigned short fs, __fsh; 278 unsigned short gs, __gsh; 279 unsigned short ldt, __ldth; 280 unsigned short trace; 281 unsigned short io_bitmap_base; 282 283 } __attribute__((packed)); 284 #else 285 struct x86_hw_tss { 286 u32 reserved1; 287 u64 sp0; 288 u64 sp1; 289 290 /* 291 * Since Linux does not use ring 2, the 'sp2' slot is unused by 292 * hardware. entry_SYSCALL_64 uses it as scratch space to stash 293 * the user RSP value. 294 */ 295 u64 sp2; 296 297 u64 reserved2; 298 u64 ist[7]; 299 u32 reserved3; 300 u32 reserved4; 301 u16 reserved5; 302 u16 io_bitmap_base; 303 304 } __attribute__((packed)); 305 #endif 306 307 /* 308 * IO-bitmap sizes: 309 */ 310 #define IO_BITMAP_BITS 65536 311 #define IO_BITMAP_BYTES (IO_BITMAP_BITS / BITS_PER_BYTE) 312 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES / sizeof(long)) 313 314 #define IO_BITMAP_OFFSET_VALID_MAP \ 315 (offsetof(struct tss_struct, io_bitmap.bitmap) - \ 316 offsetof(struct tss_struct, x86_tss)) 317 318 #define IO_BITMAP_OFFSET_VALID_ALL \ 319 (offsetof(struct tss_struct, io_bitmap.mapall) - \ 320 offsetof(struct tss_struct, x86_tss)) 321 322 #ifdef CONFIG_X86_IOPL_IOPERM 323 /* 324 * sizeof(unsigned long) coming from an extra "long" at the end of the 325 * iobitmap. The limit is inclusive, i.e. the last valid byte. 326 */ 327 # define __KERNEL_TSS_LIMIT \ 328 (IO_BITMAP_OFFSET_VALID_ALL + IO_BITMAP_BYTES + \ 329 sizeof(unsigned long) - 1) 330 #else 331 # define __KERNEL_TSS_LIMIT \ 332 (offsetof(struct tss_struct, x86_tss) + sizeof(struct x86_hw_tss) - 1) 333 #endif 334 335 /* Base offset outside of TSS_LIMIT so unpriviledged IO causes #GP */ 336 #define IO_BITMAP_OFFSET_INVALID (__KERNEL_TSS_LIMIT + 1) 337 338 struct entry_stack { 339 char stack[PAGE_SIZE]; 340 }; 341 342 struct entry_stack_page { 343 struct entry_stack stack; 344 } __aligned(PAGE_SIZE); 345 346 /* 347 * All IO bitmap related data stored in the TSS: 348 */ 349 struct x86_io_bitmap { 350 /* The sequence number of the last active bitmap. */ 351 u64 prev_sequence; 352 353 /* 354 * Store the dirty size of the last io bitmap offender. The next 355 * one will have to do the cleanup as the switch out to a non io 356 * bitmap user will just set x86_tss.io_bitmap_base to a value 357 * outside of the TSS limit. So for sane tasks there is no need to 358 * actually touch the io_bitmap at all. 359 */ 360 unsigned int prev_max; 361 362 /* 363 * The extra 1 is there because the CPU will access an 364 * additional byte beyond the end of the IO permission 365 * bitmap. The extra byte must be all 1 bits, and must 366 * be within the limit. 367 */ 368 unsigned long bitmap[IO_BITMAP_LONGS + 1]; 369 370 /* 371 * Special I/O bitmap to emulate IOPL(3). All bytes zero, 372 * except the additional byte at the end. 373 */ 374 unsigned long mapall[IO_BITMAP_LONGS + 1]; 375 }; 376 377 struct tss_struct { 378 /* 379 * The fixed hardware portion. This must not cross a page boundary 380 * at risk of violating the SDM's advice and potentially triggering 381 * errata. 382 */ 383 struct x86_hw_tss x86_tss; 384 385 struct x86_io_bitmap io_bitmap; 386 } __aligned(PAGE_SIZE); 387 388 DECLARE_PER_CPU_PAGE_ALIGNED(struct tss_struct, cpu_tss_rw); 389 390 /* Per CPU interrupt stacks */ 391 struct irq_stack { 392 char stack[IRQ_STACK_SIZE]; 393 } __aligned(IRQ_STACK_SIZE); 394 395 #ifdef CONFIG_X86_64 396 struct fixed_percpu_data { 397 /* 398 * GCC hardcodes the stack canary as %gs:40. Since the 399 * irq_stack is the object at %gs:0, we reserve the bottom 400 * 48 bytes of the irq stack for the canary. 401 * 402 * Once we are willing to require -mstack-protector-guard-symbol= 403 * support for x86_64 stackprotector, we can get rid of this. 404 */ 405 char gs_base[40]; 406 unsigned long stack_canary; 407 }; 408 409 DECLARE_PER_CPU_FIRST(struct fixed_percpu_data, fixed_percpu_data) __visible; 410 DECLARE_INIT_PER_CPU(fixed_percpu_data); 411 412 static inline unsigned long cpu_kernelmode_gs_base(int cpu) 413 { 414 return (unsigned long)per_cpu(fixed_percpu_data.gs_base, cpu); 415 } 416 417 extern asmlinkage void entry_SYSCALL32_ignore(void); 418 419 /* Save actual FS/GS selectors and bases to current->thread */ 420 void current_save_fsgs(void); 421 #else /* X86_64 */ 422 #ifdef CONFIG_STACKPROTECTOR 423 DECLARE_PER_CPU(unsigned long, __stack_chk_guard); 424 #endif 425 #endif /* !X86_64 */ 426 427 struct perf_event; 428 429 struct thread_struct { 430 /* Cached TLS descriptors: */ 431 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES]; 432 #ifdef CONFIG_X86_32 433 unsigned long sp0; 434 #endif 435 unsigned long sp; 436 #ifdef CONFIG_X86_32 437 unsigned long sysenter_cs; 438 #else 439 unsigned short es; 440 unsigned short ds; 441 unsigned short fsindex; 442 unsigned short gsindex; 443 #endif 444 445 #ifdef CONFIG_X86_64 446 unsigned long fsbase; 447 unsigned long gsbase; 448 #else 449 /* 450 * XXX: this could presumably be unsigned short. Alternatively, 451 * 32-bit kernels could be taught to use fsindex instead. 452 */ 453 unsigned long fs; 454 unsigned long gs; 455 #endif 456 457 /* Save middle states of ptrace breakpoints */ 458 struct perf_event *ptrace_bps[HBP_NUM]; 459 /* Debug status used for traps, single steps, etc... */ 460 unsigned long virtual_dr6; 461 /* Keep track of the exact dr7 value set by the user */ 462 unsigned long ptrace_dr7; 463 /* Fault info: */ 464 unsigned long cr2; 465 unsigned long trap_nr; 466 unsigned long error_code; 467 #ifdef CONFIG_VM86 468 /* Virtual 86 mode info */ 469 struct vm86 *vm86; 470 #endif 471 /* IO permissions: */ 472 struct io_bitmap *io_bitmap; 473 474 /* 475 * IOPL. Privilege level dependent I/O permission which is 476 * emulated via the I/O bitmap to prevent user space from disabling 477 * interrupts. 478 */ 479 unsigned long iopl_emul; 480 481 unsigned int iopl_warn:1; 482 unsigned int sig_on_uaccess_err:1; 483 484 /* 485 * Protection Keys Register for Userspace. Loaded immediately on 486 * context switch. Store it in thread_struct to avoid a lookup in 487 * the tasks's FPU xstate buffer. This value is only valid when a 488 * task is scheduled out. For 'current' the authoritative source of 489 * PKRU is the hardware itself. 490 */ 491 u32 pkru; 492 493 #ifdef CONFIG_X86_USER_SHADOW_STACK 494 unsigned long features; 495 unsigned long features_locked; 496 497 struct thread_shstk shstk; 498 #endif 499 500 /* Floating point and extended processor state */ 501 struct fpu fpu; 502 /* 503 * WARNING: 'fpu' is dynamically-sized. It *MUST* be at 504 * the end. 505 */ 506 }; 507 508 extern void fpu_thread_struct_whitelist(unsigned long *offset, unsigned long *size); 509 510 static inline void arch_thread_struct_whitelist(unsigned long *offset, 511 unsigned long *size) 512 { 513 fpu_thread_struct_whitelist(offset, size); 514 } 515 516 static inline void 517 native_load_sp0(unsigned long sp0) 518 { 519 this_cpu_write(cpu_tss_rw.x86_tss.sp0, sp0); 520 } 521 522 static __always_inline void native_swapgs(void) 523 { 524 #ifdef CONFIG_X86_64 525 asm volatile("swapgs" ::: "memory"); 526 #endif 527 } 528 529 static __always_inline unsigned long current_top_of_stack(void) 530 { 531 /* 532 * We can't read directly from tss.sp0: sp0 on x86_32 is special in 533 * and around vm86 mode and sp0 on x86_64 is special because of the 534 * entry trampoline. 535 */ 536 return this_cpu_read_stable(pcpu_hot.top_of_stack); 537 } 538 539 static __always_inline bool on_thread_stack(void) 540 { 541 return (unsigned long)(current_top_of_stack() - 542 current_stack_pointer) < THREAD_SIZE; 543 } 544 545 #ifdef CONFIG_PARAVIRT_XXL 546 #include <asm/paravirt.h> 547 #else 548 549 static inline void load_sp0(unsigned long sp0) 550 { 551 native_load_sp0(sp0); 552 } 553 554 #endif /* CONFIG_PARAVIRT_XXL */ 555 556 unsigned long __get_wchan(struct task_struct *p); 557 558 extern void select_idle_routine(const struct cpuinfo_x86 *c); 559 extern void amd_e400_c1e_apic_setup(void); 560 561 extern unsigned long boot_option_idle_override; 562 563 enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_NOMWAIT, 564 IDLE_POLL}; 565 566 extern void enable_sep_cpu(void); 567 568 569 /* Defined in head.S */ 570 extern struct desc_ptr early_gdt_descr; 571 572 extern void switch_gdt_and_percpu_base(int); 573 extern void load_direct_gdt(int); 574 extern void load_fixmap_gdt(int); 575 extern void cpu_init(void); 576 extern void cpu_init_exception_handling(void); 577 extern void cr4_init(void); 578 579 static inline unsigned long get_debugctlmsr(void) 580 { 581 unsigned long debugctlmsr = 0; 582 583 #ifndef CONFIG_X86_DEBUGCTLMSR 584 if (boot_cpu_data.x86 < 6) 585 return 0; 586 #endif 587 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr); 588 589 return debugctlmsr; 590 } 591 592 static inline void update_debugctlmsr(unsigned long debugctlmsr) 593 { 594 #ifndef CONFIG_X86_DEBUGCTLMSR 595 if (boot_cpu_data.x86 < 6) 596 return; 597 #endif 598 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr); 599 } 600 601 extern void set_task_blockstep(struct task_struct *task, bool on); 602 603 /* Boot loader type from the setup header: */ 604 extern int bootloader_type; 605 extern int bootloader_version; 606 607 extern char ignore_fpu_irq; 608 609 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1 610 #define ARCH_HAS_PREFETCHW 611 612 #ifdef CONFIG_X86_32 613 # define BASE_PREFETCH "" 614 # define ARCH_HAS_PREFETCH 615 #else 616 # define BASE_PREFETCH "prefetcht0 %P1" 617 #endif 618 619 /* 620 * Prefetch instructions for Pentium III (+) and AMD Athlon (+) 621 * 622 * It's not worth to care about 3dnow prefetches for the K6 623 * because they are microcoded there and very slow. 624 */ 625 static inline void prefetch(const void *x) 626 { 627 alternative_input(BASE_PREFETCH, "prefetchnta %P1", 628 X86_FEATURE_XMM, 629 "m" (*(const char *)x)); 630 } 631 632 /* 633 * 3dnow prefetch to get an exclusive cache line. 634 * Useful for spinlocks to avoid one state transition in the 635 * cache coherency protocol: 636 */ 637 static __always_inline void prefetchw(const void *x) 638 { 639 alternative_input(BASE_PREFETCH, "prefetchw %P1", 640 X86_FEATURE_3DNOWPREFETCH, 641 "m" (*(const char *)x)); 642 } 643 644 #define TOP_OF_INIT_STACK ((unsigned long)&init_stack + sizeof(init_stack) - \ 645 TOP_OF_KERNEL_STACK_PADDING) 646 647 #define task_top_of_stack(task) ((unsigned long)(task_pt_regs(task) + 1)) 648 649 #define task_pt_regs(task) \ 650 ({ \ 651 unsigned long __ptr = (unsigned long)task_stack_page(task); \ 652 __ptr += THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING; \ 653 ((struct pt_regs *)__ptr) - 1; \ 654 }) 655 656 #ifdef CONFIG_X86_32 657 #define INIT_THREAD { \ 658 .sp0 = TOP_OF_INIT_STACK, \ 659 .sysenter_cs = __KERNEL_CS, \ 660 } 661 662 #define KSTK_ESP(task) (task_pt_regs(task)->sp) 663 664 #else 665 extern unsigned long __end_init_task[]; 666 667 #define INIT_THREAD { \ 668 .sp = (unsigned long)&__end_init_task - sizeof(struct pt_regs), \ 669 } 670 671 extern unsigned long KSTK_ESP(struct task_struct *task); 672 673 #endif /* CONFIG_X86_64 */ 674 675 extern void start_thread(struct pt_regs *regs, unsigned long new_ip, 676 unsigned long new_sp); 677 678 /* 679 * This decides where the kernel will search for a free chunk of vm 680 * space during mmap's. 681 */ 682 #define __TASK_UNMAPPED_BASE(task_size) (PAGE_ALIGN(task_size / 3)) 683 #define TASK_UNMAPPED_BASE __TASK_UNMAPPED_BASE(TASK_SIZE_LOW) 684 685 #define KSTK_EIP(task) (task_pt_regs(task)->ip) 686 687 /* Get/set a process' ability to use the timestamp counter instruction */ 688 #define GET_TSC_CTL(adr) get_tsc_mode((adr)) 689 #define SET_TSC_CTL(val) set_tsc_mode((val)) 690 691 extern int get_tsc_mode(unsigned long adr); 692 extern int set_tsc_mode(unsigned int val); 693 694 DECLARE_PER_CPU(u64, msr_misc_features_shadow); 695 696 static inline u32 per_cpu_llc_id(unsigned int cpu) 697 { 698 return per_cpu(cpu_info.topo.llc_id, cpu); 699 } 700 701 static inline u32 per_cpu_l2c_id(unsigned int cpu) 702 { 703 return per_cpu(cpu_info.topo.l2c_id, cpu); 704 } 705 706 #ifdef CONFIG_CPU_SUP_AMD 707 extern u32 amd_get_nodes_per_socket(void); 708 extern u32 amd_get_highest_perf(void); 709 extern void amd_clear_divider(void); 710 extern void amd_check_microcode(void); 711 #else 712 static inline u32 amd_get_nodes_per_socket(void) { return 0; } 713 static inline u32 amd_get_highest_perf(void) { return 0; } 714 static inline void amd_clear_divider(void) { } 715 static inline void amd_check_microcode(void) { } 716 #endif 717 718 extern unsigned long arch_align_stack(unsigned long sp); 719 void free_init_pages(const char *what, unsigned long begin, unsigned long end); 720 extern void free_kernel_image_pages(const char *what, void *begin, void *end); 721 722 void default_idle(void); 723 #ifdef CONFIG_XEN 724 bool xen_set_default_idle(void); 725 #else 726 #define xen_set_default_idle 0 727 #endif 728 729 void __noreturn stop_this_cpu(void *dummy); 730 void microcode_check(struct cpuinfo_x86 *prev_info); 731 void store_cpu_caps(struct cpuinfo_x86 *info); 732 733 enum l1tf_mitigations { 734 L1TF_MITIGATION_OFF, 735 L1TF_MITIGATION_FLUSH_NOWARN, 736 L1TF_MITIGATION_FLUSH, 737 L1TF_MITIGATION_FLUSH_NOSMT, 738 L1TF_MITIGATION_FULL, 739 L1TF_MITIGATION_FULL_FORCE 740 }; 741 742 extern enum l1tf_mitigations l1tf_mitigation; 743 744 enum mds_mitigations { 745 MDS_MITIGATION_OFF, 746 MDS_MITIGATION_FULL, 747 MDS_MITIGATION_VMWERV, 748 }; 749 750 extern bool gds_ucode_mitigated(void); 751 752 /* 753 * Make previous memory operations globally visible before 754 * a WRMSR. 755 * 756 * MFENCE makes writes visible, but only affects load/store 757 * instructions. WRMSR is unfortunately not a load/store 758 * instruction and is unaffected by MFENCE. The LFENCE ensures 759 * that the WRMSR is not reordered. 760 * 761 * Most WRMSRs are full serializing instructions themselves and 762 * do not require this barrier. This is only required for the 763 * IA32_TSC_DEADLINE and X2APIC MSRs. 764 */ 765 static inline void weak_wrmsr_fence(void) 766 { 767 alternative("mfence; lfence", "", ALT_NOT(X86_FEATURE_APIC_MSRS_FENCE)); 768 } 769 770 #endif /* _ASM_X86_PROCESSOR_H */ 771