1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _ASM_X86_PROCESSOR_H 3 #define _ASM_X86_PROCESSOR_H 4 5 #include <asm/processor-flags.h> 6 7 /* Forward declaration, a strange C thing */ 8 struct task_struct; 9 struct mm_struct; 10 struct io_bitmap; 11 struct vm86; 12 13 #include <asm/math_emu.h> 14 #include <asm/segment.h> 15 #include <asm/types.h> 16 #include <uapi/asm/sigcontext.h> 17 #include <asm/current.h> 18 #include <asm/cpufeatures.h> 19 #include <asm/page.h> 20 #include <asm/pgtable_types.h> 21 #include <asm/percpu.h> 22 #include <asm/msr.h> 23 #include <asm/desc_defs.h> 24 #include <asm/nops.h> 25 #include <asm/special_insns.h> 26 #include <asm/fpu/types.h> 27 #include <asm/unwind_hints.h> 28 29 #include <linux/personality.h> 30 #include <linux/cache.h> 31 #include <linux/threads.h> 32 #include <linux/math64.h> 33 #include <linux/err.h> 34 #include <linux/irqflags.h> 35 #include <linux/mem_encrypt.h> 36 37 /* 38 * We handle most unaligned accesses in hardware. On the other hand 39 * unaligned DMA can be quite expensive on some Nehalem processors. 40 * 41 * Based on this we disable the IP header alignment in network drivers. 42 */ 43 #define NET_IP_ALIGN 0 44 45 #define HBP_NUM 4 46 47 /* 48 * These alignment constraints are for performance in the vSMP case, 49 * but in the task_struct case we must also meet hardware imposed 50 * alignment requirements of the FPU state: 51 */ 52 #ifdef CONFIG_X86_VSMP 53 # define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT) 54 # define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT) 55 #else 56 # define ARCH_MIN_TASKALIGN __alignof__(union fpregs_state) 57 # define ARCH_MIN_MMSTRUCT_ALIGN 0 58 #endif 59 60 enum tlb_infos { 61 ENTRIES, 62 NR_INFO 63 }; 64 65 extern u16 __read_mostly tlb_lli_4k[NR_INFO]; 66 extern u16 __read_mostly tlb_lli_2m[NR_INFO]; 67 extern u16 __read_mostly tlb_lli_4m[NR_INFO]; 68 extern u16 __read_mostly tlb_lld_4k[NR_INFO]; 69 extern u16 __read_mostly tlb_lld_2m[NR_INFO]; 70 extern u16 __read_mostly tlb_lld_4m[NR_INFO]; 71 extern u16 __read_mostly tlb_lld_1g[NR_INFO]; 72 73 /* 74 * CPU type and hardware bug flags. Kept separately for each CPU. 75 * Members of this structure are referenced in head_32.S, so think twice 76 * before touching them. [mj] 77 */ 78 79 struct cpuinfo_x86 { 80 __u8 x86; /* CPU family */ 81 __u8 x86_vendor; /* CPU vendor */ 82 __u8 x86_model; 83 __u8 x86_stepping; 84 #ifdef CONFIG_X86_64 85 /* Number of 4K pages in DTLB/ITLB combined(in pages): */ 86 int x86_tlbsize; 87 #endif 88 __u8 x86_virt_bits; 89 __u8 x86_phys_bits; 90 /* CPUID returned core id bits: */ 91 __u8 x86_coreid_bits; 92 __u8 cu_id; 93 /* Max extended CPUID function supported: */ 94 __u32 extended_cpuid_level; 95 /* Maximum supported CPUID level, -1=no CPUID: */ 96 int cpuid_level; 97 /* 98 * Align to size of unsigned long because the x86_capability array 99 * is passed to bitops which require the alignment. Use unnamed 100 * union to enforce the array is aligned to size of unsigned long. 101 */ 102 union { 103 __u32 x86_capability[NCAPINTS + NBUGINTS]; 104 unsigned long x86_capability_alignment; 105 }; 106 char x86_vendor_id[16]; 107 char x86_model_id[64]; 108 /* in KB - valid for CPUS which support this call: */ 109 unsigned int x86_cache_size; 110 int x86_cache_alignment; /* In bytes */ 111 /* Cache QoS architectural values: */ 112 int x86_cache_max_rmid; /* max index */ 113 int x86_cache_occ_scale; /* scale to bytes */ 114 int x86_power; 115 unsigned long loops_per_jiffy; 116 /* cpuid returned max cores value: */ 117 u16 x86_max_cores; 118 u16 apicid; 119 u16 initial_apicid; 120 u16 x86_clflush_size; 121 /* number of cores as seen by the OS: */ 122 u16 booted_cores; 123 /* Physical processor id: */ 124 u16 phys_proc_id; 125 /* Logical processor id: */ 126 u16 logical_proc_id; 127 /* Core id: */ 128 u16 cpu_core_id; 129 u16 cpu_die_id; 130 u16 logical_die_id; 131 /* Index into per_cpu list: */ 132 u16 cpu_index; 133 u32 microcode; 134 /* Address space bits used by the cache internally */ 135 u8 x86_cache_bits; 136 unsigned initialized : 1; 137 } __randomize_layout; 138 139 struct cpuid_regs { 140 u32 eax, ebx, ecx, edx; 141 }; 142 143 enum cpuid_regs_idx { 144 CPUID_EAX = 0, 145 CPUID_EBX, 146 CPUID_ECX, 147 CPUID_EDX, 148 }; 149 150 #define X86_VENDOR_INTEL 0 151 #define X86_VENDOR_CYRIX 1 152 #define X86_VENDOR_AMD 2 153 #define X86_VENDOR_UMC 3 154 #define X86_VENDOR_CENTAUR 5 155 #define X86_VENDOR_TRANSMETA 7 156 #define X86_VENDOR_NSC 8 157 #define X86_VENDOR_HYGON 9 158 #define X86_VENDOR_ZHAOXIN 10 159 #define X86_VENDOR_NUM 11 160 161 #define X86_VENDOR_UNKNOWN 0xff 162 163 /* 164 * capabilities of CPUs 165 */ 166 extern struct cpuinfo_x86 boot_cpu_data; 167 extern struct cpuinfo_x86 new_cpu_data; 168 169 extern struct x86_hw_tss doublefault_tss; 170 extern __u32 cpu_caps_cleared[NCAPINTS + NBUGINTS]; 171 extern __u32 cpu_caps_set[NCAPINTS + NBUGINTS]; 172 173 #ifdef CONFIG_SMP 174 DECLARE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info); 175 #define cpu_data(cpu) per_cpu(cpu_info, cpu) 176 #else 177 #define cpu_info boot_cpu_data 178 #define cpu_data(cpu) boot_cpu_data 179 #endif 180 181 extern const struct seq_operations cpuinfo_op; 182 183 #define cache_line_size() (boot_cpu_data.x86_cache_alignment) 184 185 extern void cpu_detect(struct cpuinfo_x86 *c); 186 187 static inline unsigned long long l1tf_pfn_limit(void) 188 { 189 return BIT_ULL(boot_cpu_data.x86_cache_bits - 1 - PAGE_SHIFT); 190 } 191 192 extern void early_cpu_init(void); 193 extern void identify_boot_cpu(void); 194 extern void identify_secondary_cpu(struct cpuinfo_x86 *); 195 extern void print_cpu_info(struct cpuinfo_x86 *); 196 void print_cpu_msr(struct cpuinfo_x86 *); 197 198 #ifdef CONFIG_X86_32 199 extern int have_cpuid_p(void); 200 #else 201 static inline int have_cpuid_p(void) 202 { 203 return 1; 204 } 205 #endif 206 static inline void native_cpuid(unsigned int *eax, unsigned int *ebx, 207 unsigned int *ecx, unsigned int *edx) 208 { 209 /* ecx is often an input as well as an output. */ 210 asm volatile("cpuid" 211 : "=a" (*eax), 212 "=b" (*ebx), 213 "=c" (*ecx), 214 "=d" (*edx) 215 : "0" (*eax), "2" (*ecx) 216 : "memory"); 217 } 218 219 #define native_cpuid_reg(reg) \ 220 static inline unsigned int native_cpuid_##reg(unsigned int op) \ 221 { \ 222 unsigned int eax = op, ebx, ecx = 0, edx; \ 223 \ 224 native_cpuid(&eax, &ebx, &ecx, &edx); \ 225 \ 226 return reg; \ 227 } 228 229 /* 230 * Native CPUID functions returning a single datum. 231 */ 232 native_cpuid_reg(eax) 233 native_cpuid_reg(ebx) 234 native_cpuid_reg(ecx) 235 native_cpuid_reg(edx) 236 237 /* 238 * Friendlier CR3 helpers. 239 */ 240 static inline unsigned long read_cr3_pa(void) 241 { 242 return __read_cr3() & CR3_ADDR_MASK; 243 } 244 245 static inline unsigned long native_read_cr3_pa(void) 246 { 247 return __native_read_cr3() & CR3_ADDR_MASK; 248 } 249 250 static inline void load_cr3(pgd_t *pgdir) 251 { 252 write_cr3(__sme_pa(pgdir)); 253 } 254 255 /* 256 * Note that while the legacy 'TSS' name comes from 'Task State Segment', 257 * on modern x86 CPUs the TSS also holds information important to 64-bit mode, 258 * unrelated to the task-switch mechanism: 259 */ 260 #ifdef CONFIG_X86_32 261 /* This is the TSS defined by the hardware. */ 262 struct x86_hw_tss { 263 unsigned short back_link, __blh; 264 unsigned long sp0; 265 unsigned short ss0, __ss0h; 266 unsigned long sp1; 267 268 /* 269 * We don't use ring 1, so ss1 is a convenient scratch space in 270 * the same cacheline as sp0. We use ss1 to cache the value in 271 * MSR_IA32_SYSENTER_CS. When we context switch 272 * MSR_IA32_SYSENTER_CS, we first check if the new value being 273 * written matches ss1, and, if it's not, then we wrmsr the new 274 * value and update ss1. 275 * 276 * The only reason we context switch MSR_IA32_SYSENTER_CS is 277 * that we set it to zero in vm86 tasks to avoid corrupting the 278 * stack if we were to go through the sysenter path from vm86 279 * mode. 280 */ 281 unsigned short ss1; /* MSR_IA32_SYSENTER_CS */ 282 283 unsigned short __ss1h; 284 unsigned long sp2; 285 unsigned short ss2, __ss2h; 286 unsigned long __cr3; 287 unsigned long ip; 288 unsigned long flags; 289 unsigned long ax; 290 unsigned long cx; 291 unsigned long dx; 292 unsigned long bx; 293 unsigned long sp; 294 unsigned long bp; 295 unsigned long si; 296 unsigned long di; 297 unsigned short es, __esh; 298 unsigned short cs, __csh; 299 unsigned short ss, __ssh; 300 unsigned short ds, __dsh; 301 unsigned short fs, __fsh; 302 unsigned short gs, __gsh; 303 unsigned short ldt, __ldth; 304 unsigned short trace; 305 unsigned short io_bitmap_base; 306 307 } __attribute__((packed)); 308 #else 309 struct x86_hw_tss { 310 u32 reserved1; 311 u64 sp0; 312 313 /* 314 * We store cpu_current_top_of_stack in sp1 so it's always accessible. 315 * Linux does not use ring 1, so sp1 is not otherwise needed. 316 */ 317 u64 sp1; 318 319 /* 320 * Since Linux does not use ring 2, the 'sp2' slot is unused by 321 * hardware. entry_SYSCALL_64 uses it as scratch space to stash 322 * the user RSP value. 323 */ 324 u64 sp2; 325 326 u64 reserved2; 327 u64 ist[7]; 328 u32 reserved3; 329 u32 reserved4; 330 u16 reserved5; 331 u16 io_bitmap_base; 332 333 } __attribute__((packed)); 334 #endif 335 336 /* 337 * IO-bitmap sizes: 338 */ 339 #define IO_BITMAP_BITS 65536 340 #define IO_BITMAP_BYTES (IO_BITMAP_BITS / BITS_PER_BYTE) 341 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES / sizeof(long)) 342 343 #define IO_BITMAP_OFFSET_VALID_MAP \ 344 (offsetof(struct tss_struct, io_bitmap.bitmap) - \ 345 offsetof(struct tss_struct, x86_tss)) 346 347 #define IO_BITMAP_OFFSET_VALID_ALL \ 348 (offsetof(struct tss_struct, io_bitmap.mapall) - \ 349 offsetof(struct tss_struct, x86_tss)) 350 351 #ifdef CONFIG_X86_IOPL_IOPERM 352 /* 353 * sizeof(unsigned long) coming from an extra "long" at the end of the 354 * iobitmap. The limit is inclusive, i.e. the last valid byte. 355 */ 356 # define __KERNEL_TSS_LIMIT \ 357 (IO_BITMAP_OFFSET_VALID_ALL + IO_BITMAP_BYTES + \ 358 sizeof(unsigned long) - 1) 359 #else 360 # define __KERNEL_TSS_LIMIT \ 361 (offsetof(struct tss_struct, x86_tss) + sizeof(struct x86_hw_tss) - 1) 362 #endif 363 364 /* Base offset outside of TSS_LIMIT so unpriviledged IO causes #GP */ 365 #define IO_BITMAP_OFFSET_INVALID (__KERNEL_TSS_LIMIT + 1) 366 367 struct entry_stack { 368 unsigned long words[64]; 369 }; 370 371 struct entry_stack_page { 372 struct entry_stack stack; 373 } __aligned(PAGE_SIZE); 374 375 /* 376 * All IO bitmap related data stored in the TSS: 377 */ 378 struct x86_io_bitmap { 379 /* The sequence number of the last active bitmap. */ 380 u64 prev_sequence; 381 382 /* 383 * Store the dirty size of the last io bitmap offender. The next 384 * one will have to do the cleanup as the switch out to a non io 385 * bitmap user will just set x86_tss.io_bitmap_base to a value 386 * outside of the TSS limit. So for sane tasks there is no need to 387 * actually touch the io_bitmap at all. 388 */ 389 unsigned int prev_max; 390 391 /* 392 * The extra 1 is there because the CPU will access an 393 * additional byte beyond the end of the IO permission 394 * bitmap. The extra byte must be all 1 bits, and must 395 * be within the limit. 396 */ 397 unsigned long bitmap[IO_BITMAP_LONGS + 1]; 398 399 /* 400 * Special I/O bitmap to emulate IOPL(3). All bytes zero, 401 * except the additional byte at the end. 402 */ 403 unsigned long mapall[IO_BITMAP_LONGS + 1]; 404 }; 405 406 struct tss_struct { 407 /* 408 * The fixed hardware portion. This must not cross a page boundary 409 * at risk of violating the SDM's advice and potentially triggering 410 * errata. 411 */ 412 struct x86_hw_tss x86_tss; 413 414 struct x86_io_bitmap io_bitmap; 415 } __aligned(PAGE_SIZE); 416 417 DECLARE_PER_CPU_PAGE_ALIGNED(struct tss_struct, cpu_tss_rw); 418 419 /* Per CPU interrupt stacks */ 420 struct irq_stack { 421 char stack[IRQ_STACK_SIZE]; 422 } __aligned(IRQ_STACK_SIZE); 423 424 DECLARE_PER_CPU(struct irq_stack *, hardirq_stack_ptr); 425 426 #ifdef CONFIG_X86_32 427 DECLARE_PER_CPU(unsigned long, cpu_current_top_of_stack); 428 #else 429 /* The RO copy can't be accessed with this_cpu_xyz(), so use the RW copy. */ 430 #define cpu_current_top_of_stack cpu_tss_rw.x86_tss.sp1 431 #endif 432 433 #ifdef CONFIG_X86_64 434 struct fixed_percpu_data { 435 /* 436 * GCC hardcodes the stack canary as %gs:40. Since the 437 * irq_stack is the object at %gs:0, we reserve the bottom 438 * 48 bytes of the irq stack for the canary. 439 */ 440 char gs_base[40]; 441 unsigned long stack_canary; 442 }; 443 444 DECLARE_PER_CPU_FIRST(struct fixed_percpu_data, fixed_percpu_data) __visible; 445 DECLARE_INIT_PER_CPU(fixed_percpu_data); 446 447 static inline unsigned long cpu_kernelmode_gs_base(int cpu) 448 { 449 return (unsigned long)per_cpu(fixed_percpu_data.gs_base, cpu); 450 } 451 452 DECLARE_PER_CPU(unsigned int, irq_count); 453 extern asmlinkage void ignore_sysret(void); 454 455 #if IS_ENABLED(CONFIG_KVM) 456 /* Save actual FS/GS selectors and bases to current->thread */ 457 void save_fsgs_for_kvm(void); 458 #endif 459 #else /* X86_64 */ 460 #ifdef CONFIG_STACKPROTECTOR 461 /* 462 * Make sure stack canary segment base is cached-aligned: 463 * "For Intel Atom processors, avoid non zero segment base address 464 * that is not aligned to cache line boundary at all cost." 465 * (Optim Ref Manual Assembly/Compiler Coding Rule 15.) 466 */ 467 struct stack_canary { 468 char __pad[20]; /* canary at %gs:20 */ 469 unsigned long canary; 470 }; 471 DECLARE_PER_CPU_ALIGNED(struct stack_canary, stack_canary); 472 #endif 473 /* Per CPU softirq stack pointer */ 474 DECLARE_PER_CPU(struct irq_stack *, softirq_stack_ptr); 475 #endif /* X86_64 */ 476 477 extern unsigned int fpu_kernel_xstate_size; 478 extern unsigned int fpu_user_xstate_size; 479 480 struct perf_event; 481 482 typedef struct { 483 unsigned long seg; 484 } mm_segment_t; 485 486 struct thread_struct { 487 /* Cached TLS descriptors: */ 488 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES]; 489 #ifdef CONFIG_X86_32 490 unsigned long sp0; 491 #endif 492 unsigned long sp; 493 #ifdef CONFIG_X86_32 494 unsigned long sysenter_cs; 495 #else 496 unsigned short es; 497 unsigned short ds; 498 unsigned short fsindex; 499 unsigned short gsindex; 500 #endif 501 502 #ifdef CONFIG_X86_64 503 unsigned long fsbase; 504 unsigned long gsbase; 505 #else 506 /* 507 * XXX: this could presumably be unsigned short. Alternatively, 508 * 32-bit kernels could be taught to use fsindex instead. 509 */ 510 unsigned long fs; 511 unsigned long gs; 512 #endif 513 514 /* Save middle states of ptrace breakpoints */ 515 struct perf_event *ptrace_bps[HBP_NUM]; 516 /* Debug status used for traps, single steps, etc... */ 517 unsigned long debugreg6; 518 /* Keep track of the exact dr7 value set by the user */ 519 unsigned long ptrace_dr7; 520 /* Fault info: */ 521 unsigned long cr2; 522 unsigned long trap_nr; 523 unsigned long error_code; 524 #ifdef CONFIG_VM86 525 /* Virtual 86 mode info */ 526 struct vm86 *vm86; 527 #endif 528 /* IO permissions: */ 529 struct io_bitmap *io_bitmap; 530 531 /* 532 * IOPL. Priviledge level dependent I/O permission which is 533 * emulated via the I/O bitmap to prevent user space from disabling 534 * interrupts. 535 */ 536 unsigned long iopl_emul; 537 538 mm_segment_t addr_limit; 539 540 unsigned int sig_on_uaccess_err:1; 541 unsigned int uaccess_err:1; /* uaccess failed */ 542 543 /* Floating point and extended processor state */ 544 struct fpu fpu; 545 /* 546 * WARNING: 'fpu' is dynamically-sized. It *MUST* be at 547 * the end. 548 */ 549 }; 550 551 /* Whitelist the FPU state from the task_struct for hardened usercopy. */ 552 static inline void arch_thread_struct_whitelist(unsigned long *offset, 553 unsigned long *size) 554 { 555 *offset = offsetof(struct thread_struct, fpu.state); 556 *size = fpu_kernel_xstate_size; 557 } 558 559 /* 560 * Thread-synchronous status. 561 * 562 * This is different from the flags in that nobody else 563 * ever touches our thread-synchronous status, so we don't 564 * have to worry about atomic accesses. 565 */ 566 #define TS_COMPAT 0x0002 /* 32bit syscall active (64BIT)*/ 567 568 static inline void 569 native_load_sp0(unsigned long sp0) 570 { 571 this_cpu_write(cpu_tss_rw.x86_tss.sp0, sp0); 572 } 573 574 static inline void native_swapgs(void) 575 { 576 #ifdef CONFIG_X86_64 577 asm volatile("swapgs" ::: "memory"); 578 #endif 579 } 580 581 static inline unsigned long current_top_of_stack(void) 582 { 583 /* 584 * We can't read directly from tss.sp0: sp0 on x86_32 is special in 585 * and around vm86 mode and sp0 on x86_64 is special because of the 586 * entry trampoline. 587 */ 588 return this_cpu_read_stable(cpu_current_top_of_stack); 589 } 590 591 static inline bool on_thread_stack(void) 592 { 593 return (unsigned long)(current_top_of_stack() - 594 current_stack_pointer) < THREAD_SIZE; 595 } 596 597 #ifdef CONFIG_PARAVIRT_XXL 598 #include <asm/paravirt.h> 599 #else 600 #define __cpuid native_cpuid 601 602 static inline void load_sp0(unsigned long sp0) 603 { 604 native_load_sp0(sp0); 605 } 606 607 #endif /* CONFIG_PARAVIRT_XXL */ 608 609 /* Free all resources held by a thread. */ 610 extern void release_thread(struct task_struct *); 611 612 unsigned long get_wchan(struct task_struct *p); 613 614 /* 615 * Generic CPUID function 616 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx 617 * resulting in stale register contents being returned. 618 */ 619 static inline void cpuid(unsigned int op, 620 unsigned int *eax, unsigned int *ebx, 621 unsigned int *ecx, unsigned int *edx) 622 { 623 *eax = op; 624 *ecx = 0; 625 __cpuid(eax, ebx, ecx, edx); 626 } 627 628 /* Some CPUID calls want 'count' to be placed in ecx */ 629 static inline void cpuid_count(unsigned int op, int count, 630 unsigned int *eax, unsigned int *ebx, 631 unsigned int *ecx, unsigned int *edx) 632 { 633 *eax = op; 634 *ecx = count; 635 __cpuid(eax, ebx, ecx, edx); 636 } 637 638 /* 639 * CPUID functions returning a single datum 640 */ 641 static inline unsigned int cpuid_eax(unsigned int op) 642 { 643 unsigned int eax, ebx, ecx, edx; 644 645 cpuid(op, &eax, &ebx, &ecx, &edx); 646 647 return eax; 648 } 649 650 static inline unsigned int cpuid_ebx(unsigned int op) 651 { 652 unsigned int eax, ebx, ecx, edx; 653 654 cpuid(op, &eax, &ebx, &ecx, &edx); 655 656 return ebx; 657 } 658 659 static inline unsigned int cpuid_ecx(unsigned int op) 660 { 661 unsigned int eax, ebx, ecx, edx; 662 663 cpuid(op, &eax, &ebx, &ecx, &edx); 664 665 return ecx; 666 } 667 668 static inline unsigned int cpuid_edx(unsigned int op) 669 { 670 unsigned int eax, ebx, ecx, edx; 671 672 cpuid(op, &eax, &ebx, &ecx, &edx); 673 674 return edx; 675 } 676 677 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */ 678 static __always_inline void rep_nop(void) 679 { 680 asm volatile("rep; nop" ::: "memory"); 681 } 682 683 static __always_inline void cpu_relax(void) 684 { 685 rep_nop(); 686 } 687 688 /* 689 * This function forces the icache and prefetched instruction stream to 690 * catch up with reality in two very specific cases: 691 * 692 * a) Text was modified using one virtual address and is about to be executed 693 * from the same physical page at a different virtual address. 694 * 695 * b) Text was modified on a different CPU, may subsequently be 696 * executed on this CPU, and you want to make sure the new version 697 * gets executed. This generally means you're calling this in a IPI. 698 * 699 * If you're calling this for a different reason, you're probably doing 700 * it wrong. 701 */ 702 static inline void sync_core(void) 703 { 704 /* 705 * There are quite a few ways to do this. IRET-to-self is nice 706 * because it works on every CPU, at any CPL (so it's compatible 707 * with paravirtualization), and it never exits to a hypervisor. 708 * The only down sides are that it's a bit slow (it seems to be 709 * a bit more than 2x slower than the fastest options) and that 710 * it unmasks NMIs. The "push %cs" is needed because, in 711 * paravirtual environments, __KERNEL_CS may not be a valid CS 712 * value when we do IRET directly. 713 * 714 * In case NMI unmasking or performance ever becomes a problem, 715 * the next best option appears to be MOV-to-CR2 and an 716 * unconditional jump. That sequence also works on all CPUs, 717 * but it will fault at CPL3 (i.e. Xen PV). 718 * 719 * CPUID is the conventional way, but it's nasty: it doesn't 720 * exist on some 486-like CPUs, and it usually exits to a 721 * hypervisor. 722 * 723 * Like all of Linux's memory ordering operations, this is a 724 * compiler barrier as well. 725 */ 726 #ifdef CONFIG_X86_32 727 asm volatile ( 728 "pushfl\n\t" 729 "pushl %%cs\n\t" 730 "pushl $1f\n\t" 731 "iret\n\t" 732 "1:" 733 : ASM_CALL_CONSTRAINT : : "memory"); 734 #else 735 unsigned int tmp; 736 737 asm volatile ( 738 UNWIND_HINT_SAVE 739 "mov %%ss, %0\n\t" 740 "pushq %q0\n\t" 741 "pushq %%rsp\n\t" 742 "addq $8, (%%rsp)\n\t" 743 "pushfq\n\t" 744 "mov %%cs, %0\n\t" 745 "pushq %q0\n\t" 746 "pushq $1f\n\t" 747 "iretq\n\t" 748 UNWIND_HINT_RESTORE 749 "1:" 750 : "=&r" (tmp), ASM_CALL_CONSTRAINT : : "cc", "memory"); 751 #endif 752 } 753 754 extern void select_idle_routine(const struct cpuinfo_x86 *c); 755 extern void amd_e400_c1e_apic_setup(void); 756 757 extern unsigned long boot_option_idle_override; 758 759 enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_NOMWAIT, 760 IDLE_POLL}; 761 762 extern void enable_sep_cpu(void); 763 extern int sysenter_setup(void); 764 765 766 /* Defined in head.S */ 767 extern struct desc_ptr early_gdt_descr; 768 769 extern void switch_to_new_gdt(int); 770 extern void load_direct_gdt(int); 771 extern void load_fixmap_gdt(int); 772 extern void load_percpu_segment(int); 773 extern void cpu_init(void); 774 extern void cr4_init(void); 775 776 static inline unsigned long get_debugctlmsr(void) 777 { 778 unsigned long debugctlmsr = 0; 779 780 #ifndef CONFIG_X86_DEBUGCTLMSR 781 if (boot_cpu_data.x86 < 6) 782 return 0; 783 #endif 784 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr); 785 786 return debugctlmsr; 787 } 788 789 static inline void update_debugctlmsr(unsigned long debugctlmsr) 790 { 791 #ifndef CONFIG_X86_DEBUGCTLMSR 792 if (boot_cpu_data.x86 < 6) 793 return; 794 #endif 795 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr); 796 } 797 798 extern void set_task_blockstep(struct task_struct *task, bool on); 799 800 /* Boot loader type from the setup header: */ 801 extern int bootloader_type; 802 extern int bootloader_version; 803 804 extern char ignore_fpu_irq; 805 806 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1 807 #define ARCH_HAS_PREFETCHW 808 #define ARCH_HAS_SPINLOCK_PREFETCH 809 810 #ifdef CONFIG_X86_32 811 # define BASE_PREFETCH "" 812 # define ARCH_HAS_PREFETCH 813 #else 814 # define BASE_PREFETCH "prefetcht0 %P1" 815 #endif 816 817 /* 818 * Prefetch instructions for Pentium III (+) and AMD Athlon (+) 819 * 820 * It's not worth to care about 3dnow prefetches for the K6 821 * because they are microcoded there and very slow. 822 */ 823 static inline void prefetch(const void *x) 824 { 825 alternative_input(BASE_PREFETCH, "prefetchnta %P1", 826 X86_FEATURE_XMM, 827 "m" (*(const char *)x)); 828 } 829 830 /* 831 * 3dnow prefetch to get an exclusive cache line. 832 * Useful for spinlocks to avoid one state transition in the 833 * cache coherency protocol: 834 */ 835 static inline void prefetchw(const void *x) 836 { 837 alternative_input(BASE_PREFETCH, "prefetchw %P1", 838 X86_FEATURE_3DNOWPREFETCH, 839 "m" (*(const char *)x)); 840 } 841 842 static inline void spin_lock_prefetch(const void *x) 843 { 844 prefetchw(x); 845 } 846 847 #define TOP_OF_INIT_STACK ((unsigned long)&init_stack + sizeof(init_stack) - \ 848 TOP_OF_KERNEL_STACK_PADDING) 849 850 #define task_top_of_stack(task) ((unsigned long)(task_pt_regs(task) + 1)) 851 852 #define task_pt_regs(task) \ 853 ({ \ 854 unsigned long __ptr = (unsigned long)task_stack_page(task); \ 855 __ptr += THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING; \ 856 ((struct pt_regs *)__ptr) - 1; \ 857 }) 858 859 #ifdef CONFIG_X86_32 860 /* 861 * User space process size: 3GB (default). 862 */ 863 #define IA32_PAGE_OFFSET PAGE_OFFSET 864 #define TASK_SIZE PAGE_OFFSET 865 #define TASK_SIZE_LOW TASK_SIZE 866 #define TASK_SIZE_MAX TASK_SIZE 867 #define DEFAULT_MAP_WINDOW TASK_SIZE 868 #define STACK_TOP TASK_SIZE 869 #define STACK_TOP_MAX STACK_TOP 870 871 #define INIT_THREAD { \ 872 .sp0 = TOP_OF_INIT_STACK, \ 873 .sysenter_cs = __KERNEL_CS, \ 874 .addr_limit = KERNEL_DS, \ 875 } 876 877 #define KSTK_ESP(task) (task_pt_regs(task)->sp) 878 879 #else 880 /* 881 * User space process size. This is the first address outside the user range. 882 * There are a few constraints that determine this: 883 * 884 * On Intel CPUs, if a SYSCALL instruction is at the highest canonical 885 * address, then that syscall will enter the kernel with a 886 * non-canonical return address, and SYSRET will explode dangerously. 887 * We avoid this particular problem by preventing anything executable 888 * from being mapped at the maximum canonical address. 889 * 890 * On AMD CPUs in the Ryzen family, there's a nasty bug in which the 891 * CPUs malfunction if they execute code from the highest canonical page. 892 * They'll speculate right off the end of the canonical space, and 893 * bad things happen. This is worked around in the same way as the 894 * Intel problem. 895 * 896 * With page table isolation enabled, we map the LDT in ... [stay tuned] 897 */ 898 #define TASK_SIZE_MAX ((1UL << __VIRTUAL_MASK_SHIFT) - PAGE_SIZE) 899 900 #define DEFAULT_MAP_WINDOW ((1UL << 47) - PAGE_SIZE) 901 902 /* This decides where the kernel will search for a free chunk of vm 903 * space during mmap's. 904 */ 905 #define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? \ 906 0xc0000000 : 0xFFFFe000) 907 908 #define TASK_SIZE_LOW (test_thread_flag(TIF_ADDR32) ? \ 909 IA32_PAGE_OFFSET : DEFAULT_MAP_WINDOW) 910 #define TASK_SIZE (test_thread_flag(TIF_ADDR32) ? \ 911 IA32_PAGE_OFFSET : TASK_SIZE_MAX) 912 #define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_ADDR32)) ? \ 913 IA32_PAGE_OFFSET : TASK_SIZE_MAX) 914 915 #define STACK_TOP TASK_SIZE_LOW 916 #define STACK_TOP_MAX TASK_SIZE_MAX 917 918 #define INIT_THREAD { \ 919 .addr_limit = KERNEL_DS, \ 920 } 921 922 extern unsigned long KSTK_ESP(struct task_struct *task); 923 924 #endif /* CONFIG_X86_64 */ 925 926 extern void start_thread(struct pt_regs *regs, unsigned long new_ip, 927 unsigned long new_sp); 928 929 /* 930 * This decides where the kernel will search for a free chunk of vm 931 * space during mmap's. 932 */ 933 #define __TASK_UNMAPPED_BASE(task_size) (PAGE_ALIGN(task_size / 3)) 934 #define TASK_UNMAPPED_BASE __TASK_UNMAPPED_BASE(TASK_SIZE_LOW) 935 936 #define KSTK_EIP(task) (task_pt_regs(task)->ip) 937 938 /* Get/set a process' ability to use the timestamp counter instruction */ 939 #define GET_TSC_CTL(adr) get_tsc_mode((adr)) 940 #define SET_TSC_CTL(val) set_tsc_mode((val)) 941 942 extern int get_tsc_mode(unsigned long adr); 943 extern int set_tsc_mode(unsigned int val); 944 945 DECLARE_PER_CPU(u64, msr_misc_features_shadow); 946 947 /* Register/unregister a process' MPX related resource */ 948 #define MPX_ENABLE_MANAGEMENT() mpx_enable_management() 949 #define MPX_DISABLE_MANAGEMENT() mpx_disable_management() 950 951 #ifdef CONFIG_X86_INTEL_MPX 952 extern int mpx_enable_management(void); 953 extern int mpx_disable_management(void); 954 #else 955 static inline int mpx_enable_management(void) 956 { 957 return -EINVAL; 958 } 959 static inline int mpx_disable_management(void) 960 { 961 return -EINVAL; 962 } 963 #endif /* CONFIG_X86_INTEL_MPX */ 964 965 #ifdef CONFIG_CPU_SUP_AMD 966 extern u16 amd_get_nb_id(int cpu); 967 extern u32 amd_get_nodes_per_socket(void); 968 #else 969 static inline u16 amd_get_nb_id(int cpu) { return 0; } 970 static inline u32 amd_get_nodes_per_socket(void) { return 0; } 971 #endif 972 973 static inline uint32_t hypervisor_cpuid_base(const char *sig, uint32_t leaves) 974 { 975 uint32_t base, eax, signature[3]; 976 977 for (base = 0x40000000; base < 0x40010000; base += 0x100) { 978 cpuid(base, &eax, &signature[0], &signature[1], &signature[2]); 979 980 if (!memcmp(sig, signature, 12) && 981 (leaves == 0 || ((eax - base) >= leaves))) 982 return base; 983 } 984 985 return 0; 986 } 987 988 extern unsigned long arch_align_stack(unsigned long sp); 989 void free_init_pages(const char *what, unsigned long begin, unsigned long end); 990 extern void free_kernel_image_pages(const char *what, void *begin, void *end); 991 992 void default_idle(void); 993 #ifdef CONFIG_XEN 994 bool xen_set_default_idle(void); 995 #else 996 #define xen_set_default_idle 0 997 #endif 998 999 void stop_this_cpu(void *dummy); 1000 void df_debug(struct pt_regs *regs, long error_code); 1001 void microcode_check(void); 1002 1003 enum l1tf_mitigations { 1004 L1TF_MITIGATION_OFF, 1005 L1TF_MITIGATION_FLUSH_NOWARN, 1006 L1TF_MITIGATION_FLUSH, 1007 L1TF_MITIGATION_FLUSH_NOSMT, 1008 L1TF_MITIGATION_FULL, 1009 L1TF_MITIGATION_FULL_FORCE 1010 }; 1011 1012 extern enum l1tf_mitigations l1tf_mitigation; 1013 1014 enum mds_mitigations { 1015 MDS_MITIGATION_OFF, 1016 MDS_MITIGATION_FULL, 1017 MDS_MITIGATION_VMWERV, 1018 }; 1019 1020 enum taa_mitigations { 1021 TAA_MITIGATION_OFF, 1022 TAA_MITIGATION_UCODE_NEEDED, 1023 TAA_MITIGATION_VERW, 1024 TAA_MITIGATION_TSX_DISABLED, 1025 }; 1026 1027 #endif /* _ASM_X86_PROCESSOR_H */ 1028