1 #ifndef _ASM_X86_PROCESSOR_H 2 #define _ASM_X86_PROCESSOR_H 3 4 #include <asm/processor-flags.h> 5 6 /* Forward declaration, a strange C thing */ 7 struct task_struct; 8 struct mm_struct; 9 struct vm86; 10 11 #include <asm/math_emu.h> 12 #include <asm/segment.h> 13 #include <asm/types.h> 14 #include <uapi/asm/sigcontext.h> 15 #include <asm/current.h> 16 #include <asm/cpufeatures.h> 17 #include <asm/page.h> 18 #include <asm/pgtable_types.h> 19 #include <asm/percpu.h> 20 #include <asm/msr.h> 21 #include <asm/desc_defs.h> 22 #include <asm/nops.h> 23 #include <asm/special_insns.h> 24 #include <asm/fpu/types.h> 25 26 #include <linux/personality.h> 27 #include <linux/cache.h> 28 #include <linux/threads.h> 29 #include <linux/math64.h> 30 #include <linux/err.h> 31 #include <linux/irqflags.h> 32 33 /* 34 * We handle most unaligned accesses in hardware. On the other hand 35 * unaligned DMA can be quite expensive on some Nehalem processors. 36 * 37 * Based on this we disable the IP header alignment in network drivers. 38 */ 39 #define NET_IP_ALIGN 0 40 41 #define HBP_NUM 4 42 /* 43 * Default implementation of macro that returns current 44 * instruction pointer ("program counter"). 45 */ 46 static inline void *current_text_addr(void) 47 { 48 void *pc; 49 50 asm volatile("mov $1f, %0; 1:":"=r" (pc)); 51 52 return pc; 53 } 54 55 /* 56 * These alignment constraints are for performance in the vSMP case, 57 * but in the task_struct case we must also meet hardware imposed 58 * alignment requirements of the FPU state: 59 */ 60 #ifdef CONFIG_X86_VSMP 61 # define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT) 62 # define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT) 63 #else 64 # define ARCH_MIN_TASKALIGN __alignof__(union fpregs_state) 65 # define ARCH_MIN_MMSTRUCT_ALIGN 0 66 #endif 67 68 enum tlb_infos { 69 ENTRIES, 70 NR_INFO 71 }; 72 73 extern u16 __read_mostly tlb_lli_4k[NR_INFO]; 74 extern u16 __read_mostly tlb_lli_2m[NR_INFO]; 75 extern u16 __read_mostly tlb_lli_4m[NR_INFO]; 76 extern u16 __read_mostly tlb_lld_4k[NR_INFO]; 77 extern u16 __read_mostly tlb_lld_2m[NR_INFO]; 78 extern u16 __read_mostly tlb_lld_4m[NR_INFO]; 79 extern u16 __read_mostly tlb_lld_1g[NR_INFO]; 80 81 /* 82 * CPU type and hardware bug flags. Kept separately for each CPU. 83 * Members of this structure are referenced in head.S, so think twice 84 * before touching them. [mj] 85 */ 86 87 struct cpuinfo_x86 { 88 __u8 x86; /* CPU family */ 89 __u8 x86_vendor; /* CPU vendor */ 90 __u8 x86_model; 91 __u8 x86_mask; 92 #ifdef CONFIG_X86_32 93 char wp_works_ok; /* It doesn't on 386's */ 94 95 /* Problems on some 486Dx4's and old 386's: */ 96 char rfu; 97 char pad0; 98 char pad1; 99 #else 100 /* Number of 4K pages in DTLB/ITLB combined(in pages): */ 101 int x86_tlbsize; 102 #endif 103 __u8 x86_virt_bits; 104 __u8 x86_phys_bits; 105 /* CPUID returned core id bits: */ 106 __u8 x86_coreid_bits; 107 /* Max extended CPUID function supported: */ 108 __u32 extended_cpuid_level; 109 /* Maximum supported CPUID level, -1=no CPUID: */ 110 int cpuid_level; 111 __u32 x86_capability[NCAPINTS + NBUGINTS]; 112 char x86_vendor_id[16]; 113 char x86_model_id[64]; 114 /* in KB - valid for CPUS which support this call: */ 115 int x86_cache_size; 116 int x86_cache_alignment; /* In bytes */ 117 /* Cache QoS architectural values: */ 118 int x86_cache_max_rmid; /* max index */ 119 int x86_cache_occ_scale; /* scale to bytes */ 120 int x86_power; 121 unsigned long loops_per_jiffy; 122 /* cpuid returned max cores value: */ 123 u16 x86_max_cores; 124 u16 apicid; 125 u16 initial_apicid; 126 u16 x86_clflush_size; 127 /* number of cores as seen by the OS: */ 128 u16 booted_cores; 129 /* Physical processor id: */ 130 u16 phys_proc_id; 131 /* Core id: */ 132 u16 cpu_core_id; 133 /* Compute unit id */ 134 u8 compute_unit_id; 135 /* Index into per_cpu list: */ 136 u16 cpu_index; 137 u32 microcode; 138 }; 139 140 #define X86_VENDOR_INTEL 0 141 #define X86_VENDOR_CYRIX 1 142 #define X86_VENDOR_AMD 2 143 #define X86_VENDOR_UMC 3 144 #define X86_VENDOR_CENTAUR 5 145 #define X86_VENDOR_TRANSMETA 7 146 #define X86_VENDOR_NSC 8 147 #define X86_VENDOR_NUM 9 148 149 #define X86_VENDOR_UNKNOWN 0xff 150 151 /* 152 * capabilities of CPUs 153 */ 154 extern struct cpuinfo_x86 boot_cpu_data; 155 extern struct cpuinfo_x86 new_cpu_data; 156 157 extern struct tss_struct doublefault_tss; 158 extern __u32 cpu_caps_cleared[NCAPINTS]; 159 extern __u32 cpu_caps_set[NCAPINTS]; 160 161 #ifdef CONFIG_SMP 162 DECLARE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info); 163 #define cpu_data(cpu) per_cpu(cpu_info, cpu) 164 #else 165 #define cpu_info boot_cpu_data 166 #define cpu_data(cpu) boot_cpu_data 167 #endif 168 169 extern const struct seq_operations cpuinfo_op; 170 171 #define cache_line_size() (boot_cpu_data.x86_cache_alignment) 172 173 extern void cpu_detect(struct cpuinfo_x86 *c); 174 175 extern void early_cpu_init(void); 176 extern void identify_boot_cpu(void); 177 extern void identify_secondary_cpu(struct cpuinfo_x86 *); 178 extern void print_cpu_info(struct cpuinfo_x86 *); 179 void print_cpu_msr(struct cpuinfo_x86 *); 180 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c); 181 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c); 182 extern void init_amd_cacheinfo(struct cpuinfo_x86 *c); 183 184 extern void detect_extended_topology(struct cpuinfo_x86 *c); 185 extern void detect_ht(struct cpuinfo_x86 *c); 186 187 #ifdef CONFIG_X86_32 188 extern int have_cpuid_p(void); 189 #else 190 static inline int have_cpuid_p(void) 191 { 192 return 1; 193 } 194 #endif 195 static inline void native_cpuid(unsigned int *eax, unsigned int *ebx, 196 unsigned int *ecx, unsigned int *edx) 197 { 198 /* ecx is often an input as well as an output. */ 199 asm volatile("cpuid" 200 : "=a" (*eax), 201 "=b" (*ebx), 202 "=c" (*ecx), 203 "=d" (*edx) 204 : "0" (*eax), "2" (*ecx) 205 : "memory"); 206 } 207 208 static inline void load_cr3(pgd_t *pgdir) 209 { 210 write_cr3(__pa(pgdir)); 211 } 212 213 #ifdef CONFIG_X86_32 214 /* This is the TSS defined by the hardware. */ 215 struct x86_hw_tss { 216 unsigned short back_link, __blh; 217 unsigned long sp0; 218 unsigned short ss0, __ss0h; 219 unsigned long sp1; 220 221 /* 222 * We don't use ring 1, so ss1 is a convenient scratch space in 223 * the same cacheline as sp0. We use ss1 to cache the value in 224 * MSR_IA32_SYSENTER_CS. When we context switch 225 * MSR_IA32_SYSENTER_CS, we first check if the new value being 226 * written matches ss1, and, if it's not, then we wrmsr the new 227 * value and update ss1. 228 * 229 * The only reason we context switch MSR_IA32_SYSENTER_CS is 230 * that we set it to zero in vm86 tasks to avoid corrupting the 231 * stack if we were to go through the sysenter path from vm86 232 * mode. 233 */ 234 unsigned short ss1; /* MSR_IA32_SYSENTER_CS */ 235 236 unsigned short __ss1h; 237 unsigned long sp2; 238 unsigned short ss2, __ss2h; 239 unsigned long __cr3; 240 unsigned long ip; 241 unsigned long flags; 242 unsigned long ax; 243 unsigned long cx; 244 unsigned long dx; 245 unsigned long bx; 246 unsigned long sp; 247 unsigned long bp; 248 unsigned long si; 249 unsigned long di; 250 unsigned short es, __esh; 251 unsigned short cs, __csh; 252 unsigned short ss, __ssh; 253 unsigned short ds, __dsh; 254 unsigned short fs, __fsh; 255 unsigned short gs, __gsh; 256 unsigned short ldt, __ldth; 257 unsigned short trace; 258 unsigned short io_bitmap_base; 259 260 } __attribute__((packed)); 261 #else 262 struct x86_hw_tss { 263 u32 reserved1; 264 u64 sp0; 265 u64 sp1; 266 u64 sp2; 267 u64 reserved2; 268 u64 ist[7]; 269 u32 reserved3; 270 u32 reserved4; 271 u16 reserved5; 272 u16 io_bitmap_base; 273 274 } __attribute__((packed)) ____cacheline_aligned; 275 #endif 276 277 /* 278 * IO-bitmap sizes: 279 */ 280 #define IO_BITMAP_BITS 65536 281 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8) 282 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long)) 283 #define IO_BITMAP_OFFSET offsetof(struct tss_struct, io_bitmap) 284 #define INVALID_IO_BITMAP_OFFSET 0x8000 285 286 struct tss_struct { 287 /* 288 * The hardware state: 289 */ 290 struct x86_hw_tss x86_tss; 291 292 /* 293 * The extra 1 is there because the CPU will access an 294 * additional byte beyond the end of the IO permission 295 * bitmap. The extra byte must be all 1 bits, and must 296 * be within the limit. 297 */ 298 unsigned long io_bitmap[IO_BITMAP_LONGS + 1]; 299 300 /* 301 * Space for the temporary SYSENTER stack: 302 */ 303 unsigned long SYSENTER_stack[64]; 304 305 } ____cacheline_aligned; 306 307 DECLARE_PER_CPU_SHARED_ALIGNED(struct tss_struct, cpu_tss); 308 309 #ifdef CONFIG_X86_32 310 DECLARE_PER_CPU(unsigned long, cpu_current_top_of_stack); 311 #endif 312 313 /* 314 * Save the original ist values for checking stack pointers during debugging 315 */ 316 struct orig_ist { 317 unsigned long ist[7]; 318 }; 319 320 #ifdef CONFIG_X86_64 321 DECLARE_PER_CPU(struct orig_ist, orig_ist); 322 323 union irq_stack_union { 324 char irq_stack[IRQ_STACK_SIZE]; 325 /* 326 * GCC hardcodes the stack canary as %gs:40. Since the 327 * irq_stack is the object at %gs:0, we reserve the bottom 328 * 48 bytes of the irq stack for the canary. 329 */ 330 struct { 331 char gs_base[40]; 332 unsigned long stack_canary; 333 }; 334 }; 335 336 DECLARE_PER_CPU_FIRST(union irq_stack_union, irq_stack_union) __visible; 337 DECLARE_INIT_PER_CPU(irq_stack_union); 338 339 DECLARE_PER_CPU(char *, irq_stack_ptr); 340 DECLARE_PER_CPU(unsigned int, irq_count); 341 extern asmlinkage void ignore_sysret(void); 342 #else /* X86_64 */ 343 #ifdef CONFIG_CC_STACKPROTECTOR 344 /* 345 * Make sure stack canary segment base is cached-aligned: 346 * "For Intel Atom processors, avoid non zero segment base address 347 * that is not aligned to cache line boundary at all cost." 348 * (Optim Ref Manual Assembly/Compiler Coding Rule 15.) 349 */ 350 struct stack_canary { 351 char __pad[20]; /* canary at %gs:20 */ 352 unsigned long canary; 353 }; 354 DECLARE_PER_CPU_ALIGNED(struct stack_canary, stack_canary); 355 #endif 356 /* 357 * per-CPU IRQ handling stacks 358 */ 359 struct irq_stack { 360 u32 stack[THREAD_SIZE/sizeof(u32)]; 361 } __aligned(THREAD_SIZE); 362 363 DECLARE_PER_CPU(struct irq_stack *, hardirq_stack); 364 DECLARE_PER_CPU(struct irq_stack *, softirq_stack); 365 #endif /* X86_64 */ 366 367 extern unsigned int xstate_size; 368 369 struct perf_event; 370 371 struct thread_struct { 372 /* Cached TLS descriptors: */ 373 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES]; 374 unsigned long sp0; 375 unsigned long sp; 376 #ifdef CONFIG_X86_32 377 unsigned long sysenter_cs; 378 #else 379 unsigned short es; 380 unsigned short ds; 381 unsigned short fsindex; 382 unsigned short gsindex; 383 #endif 384 #ifdef CONFIG_X86_32 385 unsigned long ip; 386 #endif 387 #ifdef CONFIG_X86_64 388 unsigned long fs; 389 #endif 390 unsigned long gs; 391 392 /* Save middle states of ptrace breakpoints */ 393 struct perf_event *ptrace_bps[HBP_NUM]; 394 /* Debug status used for traps, single steps, etc... */ 395 unsigned long debugreg6; 396 /* Keep track of the exact dr7 value set by the user */ 397 unsigned long ptrace_dr7; 398 /* Fault info: */ 399 unsigned long cr2; 400 unsigned long trap_nr; 401 unsigned long error_code; 402 #ifdef CONFIG_VM86 403 /* Virtual 86 mode info */ 404 struct vm86 *vm86; 405 #endif 406 /* IO permissions: */ 407 unsigned long *io_bitmap_ptr; 408 unsigned long iopl; 409 /* Max allowed port in the bitmap, in bytes: */ 410 unsigned io_bitmap_max; 411 412 /* Floating point and extended processor state */ 413 struct fpu fpu; 414 /* 415 * WARNING: 'fpu' is dynamically-sized. It *MUST* be at 416 * the end. 417 */ 418 }; 419 420 /* 421 * Set IOPL bits in EFLAGS from given mask 422 */ 423 static inline void native_set_iopl_mask(unsigned mask) 424 { 425 #ifdef CONFIG_X86_32 426 unsigned int reg; 427 428 asm volatile ("pushfl;" 429 "popl %0;" 430 "andl %1, %0;" 431 "orl %2, %0;" 432 "pushl %0;" 433 "popfl" 434 : "=&r" (reg) 435 : "i" (~X86_EFLAGS_IOPL), "r" (mask)); 436 #endif 437 } 438 439 static inline void 440 native_load_sp0(struct tss_struct *tss, struct thread_struct *thread) 441 { 442 tss->x86_tss.sp0 = thread->sp0; 443 #ifdef CONFIG_X86_32 444 /* Only happens when SEP is enabled, no need to test "SEP"arately: */ 445 if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) { 446 tss->x86_tss.ss1 = thread->sysenter_cs; 447 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0); 448 } 449 #endif 450 } 451 452 static inline void native_swapgs(void) 453 { 454 #ifdef CONFIG_X86_64 455 asm volatile("swapgs" ::: "memory"); 456 #endif 457 } 458 459 static inline unsigned long current_top_of_stack(void) 460 { 461 #ifdef CONFIG_X86_64 462 return this_cpu_read_stable(cpu_tss.x86_tss.sp0); 463 #else 464 /* sp0 on x86_32 is special in and around vm86 mode. */ 465 return this_cpu_read_stable(cpu_current_top_of_stack); 466 #endif 467 } 468 469 #ifdef CONFIG_PARAVIRT 470 #include <asm/paravirt.h> 471 #else 472 #define __cpuid native_cpuid 473 #define paravirt_enabled() 0 474 #define paravirt_has(x) 0 475 476 static inline void load_sp0(struct tss_struct *tss, 477 struct thread_struct *thread) 478 { 479 native_load_sp0(tss, thread); 480 } 481 482 #define set_iopl_mask native_set_iopl_mask 483 #endif /* CONFIG_PARAVIRT */ 484 485 typedef struct { 486 unsigned long seg; 487 } mm_segment_t; 488 489 490 /* Free all resources held by a thread. */ 491 extern void release_thread(struct task_struct *); 492 493 unsigned long get_wchan(struct task_struct *p); 494 495 /* 496 * Generic CPUID function 497 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx 498 * resulting in stale register contents being returned. 499 */ 500 static inline void cpuid(unsigned int op, 501 unsigned int *eax, unsigned int *ebx, 502 unsigned int *ecx, unsigned int *edx) 503 { 504 *eax = op; 505 *ecx = 0; 506 __cpuid(eax, ebx, ecx, edx); 507 } 508 509 /* Some CPUID calls want 'count' to be placed in ecx */ 510 static inline void cpuid_count(unsigned int op, int count, 511 unsigned int *eax, unsigned int *ebx, 512 unsigned int *ecx, unsigned int *edx) 513 { 514 *eax = op; 515 *ecx = count; 516 __cpuid(eax, ebx, ecx, edx); 517 } 518 519 /* 520 * CPUID functions returning a single datum 521 */ 522 static inline unsigned int cpuid_eax(unsigned int op) 523 { 524 unsigned int eax, ebx, ecx, edx; 525 526 cpuid(op, &eax, &ebx, &ecx, &edx); 527 528 return eax; 529 } 530 531 static inline unsigned int cpuid_ebx(unsigned int op) 532 { 533 unsigned int eax, ebx, ecx, edx; 534 535 cpuid(op, &eax, &ebx, &ecx, &edx); 536 537 return ebx; 538 } 539 540 static inline unsigned int cpuid_ecx(unsigned int op) 541 { 542 unsigned int eax, ebx, ecx, edx; 543 544 cpuid(op, &eax, &ebx, &ecx, &edx); 545 546 return ecx; 547 } 548 549 static inline unsigned int cpuid_edx(unsigned int op) 550 { 551 unsigned int eax, ebx, ecx, edx; 552 553 cpuid(op, &eax, &ebx, &ecx, &edx); 554 555 return edx; 556 } 557 558 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */ 559 static __always_inline void rep_nop(void) 560 { 561 asm volatile("rep; nop" ::: "memory"); 562 } 563 564 static __always_inline void cpu_relax(void) 565 { 566 rep_nop(); 567 } 568 569 #define cpu_relax_lowlatency() cpu_relax() 570 571 /* Stop speculative execution and prefetching of modified code. */ 572 static inline void sync_core(void) 573 { 574 int tmp; 575 576 #ifdef CONFIG_M486 577 /* 578 * Do a CPUID if available, otherwise do a jump. The jump 579 * can conveniently enough be the jump around CPUID. 580 */ 581 asm volatile("cmpl %2,%1\n\t" 582 "jl 1f\n\t" 583 "cpuid\n" 584 "1:" 585 : "=a" (tmp) 586 : "rm" (boot_cpu_data.cpuid_level), "ri" (0), "0" (1) 587 : "ebx", "ecx", "edx", "memory"); 588 #else 589 /* 590 * CPUID is a barrier to speculative execution. 591 * Prefetched instructions are automatically 592 * invalidated when modified. 593 */ 594 asm volatile("cpuid" 595 : "=a" (tmp) 596 : "0" (1) 597 : "ebx", "ecx", "edx", "memory"); 598 #endif 599 } 600 601 extern void select_idle_routine(const struct cpuinfo_x86 *c); 602 extern void init_amd_e400_c1e_mask(void); 603 604 extern unsigned long boot_option_idle_override; 605 extern bool amd_e400_c1e_detected; 606 607 enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_NOMWAIT, 608 IDLE_POLL}; 609 610 extern void enable_sep_cpu(void); 611 extern int sysenter_setup(void); 612 613 extern void early_trap_init(void); 614 void early_trap_pf_init(void); 615 616 /* Defined in head.S */ 617 extern struct desc_ptr early_gdt_descr; 618 619 extern void cpu_set_gdt(int); 620 extern void switch_to_new_gdt(int); 621 extern void load_percpu_segment(int); 622 extern void cpu_init(void); 623 624 static inline unsigned long get_debugctlmsr(void) 625 { 626 unsigned long debugctlmsr = 0; 627 628 #ifndef CONFIG_X86_DEBUGCTLMSR 629 if (boot_cpu_data.x86 < 6) 630 return 0; 631 #endif 632 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr); 633 634 return debugctlmsr; 635 } 636 637 static inline void update_debugctlmsr(unsigned long debugctlmsr) 638 { 639 #ifndef CONFIG_X86_DEBUGCTLMSR 640 if (boot_cpu_data.x86 < 6) 641 return; 642 #endif 643 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr); 644 } 645 646 extern void set_task_blockstep(struct task_struct *task, bool on); 647 648 /* Boot loader type from the setup header: */ 649 extern int bootloader_type; 650 extern int bootloader_version; 651 652 extern char ignore_fpu_irq; 653 654 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1 655 #define ARCH_HAS_PREFETCHW 656 #define ARCH_HAS_SPINLOCK_PREFETCH 657 658 #ifdef CONFIG_X86_32 659 # define BASE_PREFETCH "" 660 # define ARCH_HAS_PREFETCH 661 #else 662 # define BASE_PREFETCH "prefetcht0 %P1" 663 #endif 664 665 /* 666 * Prefetch instructions for Pentium III (+) and AMD Athlon (+) 667 * 668 * It's not worth to care about 3dnow prefetches for the K6 669 * because they are microcoded there and very slow. 670 */ 671 static inline void prefetch(const void *x) 672 { 673 alternative_input(BASE_PREFETCH, "prefetchnta %P1", 674 X86_FEATURE_XMM, 675 "m" (*(const char *)x)); 676 } 677 678 /* 679 * 3dnow prefetch to get an exclusive cache line. 680 * Useful for spinlocks to avoid one state transition in the 681 * cache coherency protocol: 682 */ 683 static inline void prefetchw(const void *x) 684 { 685 alternative_input(BASE_PREFETCH, "prefetchw %P1", 686 X86_FEATURE_3DNOWPREFETCH, 687 "m" (*(const char *)x)); 688 } 689 690 static inline void spin_lock_prefetch(const void *x) 691 { 692 prefetchw(x); 693 } 694 695 #define TOP_OF_INIT_STACK ((unsigned long)&init_stack + sizeof(init_stack) - \ 696 TOP_OF_KERNEL_STACK_PADDING) 697 698 #ifdef CONFIG_X86_32 699 /* 700 * User space process size: 3GB (default). 701 */ 702 #define TASK_SIZE PAGE_OFFSET 703 #define TASK_SIZE_MAX TASK_SIZE 704 #define STACK_TOP TASK_SIZE 705 #define STACK_TOP_MAX STACK_TOP 706 707 #define INIT_THREAD { \ 708 .sp0 = TOP_OF_INIT_STACK, \ 709 .sysenter_cs = __KERNEL_CS, \ 710 .io_bitmap_ptr = NULL, \ 711 } 712 713 extern unsigned long thread_saved_pc(struct task_struct *tsk); 714 715 /* 716 * TOP_OF_KERNEL_STACK_PADDING reserves 8 bytes on top of the ring0 stack. 717 * This is necessary to guarantee that the entire "struct pt_regs" 718 * is accessible even if the CPU haven't stored the SS/ESP registers 719 * on the stack (interrupt gate does not save these registers 720 * when switching to the same priv ring). 721 * Therefore beware: accessing the ss/esp fields of the 722 * "struct pt_regs" is possible, but they may contain the 723 * completely wrong values. 724 */ 725 #define task_pt_regs(task) \ 726 ({ \ 727 unsigned long __ptr = (unsigned long)task_stack_page(task); \ 728 __ptr += THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING; \ 729 ((struct pt_regs *)__ptr) - 1; \ 730 }) 731 732 #define KSTK_ESP(task) (task_pt_regs(task)->sp) 733 734 #else 735 /* 736 * User space process size. 47bits minus one guard page. The guard 737 * page is necessary on Intel CPUs: if a SYSCALL instruction is at 738 * the highest possible canonical userspace address, then that 739 * syscall will enter the kernel with a non-canonical return 740 * address, and SYSRET will explode dangerously. We avoid this 741 * particular problem by preventing anything from being mapped 742 * at the maximum canonical address. 743 */ 744 #define TASK_SIZE_MAX ((1UL << 47) - PAGE_SIZE) 745 746 /* This decides where the kernel will search for a free chunk of vm 747 * space during mmap's. 748 */ 749 #define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? \ 750 0xc0000000 : 0xFFFFe000) 751 752 #define TASK_SIZE (test_thread_flag(TIF_ADDR32) ? \ 753 IA32_PAGE_OFFSET : TASK_SIZE_MAX) 754 #define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_ADDR32)) ? \ 755 IA32_PAGE_OFFSET : TASK_SIZE_MAX) 756 757 #define STACK_TOP TASK_SIZE 758 #define STACK_TOP_MAX TASK_SIZE_MAX 759 760 #define INIT_THREAD { \ 761 .sp0 = TOP_OF_INIT_STACK \ 762 } 763 764 /* 765 * Return saved PC of a blocked thread. 766 * What is this good for? it will be always the scheduler or ret_from_fork. 767 */ 768 #define thread_saved_pc(t) READ_ONCE_NOCHECK(*(unsigned long *)((t)->thread.sp - 8)) 769 770 #define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.sp0 - 1) 771 extern unsigned long KSTK_ESP(struct task_struct *task); 772 773 #endif /* CONFIG_X86_64 */ 774 775 extern void start_thread(struct pt_regs *regs, unsigned long new_ip, 776 unsigned long new_sp); 777 778 /* 779 * This decides where the kernel will search for a free chunk of vm 780 * space during mmap's. 781 */ 782 #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3)) 783 784 #define KSTK_EIP(task) (task_pt_regs(task)->ip) 785 786 /* Get/set a process' ability to use the timestamp counter instruction */ 787 #define GET_TSC_CTL(adr) get_tsc_mode((adr)) 788 #define SET_TSC_CTL(val) set_tsc_mode((val)) 789 790 extern int get_tsc_mode(unsigned long adr); 791 extern int set_tsc_mode(unsigned int val); 792 793 /* Register/unregister a process' MPX related resource */ 794 #define MPX_ENABLE_MANAGEMENT() mpx_enable_management() 795 #define MPX_DISABLE_MANAGEMENT() mpx_disable_management() 796 797 #ifdef CONFIG_X86_INTEL_MPX 798 extern int mpx_enable_management(void); 799 extern int mpx_disable_management(void); 800 #else 801 static inline int mpx_enable_management(void) 802 { 803 return -EINVAL; 804 } 805 static inline int mpx_disable_management(void) 806 { 807 return -EINVAL; 808 } 809 #endif /* CONFIG_X86_INTEL_MPX */ 810 811 extern u16 amd_get_nb_id(int cpu); 812 extern u32 amd_get_nodes_per_socket(void); 813 814 static inline uint32_t hypervisor_cpuid_base(const char *sig, uint32_t leaves) 815 { 816 uint32_t base, eax, signature[3]; 817 818 for (base = 0x40000000; base < 0x40010000; base += 0x100) { 819 cpuid(base, &eax, &signature[0], &signature[1], &signature[2]); 820 821 if (!memcmp(sig, signature, 12) && 822 (leaves == 0 || ((eax - base) >= leaves))) 823 return base; 824 } 825 826 return 0; 827 } 828 829 extern unsigned long arch_align_stack(unsigned long sp); 830 extern void free_init_pages(char *what, unsigned long begin, unsigned long end); 831 832 void default_idle(void); 833 #ifdef CONFIG_XEN 834 bool xen_set_default_idle(void); 835 #else 836 #define xen_set_default_idle 0 837 #endif 838 839 void stop_this_cpu(void *dummy); 840 void df_debug(struct pt_regs *regs, long error_code); 841 #endif /* _ASM_X86_PROCESSOR_H */ 842