1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _ASM_X86_PROCESSOR_H 3 #define _ASM_X86_PROCESSOR_H 4 5 #include <asm/processor-flags.h> 6 7 /* Forward declaration, a strange C thing */ 8 struct task_struct; 9 struct mm_struct; 10 struct io_bitmap; 11 struct vm86; 12 13 #include <asm/math_emu.h> 14 #include <asm/segment.h> 15 #include <asm/types.h> 16 #include <uapi/asm/sigcontext.h> 17 #include <asm/current.h> 18 #include <asm/cpufeatures.h> 19 #include <asm/cpuid.h> 20 #include <asm/page.h> 21 #include <asm/pgtable_types.h> 22 #include <asm/percpu.h> 23 #include <asm/desc_defs.h> 24 #include <asm/nops.h> 25 #include <asm/special_insns.h> 26 #include <asm/fpu/types.h> 27 #include <asm/unwind_hints.h> 28 #include <asm/vmxfeatures.h> 29 #include <asm/vdso/processor.h> 30 #include <asm/shstk.h> 31 32 #include <linux/personality.h> 33 #include <linux/cache.h> 34 #include <linux/threads.h> 35 #include <linux/math64.h> 36 #include <linux/err.h> 37 #include <linux/irqflags.h> 38 #include <linux/mem_encrypt.h> 39 40 /* 41 * We handle most unaligned accesses in hardware. On the other hand 42 * unaligned DMA can be quite expensive on some Nehalem processors. 43 * 44 * Based on this we disable the IP header alignment in network drivers. 45 */ 46 #define NET_IP_ALIGN 0 47 48 #define HBP_NUM 4 49 50 /* 51 * These alignment constraints are for performance in the vSMP case, 52 * but in the task_struct case we must also meet hardware imposed 53 * alignment requirements of the FPU state: 54 */ 55 #ifdef CONFIG_X86_VSMP 56 # define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT) 57 # define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT) 58 #else 59 # define ARCH_MIN_TASKALIGN __alignof__(union fpregs_state) 60 # define ARCH_MIN_MMSTRUCT_ALIGN 0 61 #endif 62 63 enum tlb_infos { 64 ENTRIES, 65 NR_INFO 66 }; 67 68 extern u16 __read_mostly tlb_lli_4k[NR_INFO]; 69 extern u16 __read_mostly tlb_lli_2m[NR_INFO]; 70 extern u16 __read_mostly tlb_lli_4m[NR_INFO]; 71 extern u16 __read_mostly tlb_lld_4k[NR_INFO]; 72 extern u16 __read_mostly tlb_lld_2m[NR_INFO]; 73 extern u16 __read_mostly tlb_lld_4m[NR_INFO]; 74 extern u16 __read_mostly tlb_lld_1g[NR_INFO]; 75 76 /* 77 * CPU type and hardware bug flags. Kept separately for each CPU. 78 */ 79 80 struct cpuinfo_topology { 81 // Real APIC ID read from the local APIC 82 u32 apicid; 83 // The initial APIC ID provided by CPUID 84 u32 initial_apicid; 85 86 // Physical package ID 87 u32 pkg_id; 88 89 // Physical die ID on AMD, Relative on Intel 90 u32 die_id; 91 92 // Compute unit ID - AMD specific 93 u32 cu_id; 94 95 // Core ID relative to the package 96 u32 core_id; 97 98 // Logical ID mappings 99 u32 logical_pkg_id; 100 u32 logical_die_id; 101 102 // AMD Node ID and Nodes per Package info 103 u32 amd_node_id; 104 105 // Cache level topology IDs 106 u32 llc_id; 107 u32 l2c_id; 108 109 // Hardware defined CPU-type 110 union { 111 u32 cpu_type; 112 struct { 113 // CPUID.1A.EAX[23-0] 114 u32 intel_native_model_id :24; 115 // CPUID.1A.EAX[31-24] 116 u32 intel_type :8; 117 }; 118 struct { 119 // CPUID 0x80000026.EBX 120 u32 amd_num_processors :16, 121 amd_power_eff_ranking :8, 122 amd_native_model_id :4, 123 amd_type :4; 124 }; 125 }; 126 }; 127 128 struct cpuinfo_x86 { 129 union { 130 /* 131 * The particular ordering (low-to-high) of (vendor, 132 * family, model) is done in case range of models, like 133 * it is usually done on AMD, need to be compared. 134 */ 135 struct { 136 __u8 x86_model; 137 /* CPU family */ 138 __u8 x86; 139 /* CPU vendor */ 140 __u8 x86_vendor; 141 __u8 x86_reserved; 142 }; 143 /* combined vendor, family, model */ 144 __u32 x86_vfm; 145 }; 146 __u8 x86_stepping; 147 #ifdef CONFIG_X86_64 148 /* Number of 4K pages in DTLB/ITLB combined(in pages): */ 149 int x86_tlbsize; 150 #endif 151 #ifdef CONFIG_X86_VMX_FEATURE_NAMES 152 __u32 vmx_capability[NVMXINTS]; 153 #endif 154 __u8 x86_virt_bits; 155 __u8 x86_phys_bits; 156 /* Max extended CPUID function supported: */ 157 __u32 extended_cpuid_level; 158 /* Maximum supported CPUID level, -1=no CPUID: */ 159 int cpuid_level; 160 /* 161 * Align to size of unsigned long because the x86_capability array 162 * is passed to bitops which require the alignment. Use unnamed 163 * union to enforce the array is aligned to size of unsigned long. 164 */ 165 union { 166 __u32 x86_capability[NCAPINTS + NBUGINTS]; 167 unsigned long x86_capability_alignment; 168 }; 169 char x86_vendor_id[16]; 170 char x86_model_id[64]; 171 struct cpuinfo_topology topo; 172 /* in KB - valid for CPUS which support this call: */ 173 unsigned int x86_cache_size; 174 int x86_cache_alignment; /* In bytes */ 175 /* Cache QoS architectural values, valid only on the BSP: */ 176 int x86_cache_max_rmid; /* max index */ 177 int x86_cache_occ_scale; /* scale to bytes */ 178 int x86_cache_mbm_width_offset; 179 int x86_power; 180 unsigned long loops_per_jiffy; 181 /* protected processor identification number */ 182 u64 ppin; 183 u16 x86_clflush_size; 184 /* number of cores as seen by the OS: */ 185 u16 booted_cores; 186 /* Index into per_cpu list: */ 187 u16 cpu_index; 188 /* Is SMT active on this core? */ 189 bool smt_active; 190 u32 microcode; 191 /* Address space bits used by the cache internally */ 192 u8 x86_cache_bits; 193 unsigned initialized : 1; 194 } __randomize_layout; 195 196 #define X86_VENDOR_INTEL 0 197 #define X86_VENDOR_CYRIX 1 198 #define X86_VENDOR_AMD 2 199 #define X86_VENDOR_UMC 3 200 #define X86_VENDOR_CENTAUR 5 201 #define X86_VENDOR_TRANSMETA 7 202 #define X86_VENDOR_NSC 8 203 #define X86_VENDOR_HYGON 9 204 #define X86_VENDOR_ZHAOXIN 10 205 #define X86_VENDOR_VORTEX 11 206 #define X86_VENDOR_NUM 12 207 208 #define X86_VENDOR_UNKNOWN 0xff 209 210 /* 211 * capabilities of CPUs 212 */ 213 extern struct cpuinfo_x86 boot_cpu_data; 214 extern struct cpuinfo_x86 new_cpu_data; 215 216 extern __u32 cpu_caps_cleared[NCAPINTS + NBUGINTS]; 217 extern __u32 cpu_caps_set[NCAPINTS + NBUGINTS]; 218 219 DECLARE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info); 220 #define cpu_data(cpu) per_cpu(cpu_info, cpu) 221 222 extern const struct seq_operations cpuinfo_op; 223 224 #define cache_line_size() (boot_cpu_data.x86_cache_alignment) 225 226 extern void cpu_detect(struct cpuinfo_x86 *c); 227 228 static inline unsigned long long l1tf_pfn_limit(void) 229 { 230 return BIT_ULL(boot_cpu_data.x86_cache_bits - 1 - PAGE_SHIFT); 231 } 232 233 void init_cpu_devs(void); 234 void get_cpu_vendor(struct cpuinfo_x86 *c); 235 extern void early_cpu_init(void); 236 extern void identify_secondary_cpu(struct cpuinfo_x86 *); 237 extern void print_cpu_info(struct cpuinfo_x86 *); 238 void print_cpu_msr(struct cpuinfo_x86 *); 239 240 /* 241 * Friendlier CR3 helpers. 242 */ 243 static inline unsigned long read_cr3_pa(void) 244 { 245 return __read_cr3() & CR3_ADDR_MASK; 246 } 247 248 static inline unsigned long native_read_cr3_pa(void) 249 { 250 return __native_read_cr3() & CR3_ADDR_MASK; 251 } 252 253 static inline void load_cr3(pgd_t *pgdir) 254 { 255 write_cr3(__sme_pa(pgdir)); 256 } 257 258 /* 259 * Note that while the legacy 'TSS' name comes from 'Task State Segment', 260 * on modern x86 CPUs the TSS also holds information important to 64-bit mode, 261 * unrelated to the task-switch mechanism: 262 */ 263 #ifdef CONFIG_X86_32 264 /* This is the TSS defined by the hardware. */ 265 struct x86_hw_tss { 266 unsigned short back_link, __blh; 267 unsigned long sp0; 268 unsigned short ss0, __ss0h; 269 unsigned long sp1; 270 271 /* 272 * We don't use ring 1, so ss1 is a convenient scratch space in 273 * the same cacheline as sp0. We use ss1 to cache the value in 274 * MSR_IA32_SYSENTER_CS. When we context switch 275 * MSR_IA32_SYSENTER_CS, we first check if the new value being 276 * written matches ss1, and, if it's not, then we wrmsr the new 277 * value and update ss1. 278 * 279 * The only reason we context switch MSR_IA32_SYSENTER_CS is 280 * that we set it to zero in vm86 tasks to avoid corrupting the 281 * stack if we were to go through the sysenter path from vm86 282 * mode. 283 */ 284 unsigned short ss1; /* MSR_IA32_SYSENTER_CS */ 285 286 unsigned short __ss1h; 287 unsigned long sp2; 288 unsigned short ss2, __ss2h; 289 unsigned long __cr3; 290 unsigned long ip; 291 unsigned long flags; 292 unsigned long ax; 293 unsigned long cx; 294 unsigned long dx; 295 unsigned long bx; 296 unsigned long sp; 297 unsigned long bp; 298 unsigned long si; 299 unsigned long di; 300 unsigned short es, __esh; 301 unsigned short cs, __csh; 302 unsigned short ss, __ssh; 303 unsigned short ds, __dsh; 304 unsigned short fs, __fsh; 305 unsigned short gs, __gsh; 306 unsigned short ldt, __ldth; 307 unsigned short trace; 308 unsigned short io_bitmap_base; 309 310 } __attribute__((packed)); 311 #else 312 struct x86_hw_tss { 313 u32 reserved1; 314 u64 sp0; 315 u64 sp1; 316 317 /* 318 * Since Linux does not use ring 2, the 'sp2' slot is unused by 319 * hardware. entry_SYSCALL_64 uses it as scratch space to stash 320 * the user RSP value. 321 */ 322 u64 sp2; 323 324 u64 reserved2; 325 u64 ist[7]; 326 u32 reserved3; 327 u32 reserved4; 328 u16 reserved5; 329 u16 io_bitmap_base; 330 331 } __attribute__((packed)); 332 #endif 333 334 /* 335 * IO-bitmap sizes: 336 */ 337 #define IO_BITMAP_BITS 65536 338 #define IO_BITMAP_BYTES (IO_BITMAP_BITS / BITS_PER_BYTE) 339 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES / sizeof(long)) 340 341 #define IO_BITMAP_OFFSET_VALID_MAP \ 342 (offsetof(struct tss_struct, io_bitmap.bitmap) - \ 343 offsetof(struct tss_struct, x86_tss)) 344 345 #define IO_BITMAP_OFFSET_VALID_ALL \ 346 (offsetof(struct tss_struct, io_bitmap.mapall) - \ 347 offsetof(struct tss_struct, x86_tss)) 348 349 #ifdef CONFIG_X86_IOPL_IOPERM 350 /* 351 * sizeof(unsigned long) coming from an extra "long" at the end of the 352 * iobitmap. The limit is inclusive, i.e. the last valid byte. 353 */ 354 # define __KERNEL_TSS_LIMIT \ 355 (IO_BITMAP_OFFSET_VALID_ALL + IO_BITMAP_BYTES + \ 356 sizeof(unsigned long) - 1) 357 #else 358 # define __KERNEL_TSS_LIMIT \ 359 (offsetof(struct tss_struct, x86_tss) + sizeof(struct x86_hw_tss) - 1) 360 #endif 361 362 /* Base offset outside of TSS_LIMIT so unpriviledged IO causes #GP */ 363 #define IO_BITMAP_OFFSET_INVALID (__KERNEL_TSS_LIMIT + 1) 364 365 struct entry_stack { 366 char stack[PAGE_SIZE]; 367 }; 368 369 struct entry_stack_page { 370 struct entry_stack stack; 371 } __aligned(PAGE_SIZE); 372 373 /* 374 * All IO bitmap related data stored in the TSS: 375 */ 376 struct x86_io_bitmap { 377 /* The sequence number of the last active bitmap. */ 378 u64 prev_sequence; 379 380 /* 381 * Store the dirty size of the last io bitmap offender. The next 382 * one will have to do the cleanup as the switch out to a non io 383 * bitmap user will just set x86_tss.io_bitmap_base to a value 384 * outside of the TSS limit. So for sane tasks there is no need to 385 * actually touch the io_bitmap at all. 386 */ 387 unsigned int prev_max; 388 389 /* 390 * The extra 1 is there because the CPU will access an 391 * additional byte beyond the end of the IO permission 392 * bitmap. The extra byte must be all 1 bits, and must 393 * be within the limit. 394 */ 395 unsigned long bitmap[IO_BITMAP_LONGS + 1]; 396 397 /* 398 * Special I/O bitmap to emulate IOPL(3). All bytes zero, 399 * except the additional byte at the end. 400 */ 401 unsigned long mapall[IO_BITMAP_LONGS + 1]; 402 }; 403 404 struct tss_struct { 405 /* 406 * The fixed hardware portion. This must not cross a page boundary 407 * at risk of violating the SDM's advice and potentially triggering 408 * errata. 409 */ 410 struct x86_hw_tss x86_tss; 411 412 struct x86_io_bitmap io_bitmap; 413 } __aligned(PAGE_SIZE); 414 415 DECLARE_PER_CPU_PAGE_ALIGNED(struct tss_struct, cpu_tss_rw); 416 417 /* Per CPU interrupt stacks */ 418 struct irq_stack { 419 char stack[IRQ_STACK_SIZE]; 420 } __aligned(IRQ_STACK_SIZE); 421 422 #ifdef CONFIG_X86_64 423 struct fixed_percpu_data { 424 /* 425 * GCC hardcodes the stack canary as %gs:40. Since the 426 * irq_stack is the object at %gs:0, we reserve the bottom 427 * 48 bytes of the irq stack for the canary. 428 * 429 * Once we are willing to require -mstack-protector-guard-symbol= 430 * support for x86_64 stackprotector, we can get rid of this. 431 */ 432 char gs_base[40]; 433 unsigned long stack_canary; 434 }; 435 436 DECLARE_PER_CPU_FIRST(struct fixed_percpu_data, fixed_percpu_data) __visible; 437 DECLARE_INIT_PER_CPU(fixed_percpu_data); 438 439 static inline unsigned long cpu_kernelmode_gs_base(int cpu) 440 { 441 return (unsigned long)per_cpu(fixed_percpu_data.gs_base, cpu); 442 } 443 444 extern asmlinkage void entry_SYSCALL32_ignore(void); 445 446 /* Save actual FS/GS selectors and bases to current->thread */ 447 void current_save_fsgs(void); 448 #else /* X86_64 */ 449 #ifdef CONFIG_STACKPROTECTOR 450 DECLARE_PER_CPU(unsigned long, __stack_chk_guard); 451 #endif 452 #endif /* !X86_64 */ 453 454 struct perf_event; 455 456 struct thread_struct { 457 /* Cached TLS descriptors: */ 458 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES]; 459 #ifdef CONFIG_X86_32 460 unsigned long sp0; 461 #endif 462 unsigned long sp; 463 #ifdef CONFIG_X86_32 464 unsigned long sysenter_cs; 465 #else 466 unsigned short es; 467 unsigned short ds; 468 unsigned short fsindex; 469 unsigned short gsindex; 470 #endif 471 472 #ifdef CONFIG_X86_64 473 unsigned long fsbase; 474 unsigned long gsbase; 475 #else 476 /* 477 * XXX: this could presumably be unsigned short. Alternatively, 478 * 32-bit kernels could be taught to use fsindex instead. 479 */ 480 unsigned long fs; 481 unsigned long gs; 482 #endif 483 484 /* Save middle states of ptrace breakpoints */ 485 struct perf_event *ptrace_bps[HBP_NUM]; 486 /* Debug status used for traps, single steps, etc... */ 487 unsigned long virtual_dr6; 488 /* Keep track of the exact dr7 value set by the user */ 489 unsigned long ptrace_dr7; 490 /* Fault info: */ 491 unsigned long cr2; 492 unsigned long trap_nr; 493 unsigned long error_code; 494 #ifdef CONFIG_VM86 495 /* Virtual 86 mode info */ 496 struct vm86 *vm86; 497 #endif 498 /* IO permissions: */ 499 struct io_bitmap *io_bitmap; 500 501 /* 502 * IOPL. Privilege level dependent I/O permission which is 503 * emulated via the I/O bitmap to prevent user space from disabling 504 * interrupts. 505 */ 506 unsigned long iopl_emul; 507 508 unsigned int iopl_warn:1; 509 510 /* 511 * Protection Keys Register for Userspace. Loaded immediately on 512 * context switch. Store it in thread_struct to avoid a lookup in 513 * the tasks's FPU xstate buffer. This value is only valid when a 514 * task is scheduled out. For 'current' the authoritative source of 515 * PKRU is the hardware itself. 516 */ 517 u32 pkru; 518 519 #ifdef CONFIG_X86_USER_SHADOW_STACK 520 unsigned long features; 521 unsigned long features_locked; 522 523 struct thread_shstk shstk; 524 #endif 525 526 /* Floating point and extended processor state */ 527 struct fpu fpu; 528 /* 529 * WARNING: 'fpu' is dynamically-sized. It *MUST* be at 530 * the end. 531 */ 532 }; 533 534 extern void fpu_thread_struct_whitelist(unsigned long *offset, unsigned long *size); 535 536 static inline void arch_thread_struct_whitelist(unsigned long *offset, 537 unsigned long *size) 538 { 539 fpu_thread_struct_whitelist(offset, size); 540 } 541 542 static inline void 543 native_load_sp0(unsigned long sp0) 544 { 545 this_cpu_write(cpu_tss_rw.x86_tss.sp0, sp0); 546 } 547 548 static __always_inline void native_swapgs(void) 549 { 550 #ifdef CONFIG_X86_64 551 asm volatile("swapgs" ::: "memory"); 552 #endif 553 } 554 555 static __always_inline unsigned long current_top_of_stack(void) 556 { 557 /* 558 * We can't read directly from tss.sp0: sp0 on x86_32 is special in 559 * and around vm86 mode and sp0 on x86_64 is special because of the 560 * entry trampoline. 561 */ 562 if (IS_ENABLED(CONFIG_USE_X86_SEG_SUPPORT)) 563 return this_cpu_read_const(const_pcpu_hot.top_of_stack); 564 565 return this_cpu_read_stable(pcpu_hot.top_of_stack); 566 } 567 568 static __always_inline bool on_thread_stack(void) 569 { 570 return (unsigned long)(current_top_of_stack() - 571 current_stack_pointer) < THREAD_SIZE; 572 } 573 574 #ifdef CONFIG_PARAVIRT_XXL 575 #include <asm/paravirt.h> 576 #else 577 578 static inline void load_sp0(unsigned long sp0) 579 { 580 native_load_sp0(sp0); 581 } 582 583 #endif /* CONFIG_PARAVIRT_XXL */ 584 585 unsigned long __get_wchan(struct task_struct *p); 586 587 extern void select_idle_routine(void); 588 extern void amd_e400_c1e_apic_setup(void); 589 590 extern unsigned long boot_option_idle_override; 591 592 enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_NOMWAIT, 593 IDLE_POLL}; 594 595 extern void enable_sep_cpu(void); 596 597 598 /* Defined in head.S */ 599 extern struct desc_ptr early_gdt_descr; 600 601 extern void switch_gdt_and_percpu_base(int); 602 extern void load_direct_gdt(int); 603 extern void load_fixmap_gdt(int); 604 extern void cpu_init(void); 605 extern void cpu_init_exception_handling(bool boot_cpu); 606 extern void cpu_init_replace_early_idt(void); 607 extern void cr4_init(void); 608 609 extern void set_task_blockstep(struct task_struct *task, bool on); 610 611 /* Boot loader type from the setup header: */ 612 extern int bootloader_type; 613 extern int bootloader_version; 614 615 extern char ignore_fpu_irq; 616 617 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1 618 #define ARCH_HAS_PREFETCHW 619 620 #ifdef CONFIG_X86_32 621 # define BASE_PREFETCH "" 622 # define ARCH_HAS_PREFETCH 623 #else 624 # define BASE_PREFETCH "prefetcht0 %1" 625 #endif 626 627 /* 628 * Prefetch instructions for Pentium III (+) and AMD Athlon (+) 629 * 630 * It's not worth to care about 3dnow prefetches for the K6 631 * because they are microcoded there and very slow. 632 */ 633 static inline void prefetch(const void *x) 634 { 635 alternative_input(BASE_PREFETCH, "prefetchnta %1", 636 X86_FEATURE_XMM, 637 "m" (*(const char *)x)); 638 } 639 640 /* 641 * 3dnow prefetch to get an exclusive cache line. 642 * Useful for spinlocks to avoid one state transition in the 643 * cache coherency protocol: 644 */ 645 static __always_inline void prefetchw(const void *x) 646 { 647 alternative_input(BASE_PREFETCH, "prefetchw %1", 648 X86_FEATURE_3DNOWPREFETCH, 649 "m" (*(const char *)x)); 650 } 651 652 #define TOP_OF_INIT_STACK ((unsigned long)&init_stack + sizeof(init_stack) - \ 653 TOP_OF_KERNEL_STACK_PADDING) 654 655 #define task_top_of_stack(task) ((unsigned long)(task_pt_regs(task) + 1)) 656 657 #define task_pt_regs(task) \ 658 ({ \ 659 unsigned long __ptr = (unsigned long)task_stack_page(task); \ 660 __ptr += THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING; \ 661 ((struct pt_regs *)__ptr) - 1; \ 662 }) 663 664 #ifdef CONFIG_X86_32 665 #define INIT_THREAD { \ 666 .sp0 = TOP_OF_INIT_STACK, \ 667 .sysenter_cs = __KERNEL_CS, \ 668 } 669 670 #define KSTK_ESP(task) (task_pt_regs(task)->sp) 671 672 #else 673 extern unsigned long __top_init_kernel_stack[]; 674 675 #define INIT_THREAD { \ 676 .sp = (unsigned long)&__top_init_kernel_stack, \ 677 } 678 679 extern unsigned long KSTK_ESP(struct task_struct *task); 680 681 #endif /* CONFIG_X86_64 */ 682 683 extern void start_thread(struct pt_regs *regs, unsigned long new_ip, 684 unsigned long new_sp); 685 686 /* 687 * This decides where the kernel will search for a free chunk of vm 688 * space during mmap's. 689 */ 690 #define __TASK_UNMAPPED_BASE(task_size) (PAGE_ALIGN(task_size / 3)) 691 #define TASK_UNMAPPED_BASE __TASK_UNMAPPED_BASE(TASK_SIZE_LOW) 692 693 #define KSTK_EIP(task) (task_pt_regs(task)->ip) 694 695 /* Get/set a process' ability to use the timestamp counter instruction */ 696 #define GET_TSC_CTL(adr) get_tsc_mode((adr)) 697 #define SET_TSC_CTL(val) set_tsc_mode((val)) 698 699 extern int get_tsc_mode(unsigned long adr); 700 extern int set_tsc_mode(unsigned int val); 701 702 DECLARE_PER_CPU(u64, msr_misc_features_shadow); 703 704 static inline u32 per_cpu_llc_id(unsigned int cpu) 705 { 706 return per_cpu(cpu_info.topo.llc_id, cpu); 707 } 708 709 static inline u32 per_cpu_l2c_id(unsigned int cpu) 710 { 711 return per_cpu(cpu_info.topo.l2c_id, cpu); 712 } 713 714 #ifdef CONFIG_CPU_SUP_AMD 715 /* 716 * Issue a DIV 0/1 insn to clear any division data from previous DIV 717 * operations. 718 */ 719 static __always_inline void amd_clear_divider(void) 720 { 721 asm volatile(ALTERNATIVE("", "div %2\n\t", X86_BUG_DIV0) 722 :: "a" (0), "d" (0), "r" (1)); 723 } 724 725 extern void amd_check_microcode(void); 726 #else 727 static inline void amd_clear_divider(void) { } 728 static inline void amd_check_microcode(void) { } 729 #endif 730 731 extern unsigned long arch_align_stack(unsigned long sp); 732 void free_init_pages(const char *what, unsigned long begin, unsigned long end); 733 extern void free_kernel_image_pages(const char *what, void *begin, void *end); 734 735 void default_idle(void); 736 #ifdef CONFIG_XEN 737 bool xen_set_default_idle(void); 738 #else 739 #define xen_set_default_idle 0 740 #endif 741 742 void __noreturn stop_this_cpu(void *dummy); 743 void microcode_check(struct cpuinfo_x86 *prev_info); 744 void store_cpu_caps(struct cpuinfo_x86 *info); 745 746 enum l1tf_mitigations { 747 L1TF_MITIGATION_OFF, 748 L1TF_MITIGATION_FLUSH_NOWARN, 749 L1TF_MITIGATION_FLUSH, 750 L1TF_MITIGATION_FLUSH_NOSMT, 751 L1TF_MITIGATION_FULL, 752 L1TF_MITIGATION_FULL_FORCE 753 }; 754 755 extern enum l1tf_mitigations l1tf_mitigation; 756 757 enum mds_mitigations { 758 MDS_MITIGATION_OFF, 759 MDS_MITIGATION_FULL, 760 MDS_MITIGATION_VMWERV, 761 }; 762 763 extern bool gds_ucode_mitigated(void); 764 765 /* 766 * Make previous memory operations globally visible before 767 * a WRMSR. 768 * 769 * MFENCE makes writes visible, but only affects load/store 770 * instructions. WRMSR is unfortunately not a load/store 771 * instruction and is unaffected by MFENCE. The LFENCE ensures 772 * that the WRMSR is not reordered. 773 * 774 * Most WRMSRs are full serializing instructions themselves and 775 * do not require this barrier. This is only required for the 776 * IA32_TSC_DEADLINE and X2APIC MSRs. 777 */ 778 static inline void weak_wrmsr_fence(void) 779 { 780 alternative("mfence; lfence", "", ALT_NOT(X86_FEATURE_APIC_MSRS_FENCE)); 781 } 782 783 #endif /* _ASM_X86_PROCESSOR_H */ 784