1 #ifndef _ASM_X86_PROCESSOR_H 2 #define _ASM_X86_PROCESSOR_H 3 4 #include <asm/processor-flags.h> 5 6 /* Forward declaration, a strange C thing */ 7 struct task_struct; 8 struct mm_struct; 9 10 #include <asm/vm86.h> 11 #include <asm/math_emu.h> 12 #include <asm/segment.h> 13 #include <asm/types.h> 14 #include <asm/sigcontext.h> 15 #include <asm/current.h> 16 #include <asm/cpufeature.h> 17 #include <asm/page.h> 18 #include <asm/pgtable_types.h> 19 #include <asm/percpu.h> 20 #include <asm/msr.h> 21 #include <asm/desc_defs.h> 22 #include <asm/nops.h> 23 #include <asm/special_insns.h> 24 25 #include <linux/personality.h> 26 #include <linux/cpumask.h> 27 #include <linux/cache.h> 28 #include <linux/threads.h> 29 #include <linux/math64.h> 30 #include <linux/init.h> 31 #include <linux/err.h> 32 #include <linux/irqflags.h> 33 34 /* 35 * We handle most unaligned accesses in hardware. On the other hand 36 * unaligned DMA can be quite expensive on some Nehalem processors. 37 * 38 * Based on this we disable the IP header alignment in network drivers. 39 */ 40 #define NET_IP_ALIGN 0 41 42 #define HBP_NUM 4 43 /* 44 * Default implementation of macro that returns current 45 * instruction pointer ("program counter"). 46 */ 47 static inline void *current_text_addr(void) 48 { 49 void *pc; 50 51 asm volatile("mov $1f, %0; 1:":"=r" (pc)); 52 53 return pc; 54 } 55 56 #ifdef CONFIG_X86_VSMP 57 # define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT) 58 # define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT) 59 #else 60 # define ARCH_MIN_TASKALIGN 16 61 # define ARCH_MIN_MMSTRUCT_ALIGN 0 62 #endif 63 64 enum tlb_infos { 65 ENTRIES, 66 NR_INFO 67 }; 68 69 extern u16 __read_mostly tlb_lli_4k[NR_INFO]; 70 extern u16 __read_mostly tlb_lli_2m[NR_INFO]; 71 extern u16 __read_mostly tlb_lli_4m[NR_INFO]; 72 extern u16 __read_mostly tlb_lld_4k[NR_INFO]; 73 extern u16 __read_mostly tlb_lld_2m[NR_INFO]; 74 extern u16 __read_mostly tlb_lld_4m[NR_INFO]; 75 extern s8 __read_mostly tlb_flushall_shift; 76 77 /* 78 * CPU type and hardware bug flags. Kept separately for each CPU. 79 * Members of this structure are referenced in head.S, so think twice 80 * before touching them. [mj] 81 */ 82 83 struct cpuinfo_x86 { 84 __u8 x86; /* CPU family */ 85 __u8 x86_vendor; /* CPU vendor */ 86 __u8 x86_model; 87 __u8 x86_mask; 88 #ifdef CONFIG_X86_32 89 char wp_works_ok; /* It doesn't on 386's */ 90 91 /* Problems on some 486Dx4's and old 386's: */ 92 char hlt_works_ok; 93 char hard_math; 94 char rfu; 95 char fdiv_bug; 96 char f00f_bug; 97 char coma_bug; 98 char pad0; 99 #else 100 /* Number of 4K pages in DTLB/ITLB combined(in pages): */ 101 int x86_tlbsize; 102 #endif 103 __u8 x86_virt_bits; 104 __u8 x86_phys_bits; 105 /* CPUID returned core id bits: */ 106 __u8 x86_coreid_bits; 107 /* Max extended CPUID function supported: */ 108 __u32 extended_cpuid_level; 109 /* Maximum supported CPUID level, -1=no CPUID: */ 110 int cpuid_level; 111 __u32 x86_capability[NCAPINTS]; 112 char x86_vendor_id[16]; 113 char x86_model_id[64]; 114 /* in KB - valid for CPUS which support this call: */ 115 int x86_cache_size; 116 int x86_cache_alignment; /* In bytes */ 117 int x86_power; 118 unsigned long loops_per_jiffy; 119 /* cpuid returned max cores value: */ 120 u16 x86_max_cores; 121 u16 apicid; 122 u16 initial_apicid; 123 u16 x86_clflush_size; 124 /* number of cores as seen by the OS: */ 125 u16 booted_cores; 126 /* Physical processor id: */ 127 u16 phys_proc_id; 128 /* Core id: */ 129 u16 cpu_core_id; 130 /* Compute unit id */ 131 u8 compute_unit_id; 132 /* Index into per_cpu list: */ 133 u16 cpu_index; 134 u32 microcode; 135 } __attribute__((__aligned__(SMP_CACHE_BYTES))); 136 137 #define X86_VENDOR_INTEL 0 138 #define X86_VENDOR_CYRIX 1 139 #define X86_VENDOR_AMD 2 140 #define X86_VENDOR_UMC 3 141 #define X86_VENDOR_CENTAUR 5 142 #define X86_VENDOR_TRANSMETA 7 143 #define X86_VENDOR_NSC 8 144 #define X86_VENDOR_NUM 9 145 146 #define X86_VENDOR_UNKNOWN 0xff 147 148 /* 149 * capabilities of CPUs 150 */ 151 extern struct cpuinfo_x86 boot_cpu_data; 152 extern struct cpuinfo_x86 new_cpu_data; 153 154 extern struct tss_struct doublefault_tss; 155 extern __u32 cpu_caps_cleared[NCAPINTS]; 156 extern __u32 cpu_caps_set[NCAPINTS]; 157 158 #ifdef CONFIG_SMP 159 DECLARE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info); 160 #define cpu_data(cpu) per_cpu(cpu_info, cpu) 161 #else 162 #define cpu_info boot_cpu_data 163 #define cpu_data(cpu) boot_cpu_data 164 #endif 165 166 extern const struct seq_operations cpuinfo_op; 167 168 static inline int hlt_works(int cpu) 169 { 170 #ifdef CONFIG_X86_32 171 return cpu_data(cpu).hlt_works_ok; 172 #else 173 return 1; 174 #endif 175 } 176 177 #define cache_line_size() (boot_cpu_data.x86_cache_alignment) 178 179 extern void cpu_detect(struct cpuinfo_x86 *c); 180 181 extern void early_cpu_init(void); 182 extern void identify_boot_cpu(void); 183 extern void identify_secondary_cpu(struct cpuinfo_x86 *); 184 extern void print_cpu_info(struct cpuinfo_x86 *); 185 void print_cpu_msr(struct cpuinfo_x86 *); 186 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c); 187 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c); 188 extern void init_amd_cacheinfo(struct cpuinfo_x86 *c); 189 190 extern void detect_extended_topology(struct cpuinfo_x86 *c); 191 extern void detect_ht(struct cpuinfo_x86 *c); 192 193 static inline void native_cpuid(unsigned int *eax, unsigned int *ebx, 194 unsigned int *ecx, unsigned int *edx) 195 { 196 /* ecx is often an input as well as an output. */ 197 asm volatile("cpuid" 198 : "=a" (*eax), 199 "=b" (*ebx), 200 "=c" (*ecx), 201 "=d" (*edx) 202 : "0" (*eax), "2" (*ecx) 203 : "memory"); 204 } 205 206 static inline void load_cr3(pgd_t *pgdir) 207 { 208 write_cr3(__pa(pgdir)); 209 } 210 211 #ifdef CONFIG_X86_32 212 /* This is the TSS defined by the hardware. */ 213 struct x86_hw_tss { 214 unsigned short back_link, __blh; 215 unsigned long sp0; 216 unsigned short ss0, __ss0h; 217 unsigned long sp1; 218 /* ss1 caches MSR_IA32_SYSENTER_CS: */ 219 unsigned short ss1, __ss1h; 220 unsigned long sp2; 221 unsigned short ss2, __ss2h; 222 unsigned long __cr3; 223 unsigned long ip; 224 unsigned long flags; 225 unsigned long ax; 226 unsigned long cx; 227 unsigned long dx; 228 unsigned long bx; 229 unsigned long sp; 230 unsigned long bp; 231 unsigned long si; 232 unsigned long di; 233 unsigned short es, __esh; 234 unsigned short cs, __csh; 235 unsigned short ss, __ssh; 236 unsigned short ds, __dsh; 237 unsigned short fs, __fsh; 238 unsigned short gs, __gsh; 239 unsigned short ldt, __ldth; 240 unsigned short trace; 241 unsigned short io_bitmap_base; 242 243 } __attribute__((packed)); 244 #else 245 struct x86_hw_tss { 246 u32 reserved1; 247 u64 sp0; 248 u64 sp1; 249 u64 sp2; 250 u64 reserved2; 251 u64 ist[7]; 252 u32 reserved3; 253 u32 reserved4; 254 u16 reserved5; 255 u16 io_bitmap_base; 256 257 } __attribute__((packed)) ____cacheline_aligned; 258 #endif 259 260 /* 261 * IO-bitmap sizes: 262 */ 263 #define IO_BITMAP_BITS 65536 264 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8) 265 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long)) 266 #define IO_BITMAP_OFFSET offsetof(struct tss_struct, io_bitmap) 267 #define INVALID_IO_BITMAP_OFFSET 0x8000 268 269 struct tss_struct { 270 /* 271 * The hardware state: 272 */ 273 struct x86_hw_tss x86_tss; 274 275 /* 276 * The extra 1 is there because the CPU will access an 277 * additional byte beyond the end of the IO permission 278 * bitmap. The extra byte must be all 1 bits, and must 279 * be within the limit. 280 */ 281 unsigned long io_bitmap[IO_BITMAP_LONGS + 1]; 282 283 /* 284 * .. and then another 0x100 bytes for the emergency kernel stack: 285 */ 286 unsigned long stack[64]; 287 288 } ____cacheline_aligned; 289 290 DECLARE_PER_CPU_SHARED_ALIGNED(struct tss_struct, init_tss); 291 292 /* 293 * Save the original ist values for checking stack pointers during debugging 294 */ 295 struct orig_ist { 296 unsigned long ist[7]; 297 }; 298 299 #define MXCSR_DEFAULT 0x1f80 300 301 struct i387_fsave_struct { 302 u32 cwd; /* FPU Control Word */ 303 u32 swd; /* FPU Status Word */ 304 u32 twd; /* FPU Tag Word */ 305 u32 fip; /* FPU IP Offset */ 306 u32 fcs; /* FPU IP Selector */ 307 u32 foo; /* FPU Operand Pointer Offset */ 308 u32 fos; /* FPU Operand Pointer Selector */ 309 310 /* 8*10 bytes for each FP-reg = 80 bytes: */ 311 u32 st_space[20]; 312 313 /* Software status information [not touched by FSAVE ]: */ 314 u32 status; 315 }; 316 317 struct i387_fxsave_struct { 318 u16 cwd; /* Control Word */ 319 u16 swd; /* Status Word */ 320 u16 twd; /* Tag Word */ 321 u16 fop; /* Last Instruction Opcode */ 322 union { 323 struct { 324 u64 rip; /* Instruction Pointer */ 325 u64 rdp; /* Data Pointer */ 326 }; 327 struct { 328 u32 fip; /* FPU IP Offset */ 329 u32 fcs; /* FPU IP Selector */ 330 u32 foo; /* FPU Operand Offset */ 331 u32 fos; /* FPU Operand Selector */ 332 }; 333 }; 334 u32 mxcsr; /* MXCSR Register State */ 335 u32 mxcsr_mask; /* MXCSR Mask */ 336 337 /* 8*16 bytes for each FP-reg = 128 bytes: */ 338 u32 st_space[32]; 339 340 /* 16*16 bytes for each XMM-reg = 256 bytes: */ 341 u32 xmm_space[64]; 342 343 u32 padding[12]; 344 345 union { 346 u32 padding1[12]; 347 u32 sw_reserved[12]; 348 }; 349 350 } __attribute__((aligned(16))); 351 352 struct i387_soft_struct { 353 u32 cwd; 354 u32 swd; 355 u32 twd; 356 u32 fip; 357 u32 fcs; 358 u32 foo; 359 u32 fos; 360 /* 8*10 bytes for each FP-reg = 80 bytes: */ 361 u32 st_space[20]; 362 u8 ftop; 363 u8 changed; 364 u8 lookahead; 365 u8 no_update; 366 u8 rm; 367 u8 alimit; 368 struct math_emu_info *info; 369 u32 entry_eip; 370 }; 371 372 struct ymmh_struct { 373 /* 16 * 16 bytes for each YMMH-reg = 256 bytes */ 374 u32 ymmh_space[64]; 375 }; 376 377 struct xsave_hdr_struct { 378 u64 xstate_bv; 379 u64 reserved1[2]; 380 u64 reserved2[5]; 381 } __attribute__((packed)); 382 383 struct xsave_struct { 384 struct i387_fxsave_struct i387; 385 struct xsave_hdr_struct xsave_hdr; 386 struct ymmh_struct ymmh; 387 /* new processor state extensions will go here */ 388 } __attribute__ ((packed, aligned (64))); 389 390 union thread_xstate { 391 struct i387_fsave_struct fsave; 392 struct i387_fxsave_struct fxsave; 393 struct i387_soft_struct soft; 394 struct xsave_struct xsave; 395 }; 396 397 struct fpu { 398 unsigned int last_cpu; 399 unsigned int has_fpu; 400 union thread_xstate *state; 401 }; 402 403 #ifdef CONFIG_X86_64 404 DECLARE_PER_CPU(struct orig_ist, orig_ist); 405 406 union irq_stack_union { 407 char irq_stack[IRQ_STACK_SIZE]; 408 /* 409 * GCC hardcodes the stack canary as %gs:40. Since the 410 * irq_stack is the object at %gs:0, we reserve the bottom 411 * 48 bytes of the irq stack for the canary. 412 */ 413 struct { 414 char gs_base[40]; 415 unsigned long stack_canary; 416 }; 417 }; 418 419 DECLARE_PER_CPU_FIRST(union irq_stack_union, irq_stack_union); 420 DECLARE_INIT_PER_CPU(irq_stack_union); 421 422 DECLARE_PER_CPU(char *, irq_stack_ptr); 423 DECLARE_PER_CPU(unsigned int, irq_count); 424 extern asmlinkage void ignore_sysret(void); 425 #else /* X86_64 */ 426 #ifdef CONFIG_CC_STACKPROTECTOR 427 /* 428 * Make sure stack canary segment base is cached-aligned: 429 * "For Intel Atom processors, avoid non zero segment base address 430 * that is not aligned to cache line boundary at all cost." 431 * (Optim Ref Manual Assembly/Compiler Coding Rule 15.) 432 */ 433 struct stack_canary { 434 char __pad[20]; /* canary at %gs:20 */ 435 unsigned long canary; 436 }; 437 DECLARE_PER_CPU_ALIGNED(struct stack_canary, stack_canary); 438 #endif 439 #endif /* X86_64 */ 440 441 extern unsigned int xstate_size; 442 extern void free_thread_xstate(struct task_struct *); 443 extern struct kmem_cache *task_xstate_cachep; 444 445 struct perf_event; 446 447 struct thread_struct { 448 /* Cached TLS descriptors: */ 449 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES]; 450 unsigned long sp0; 451 unsigned long sp; 452 #ifdef CONFIG_X86_32 453 unsigned long sysenter_cs; 454 #else 455 unsigned long usersp; /* Copy from PDA */ 456 unsigned short es; 457 unsigned short ds; 458 unsigned short fsindex; 459 unsigned short gsindex; 460 #endif 461 #ifdef CONFIG_X86_32 462 unsigned long ip; 463 #endif 464 #ifdef CONFIG_X86_64 465 unsigned long fs; 466 #endif 467 unsigned long gs; 468 /* Save middle states of ptrace breakpoints */ 469 struct perf_event *ptrace_bps[HBP_NUM]; 470 /* Debug status used for traps, single steps, etc... */ 471 unsigned long debugreg6; 472 /* Keep track of the exact dr7 value set by the user */ 473 unsigned long ptrace_dr7; 474 /* Fault info: */ 475 unsigned long cr2; 476 unsigned long trap_nr; 477 unsigned long error_code; 478 /* floating point and extended processor state */ 479 struct fpu fpu; 480 #ifdef CONFIG_X86_32 481 /* Virtual 86 mode info */ 482 struct vm86_struct __user *vm86_info; 483 unsigned long screen_bitmap; 484 unsigned long v86flags; 485 unsigned long v86mask; 486 unsigned long saved_sp0; 487 unsigned int saved_fs; 488 unsigned int saved_gs; 489 #endif 490 /* IO permissions: */ 491 unsigned long *io_bitmap_ptr; 492 unsigned long iopl; 493 /* Max allowed port in the bitmap, in bytes: */ 494 unsigned io_bitmap_max; 495 }; 496 497 /* 498 * Set IOPL bits in EFLAGS from given mask 499 */ 500 static inline void native_set_iopl_mask(unsigned mask) 501 { 502 #ifdef CONFIG_X86_32 503 unsigned int reg; 504 505 asm volatile ("pushfl;" 506 "popl %0;" 507 "andl %1, %0;" 508 "orl %2, %0;" 509 "pushl %0;" 510 "popfl" 511 : "=&r" (reg) 512 : "i" (~X86_EFLAGS_IOPL), "r" (mask)); 513 #endif 514 } 515 516 static inline void 517 native_load_sp0(struct tss_struct *tss, struct thread_struct *thread) 518 { 519 tss->x86_tss.sp0 = thread->sp0; 520 #ifdef CONFIG_X86_32 521 /* Only happens when SEP is enabled, no need to test "SEP"arately: */ 522 if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) { 523 tss->x86_tss.ss1 = thread->sysenter_cs; 524 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0); 525 } 526 #endif 527 } 528 529 static inline void native_swapgs(void) 530 { 531 #ifdef CONFIG_X86_64 532 asm volatile("swapgs" ::: "memory"); 533 #endif 534 } 535 536 #ifdef CONFIG_PARAVIRT 537 #include <asm/paravirt.h> 538 #else 539 #define __cpuid native_cpuid 540 #define paravirt_enabled() 0 541 542 static inline void load_sp0(struct tss_struct *tss, 543 struct thread_struct *thread) 544 { 545 native_load_sp0(tss, thread); 546 } 547 548 #define set_iopl_mask native_set_iopl_mask 549 #endif /* CONFIG_PARAVIRT */ 550 551 /* 552 * Save the cr4 feature set we're using (ie 553 * Pentium 4MB enable and PPro Global page 554 * enable), so that any CPU's that boot up 555 * after us can get the correct flags. 556 */ 557 extern unsigned long mmu_cr4_features; 558 extern u32 *trampoline_cr4_features; 559 560 static inline void set_in_cr4(unsigned long mask) 561 { 562 unsigned long cr4; 563 564 mmu_cr4_features |= mask; 565 if (trampoline_cr4_features) 566 *trampoline_cr4_features = mmu_cr4_features; 567 cr4 = read_cr4(); 568 cr4 |= mask; 569 write_cr4(cr4); 570 } 571 572 static inline void clear_in_cr4(unsigned long mask) 573 { 574 unsigned long cr4; 575 576 mmu_cr4_features &= ~mask; 577 if (trampoline_cr4_features) 578 *trampoline_cr4_features = mmu_cr4_features; 579 cr4 = read_cr4(); 580 cr4 &= ~mask; 581 write_cr4(cr4); 582 } 583 584 typedef struct { 585 unsigned long seg; 586 } mm_segment_t; 587 588 589 /* Free all resources held by a thread. */ 590 extern void release_thread(struct task_struct *); 591 592 unsigned long get_wchan(struct task_struct *p); 593 594 /* 595 * Generic CPUID function 596 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx 597 * resulting in stale register contents being returned. 598 */ 599 static inline void cpuid(unsigned int op, 600 unsigned int *eax, unsigned int *ebx, 601 unsigned int *ecx, unsigned int *edx) 602 { 603 *eax = op; 604 *ecx = 0; 605 __cpuid(eax, ebx, ecx, edx); 606 } 607 608 /* Some CPUID calls want 'count' to be placed in ecx */ 609 static inline void cpuid_count(unsigned int op, int count, 610 unsigned int *eax, unsigned int *ebx, 611 unsigned int *ecx, unsigned int *edx) 612 { 613 *eax = op; 614 *ecx = count; 615 __cpuid(eax, ebx, ecx, edx); 616 } 617 618 /* 619 * CPUID functions returning a single datum 620 */ 621 static inline unsigned int cpuid_eax(unsigned int op) 622 { 623 unsigned int eax, ebx, ecx, edx; 624 625 cpuid(op, &eax, &ebx, &ecx, &edx); 626 627 return eax; 628 } 629 630 static inline unsigned int cpuid_ebx(unsigned int op) 631 { 632 unsigned int eax, ebx, ecx, edx; 633 634 cpuid(op, &eax, &ebx, &ecx, &edx); 635 636 return ebx; 637 } 638 639 static inline unsigned int cpuid_ecx(unsigned int op) 640 { 641 unsigned int eax, ebx, ecx, edx; 642 643 cpuid(op, &eax, &ebx, &ecx, &edx); 644 645 return ecx; 646 } 647 648 static inline unsigned int cpuid_edx(unsigned int op) 649 { 650 unsigned int eax, ebx, ecx, edx; 651 652 cpuid(op, &eax, &ebx, &ecx, &edx); 653 654 return edx; 655 } 656 657 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */ 658 static inline void rep_nop(void) 659 { 660 asm volatile("rep; nop" ::: "memory"); 661 } 662 663 static inline void cpu_relax(void) 664 { 665 rep_nop(); 666 } 667 668 /* Stop speculative execution and prefetching of modified code. */ 669 static inline void sync_core(void) 670 { 671 int tmp; 672 673 #ifdef CONFIG_M486 674 /* 675 * Do a CPUID if available, otherwise do a jump. The jump 676 * can conveniently enough be the jump around CPUID. 677 */ 678 asm volatile("cmpl %2,%1\n\t" 679 "jl 1f\n\t" 680 "cpuid\n" 681 "1:" 682 : "=a" (tmp) 683 : "rm" (boot_cpu_data.cpuid_level), "ri" (0), "0" (1) 684 : "ebx", "ecx", "edx", "memory"); 685 #else 686 /* 687 * CPUID is a barrier to speculative execution. 688 * Prefetched instructions are automatically 689 * invalidated when modified. 690 */ 691 asm volatile("cpuid" 692 : "=a" (tmp) 693 : "0" (1) 694 : "ebx", "ecx", "edx", "memory"); 695 #endif 696 } 697 698 static inline void __monitor(const void *eax, unsigned long ecx, 699 unsigned long edx) 700 { 701 /* "monitor %eax, %ecx, %edx;" */ 702 asm volatile(".byte 0x0f, 0x01, 0xc8;" 703 :: "a" (eax), "c" (ecx), "d"(edx)); 704 } 705 706 static inline void __mwait(unsigned long eax, unsigned long ecx) 707 { 708 /* "mwait %eax, %ecx;" */ 709 asm volatile(".byte 0x0f, 0x01, 0xc9;" 710 :: "a" (eax), "c" (ecx)); 711 } 712 713 static inline void __sti_mwait(unsigned long eax, unsigned long ecx) 714 { 715 trace_hardirqs_on(); 716 /* "mwait %eax, %ecx;" */ 717 asm volatile("sti; .byte 0x0f, 0x01, 0xc9;" 718 :: "a" (eax), "c" (ecx)); 719 } 720 721 extern void select_idle_routine(const struct cpuinfo_x86 *c); 722 extern void init_amd_e400_c1e_mask(void); 723 724 extern unsigned long boot_option_idle_override; 725 extern bool amd_e400_c1e_detected; 726 727 enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_NOMWAIT, 728 IDLE_POLL, IDLE_FORCE_MWAIT}; 729 730 extern void enable_sep_cpu(void); 731 extern int sysenter_setup(void); 732 733 extern void early_trap_init(void); 734 735 /* Defined in head.S */ 736 extern struct desc_ptr early_gdt_descr; 737 738 extern void cpu_set_gdt(int); 739 extern void switch_to_new_gdt(int); 740 extern void load_percpu_segment(int); 741 extern void cpu_init(void); 742 743 static inline unsigned long get_debugctlmsr(void) 744 { 745 unsigned long debugctlmsr = 0; 746 747 #ifndef CONFIG_X86_DEBUGCTLMSR 748 if (boot_cpu_data.x86 < 6) 749 return 0; 750 #endif 751 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr); 752 753 return debugctlmsr; 754 } 755 756 static inline void update_debugctlmsr(unsigned long debugctlmsr) 757 { 758 #ifndef CONFIG_X86_DEBUGCTLMSR 759 if (boot_cpu_data.x86 < 6) 760 return; 761 #endif 762 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr); 763 } 764 765 extern void set_task_blockstep(struct task_struct *task, bool on); 766 767 /* 768 * from system description table in BIOS. Mostly for MCA use, but 769 * others may find it useful: 770 */ 771 extern unsigned int machine_id; 772 extern unsigned int machine_submodel_id; 773 extern unsigned int BIOS_revision; 774 775 /* Boot loader type from the setup header: */ 776 extern int bootloader_type; 777 extern int bootloader_version; 778 779 extern char ignore_fpu_irq; 780 781 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1 782 #define ARCH_HAS_PREFETCHW 783 #define ARCH_HAS_SPINLOCK_PREFETCH 784 785 #ifdef CONFIG_X86_32 786 # define BASE_PREFETCH ASM_NOP4 787 # define ARCH_HAS_PREFETCH 788 #else 789 # define BASE_PREFETCH "prefetcht0 (%1)" 790 #endif 791 792 /* 793 * Prefetch instructions for Pentium III (+) and AMD Athlon (+) 794 * 795 * It's not worth to care about 3dnow prefetches for the K6 796 * because they are microcoded there and very slow. 797 */ 798 static inline void prefetch(const void *x) 799 { 800 alternative_input(BASE_PREFETCH, 801 "prefetchnta (%1)", 802 X86_FEATURE_XMM, 803 "r" (x)); 804 } 805 806 /* 807 * 3dnow prefetch to get an exclusive cache line. 808 * Useful for spinlocks to avoid one state transition in the 809 * cache coherency protocol: 810 */ 811 static inline void prefetchw(const void *x) 812 { 813 alternative_input(BASE_PREFETCH, 814 "prefetchw (%1)", 815 X86_FEATURE_3DNOW, 816 "r" (x)); 817 } 818 819 static inline void spin_lock_prefetch(const void *x) 820 { 821 prefetchw(x); 822 } 823 824 #ifdef CONFIG_X86_32 825 /* 826 * User space process size: 3GB (default). 827 */ 828 #define TASK_SIZE PAGE_OFFSET 829 #define TASK_SIZE_MAX TASK_SIZE 830 #define STACK_TOP TASK_SIZE 831 #define STACK_TOP_MAX STACK_TOP 832 833 #define INIT_THREAD { \ 834 .sp0 = sizeof(init_stack) + (long)&init_stack, \ 835 .vm86_info = NULL, \ 836 .sysenter_cs = __KERNEL_CS, \ 837 .io_bitmap_ptr = NULL, \ 838 } 839 840 /* 841 * Note that the .io_bitmap member must be extra-big. This is because 842 * the CPU will access an additional byte beyond the end of the IO 843 * permission bitmap. The extra byte must be all 1 bits, and must 844 * be within the limit. 845 */ 846 #define INIT_TSS { \ 847 .x86_tss = { \ 848 .sp0 = sizeof(init_stack) + (long)&init_stack, \ 849 .ss0 = __KERNEL_DS, \ 850 .ss1 = __KERNEL_CS, \ 851 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, \ 852 }, \ 853 .io_bitmap = { [0 ... IO_BITMAP_LONGS] = ~0 }, \ 854 } 855 856 extern unsigned long thread_saved_pc(struct task_struct *tsk); 857 858 #define THREAD_SIZE_LONGS (THREAD_SIZE/sizeof(unsigned long)) 859 #define KSTK_TOP(info) \ 860 ({ \ 861 unsigned long *__ptr = (unsigned long *)(info); \ 862 (unsigned long)(&__ptr[THREAD_SIZE_LONGS]); \ 863 }) 864 865 /* 866 * The below -8 is to reserve 8 bytes on top of the ring0 stack. 867 * This is necessary to guarantee that the entire "struct pt_regs" 868 * is accessible even if the CPU haven't stored the SS/ESP registers 869 * on the stack (interrupt gate does not save these registers 870 * when switching to the same priv ring). 871 * Therefore beware: accessing the ss/esp fields of the 872 * "struct pt_regs" is possible, but they may contain the 873 * completely wrong values. 874 */ 875 #define task_pt_regs(task) \ 876 ({ \ 877 struct pt_regs *__regs__; \ 878 __regs__ = (struct pt_regs *)(KSTK_TOP(task_stack_page(task))-8); \ 879 __regs__ - 1; \ 880 }) 881 882 #define KSTK_ESP(task) (task_pt_regs(task)->sp) 883 884 #else 885 /* 886 * User space process size. 47bits minus one guard page. 887 */ 888 #define TASK_SIZE_MAX ((1UL << 47) - PAGE_SIZE) 889 890 /* This decides where the kernel will search for a free chunk of vm 891 * space during mmap's. 892 */ 893 #define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? \ 894 0xc0000000 : 0xFFFFe000) 895 896 #define TASK_SIZE (test_thread_flag(TIF_ADDR32) ? \ 897 IA32_PAGE_OFFSET : TASK_SIZE_MAX) 898 #define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_ADDR32)) ? \ 899 IA32_PAGE_OFFSET : TASK_SIZE_MAX) 900 901 #define STACK_TOP TASK_SIZE 902 #define STACK_TOP_MAX TASK_SIZE_MAX 903 904 #define INIT_THREAD { \ 905 .sp0 = (unsigned long)&init_stack + sizeof(init_stack) \ 906 } 907 908 #define INIT_TSS { \ 909 .x86_tss.sp0 = (unsigned long)&init_stack + sizeof(init_stack) \ 910 } 911 912 /* 913 * Return saved PC of a blocked thread. 914 * What is this good for? it will be always the scheduler or ret_from_fork. 915 */ 916 #define thread_saved_pc(t) (*(unsigned long *)((t)->thread.sp - 8)) 917 918 #define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.sp0 - 1) 919 extern unsigned long KSTK_ESP(struct task_struct *task); 920 921 /* 922 * User space RSP while inside the SYSCALL fast path 923 */ 924 DECLARE_PER_CPU(unsigned long, old_rsp); 925 926 #endif /* CONFIG_X86_64 */ 927 928 extern void start_thread(struct pt_regs *regs, unsigned long new_ip, 929 unsigned long new_sp); 930 931 /* 932 * This decides where the kernel will search for a free chunk of vm 933 * space during mmap's. 934 */ 935 #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3)) 936 937 #define KSTK_EIP(task) (task_pt_regs(task)->ip) 938 939 /* Get/set a process' ability to use the timestamp counter instruction */ 940 #define GET_TSC_CTL(adr) get_tsc_mode((adr)) 941 #define SET_TSC_CTL(val) set_tsc_mode((val)) 942 943 extern int get_tsc_mode(unsigned long adr); 944 extern int set_tsc_mode(unsigned int val); 945 946 extern int amd_get_nb_id(int cpu); 947 948 struct aperfmperf { 949 u64 aperf, mperf; 950 }; 951 952 static inline void get_aperfmperf(struct aperfmperf *am) 953 { 954 WARN_ON_ONCE(!boot_cpu_has(X86_FEATURE_APERFMPERF)); 955 956 rdmsrl(MSR_IA32_APERF, am->aperf); 957 rdmsrl(MSR_IA32_MPERF, am->mperf); 958 } 959 960 #define APERFMPERF_SHIFT 10 961 962 static inline 963 unsigned long calc_aperfmperf_ratio(struct aperfmperf *old, 964 struct aperfmperf *new) 965 { 966 u64 aperf = new->aperf - old->aperf; 967 u64 mperf = new->mperf - old->mperf; 968 unsigned long ratio = aperf; 969 970 mperf >>= APERFMPERF_SHIFT; 971 if (mperf) 972 ratio = div64_u64(aperf, mperf); 973 974 return ratio; 975 } 976 977 /* 978 * AMD errata checking 979 */ 980 #ifdef CONFIG_CPU_SUP_AMD 981 extern const int amd_erratum_383[]; 982 extern const int amd_erratum_400[]; 983 extern bool cpu_has_amd_erratum(const int *); 984 985 #define AMD_LEGACY_ERRATUM(...) { -1, __VA_ARGS__, 0 } 986 #define AMD_OSVW_ERRATUM(osvw_id, ...) { osvw_id, __VA_ARGS__, 0 } 987 #define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \ 988 ((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end)) 989 #define AMD_MODEL_RANGE_FAMILY(range) (((range) >> 24) & 0xff) 990 #define AMD_MODEL_RANGE_START(range) (((range) >> 12) & 0xfff) 991 #define AMD_MODEL_RANGE_END(range) ((range) & 0xfff) 992 993 #else 994 #define cpu_has_amd_erratum(x) (false) 995 #endif /* CONFIG_CPU_SUP_AMD */ 996 997 extern unsigned long arch_align_stack(unsigned long sp); 998 extern void free_init_pages(char *what, unsigned long begin, unsigned long end); 999 1000 void default_idle(void); 1001 bool set_pm_idle_to_default(void); 1002 1003 void stop_this_cpu(void *dummy); 1004 1005 #endif /* _ASM_X86_PROCESSOR_H */ 1006