1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _ASM_X86_PROCESSOR_H 3 #define _ASM_X86_PROCESSOR_H 4 5 #include <asm/processor-flags.h> 6 7 /* Forward declaration, a strange C thing */ 8 struct task_struct; 9 struct mm_struct; 10 struct vm86; 11 12 #include <asm/math_emu.h> 13 #include <asm/segment.h> 14 #include <asm/types.h> 15 #include <uapi/asm/sigcontext.h> 16 #include <asm/current.h> 17 #include <asm/cpufeatures.h> 18 #include <asm/page.h> 19 #include <asm/pgtable_types.h> 20 #include <asm/percpu.h> 21 #include <asm/msr.h> 22 #include <asm/desc_defs.h> 23 #include <asm/nops.h> 24 #include <asm/special_insns.h> 25 #include <asm/fpu/types.h> 26 #include <asm/unwind_hints.h> 27 28 #include <linux/personality.h> 29 #include <linux/cache.h> 30 #include <linux/threads.h> 31 #include <linux/math64.h> 32 #include <linux/err.h> 33 #include <linux/irqflags.h> 34 #include <linux/mem_encrypt.h> 35 36 /* 37 * We handle most unaligned accesses in hardware. On the other hand 38 * unaligned DMA can be quite expensive on some Nehalem processors. 39 * 40 * Based on this we disable the IP header alignment in network drivers. 41 */ 42 #define NET_IP_ALIGN 0 43 44 #define HBP_NUM 4 45 46 /* 47 * These alignment constraints are for performance in the vSMP case, 48 * but in the task_struct case we must also meet hardware imposed 49 * alignment requirements of the FPU state: 50 */ 51 #ifdef CONFIG_X86_VSMP 52 # define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT) 53 # define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT) 54 #else 55 # define ARCH_MIN_TASKALIGN __alignof__(union fpregs_state) 56 # define ARCH_MIN_MMSTRUCT_ALIGN 0 57 #endif 58 59 enum tlb_infos { 60 ENTRIES, 61 NR_INFO 62 }; 63 64 extern u16 __read_mostly tlb_lli_4k[NR_INFO]; 65 extern u16 __read_mostly tlb_lli_2m[NR_INFO]; 66 extern u16 __read_mostly tlb_lli_4m[NR_INFO]; 67 extern u16 __read_mostly tlb_lld_4k[NR_INFO]; 68 extern u16 __read_mostly tlb_lld_2m[NR_INFO]; 69 extern u16 __read_mostly tlb_lld_4m[NR_INFO]; 70 extern u16 __read_mostly tlb_lld_1g[NR_INFO]; 71 72 /* 73 * CPU type and hardware bug flags. Kept separately for each CPU. 74 * Members of this structure are referenced in head_32.S, so think twice 75 * before touching them. [mj] 76 */ 77 78 struct cpuinfo_x86 { 79 __u8 x86; /* CPU family */ 80 __u8 x86_vendor; /* CPU vendor */ 81 __u8 x86_model; 82 __u8 x86_stepping; 83 #ifdef CONFIG_X86_64 84 /* Number of 4K pages in DTLB/ITLB combined(in pages): */ 85 int x86_tlbsize; 86 #endif 87 __u8 x86_virt_bits; 88 __u8 x86_phys_bits; 89 /* CPUID returned core id bits: */ 90 __u8 x86_coreid_bits; 91 __u8 cu_id; 92 /* Max extended CPUID function supported: */ 93 __u32 extended_cpuid_level; 94 /* Maximum supported CPUID level, -1=no CPUID: */ 95 int cpuid_level; 96 __u32 x86_capability[NCAPINTS + NBUGINTS]; 97 char x86_vendor_id[16]; 98 char x86_model_id[64]; 99 /* in KB - valid for CPUS which support this call: */ 100 unsigned int x86_cache_size; 101 int x86_cache_alignment; /* In bytes */ 102 /* Cache QoS architectural values: */ 103 int x86_cache_max_rmid; /* max index */ 104 int x86_cache_occ_scale; /* scale to bytes */ 105 int x86_power; 106 unsigned long loops_per_jiffy; 107 /* cpuid returned max cores value: */ 108 u16 x86_max_cores; 109 u16 apicid; 110 u16 initial_apicid; 111 u16 x86_clflush_size; 112 /* number of cores as seen by the OS: */ 113 u16 booted_cores; 114 /* Physical processor id: */ 115 u16 phys_proc_id; 116 /* Logical processor id: */ 117 u16 logical_proc_id; 118 /* Core id: */ 119 u16 cpu_core_id; 120 /* Index into per_cpu list: */ 121 u16 cpu_index; 122 u32 microcode; 123 /* Address space bits used by the cache internally */ 124 u8 x86_cache_bits; 125 unsigned initialized : 1; 126 } __randomize_layout; 127 128 struct cpuid_regs { 129 u32 eax, ebx, ecx, edx; 130 }; 131 132 enum cpuid_regs_idx { 133 CPUID_EAX = 0, 134 CPUID_EBX, 135 CPUID_ECX, 136 CPUID_EDX, 137 }; 138 139 #define X86_VENDOR_INTEL 0 140 #define X86_VENDOR_CYRIX 1 141 #define X86_VENDOR_AMD 2 142 #define X86_VENDOR_UMC 3 143 #define X86_VENDOR_CENTAUR 5 144 #define X86_VENDOR_TRANSMETA 7 145 #define X86_VENDOR_NSC 8 146 #define X86_VENDOR_HYGON 9 147 #define X86_VENDOR_NUM 10 148 149 #define X86_VENDOR_UNKNOWN 0xff 150 151 /* 152 * capabilities of CPUs 153 */ 154 extern struct cpuinfo_x86 boot_cpu_data; 155 extern struct cpuinfo_x86 new_cpu_data; 156 157 extern struct x86_hw_tss doublefault_tss; 158 extern __u32 cpu_caps_cleared[NCAPINTS + NBUGINTS]; 159 extern __u32 cpu_caps_set[NCAPINTS + NBUGINTS]; 160 161 #ifdef CONFIG_SMP 162 DECLARE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info); 163 #define cpu_data(cpu) per_cpu(cpu_info, cpu) 164 #else 165 #define cpu_info boot_cpu_data 166 #define cpu_data(cpu) boot_cpu_data 167 #endif 168 169 extern const struct seq_operations cpuinfo_op; 170 171 #define cache_line_size() (boot_cpu_data.x86_cache_alignment) 172 173 extern void cpu_detect(struct cpuinfo_x86 *c); 174 175 static inline unsigned long long l1tf_pfn_limit(void) 176 { 177 return BIT_ULL(boot_cpu_data.x86_cache_bits - 1 - PAGE_SHIFT); 178 } 179 180 extern void early_cpu_init(void); 181 extern void identify_boot_cpu(void); 182 extern void identify_secondary_cpu(struct cpuinfo_x86 *); 183 extern void print_cpu_info(struct cpuinfo_x86 *); 184 void print_cpu_msr(struct cpuinfo_x86 *); 185 186 #ifdef CONFIG_X86_32 187 extern int have_cpuid_p(void); 188 #else 189 static inline int have_cpuid_p(void) 190 { 191 return 1; 192 } 193 #endif 194 static inline void native_cpuid(unsigned int *eax, unsigned int *ebx, 195 unsigned int *ecx, unsigned int *edx) 196 { 197 /* ecx is often an input as well as an output. */ 198 asm volatile("cpuid" 199 : "=a" (*eax), 200 "=b" (*ebx), 201 "=c" (*ecx), 202 "=d" (*edx) 203 : "0" (*eax), "2" (*ecx) 204 : "memory"); 205 } 206 207 #define native_cpuid_reg(reg) \ 208 static inline unsigned int native_cpuid_##reg(unsigned int op) \ 209 { \ 210 unsigned int eax = op, ebx, ecx = 0, edx; \ 211 \ 212 native_cpuid(&eax, &ebx, &ecx, &edx); \ 213 \ 214 return reg; \ 215 } 216 217 /* 218 * Native CPUID functions returning a single datum. 219 */ 220 native_cpuid_reg(eax) 221 native_cpuid_reg(ebx) 222 native_cpuid_reg(ecx) 223 native_cpuid_reg(edx) 224 225 /* 226 * Friendlier CR3 helpers. 227 */ 228 static inline unsigned long read_cr3_pa(void) 229 { 230 return __read_cr3() & CR3_ADDR_MASK; 231 } 232 233 static inline unsigned long native_read_cr3_pa(void) 234 { 235 return __native_read_cr3() & CR3_ADDR_MASK; 236 } 237 238 static inline void load_cr3(pgd_t *pgdir) 239 { 240 write_cr3(__sme_pa(pgdir)); 241 } 242 243 /* 244 * Note that while the legacy 'TSS' name comes from 'Task State Segment', 245 * on modern x86 CPUs the TSS also holds information important to 64-bit mode, 246 * unrelated to the task-switch mechanism: 247 */ 248 #ifdef CONFIG_X86_32 249 /* This is the TSS defined by the hardware. */ 250 struct x86_hw_tss { 251 unsigned short back_link, __blh; 252 unsigned long sp0; 253 unsigned short ss0, __ss0h; 254 unsigned long sp1; 255 256 /* 257 * We don't use ring 1, so ss1 is a convenient scratch space in 258 * the same cacheline as sp0. We use ss1 to cache the value in 259 * MSR_IA32_SYSENTER_CS. When we context switch 260 * MSR_IA32_SYSENTER_CS, we first check if the new value being 261 * written matches ss1, and, if it's not, then we wrmsr the new 262 * value and update ss1. 263 * 264 * The only reason we context switch MSR_IA32_SYSENTER_CS is 265 * that we set it to zero in vm86 tasks to avoid corrupting the 266 * stack if we were to go through the sysenter path from vm86 267 * mode. 268 */ 269 unsigned short ss1; /* MSR_IA32_SYSENTER_CS */ 270 271 unsigned short __ss1h; 272 unsigned long sp2; 273 unsigned short ss2, __ss2h; 274 unsigned long __cr3; 275 unsigned long ip; 276 unsigned long flags; 277 unsigned long ax; 278 unsigned long cx; 279 unsigned long dx; 280 unsigned long bx; 281 unsigned long sp; 282 unsigned long bp; 283 unsigned long si; 284 unsigned long di; 285 unsigned short es, __esh; 286 unsigned short cs, __csh; 287 unsigned short ss, __ssh; 288 unsigned short ds, __dsh; 289 unsigned short fs, __fsh; 290 unsigned short gs, __gsh; 291 unsigned short ldt, __ldth; 292 unsigned short trace; 293 unsigned short io_bitmap_base; 294 295 } __attribute__((packed)); 296 #else 297 struct x86_hw_tss { 298 u32 reserved1; 299 u64 sp0; 300 301 /* 302 * We store cpu_current_top_of_stack in sp1 so it's always accessible. 303 * Linux does not use ring 1, so sp1 is not otherwise needed. 304 */ 305 u64 sp1; 306 307 /* 308 * Since Linux does not use ring 2, the 'sp2' slot is unused by 309 * hardware. entry_SYSCALL_64 uses it as scratch space to stash 310 * the user RSP value. 311 */ 312 u64 sp2; 313 314 u64 reserved2; 315 u64 ist[7]; 316 u32 reserved3; 317 u32 reserved4; 318 u16 reserved5; 319 u16 io_bitmap_base; 320 321 } __attribute__((packed)); 322 #endif 323 324 /* 325 * IO-bitmap sizes: 326 */ 327 #define IO_BITMAP_BITS 65536 328 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8) 329 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long)) 330 #define IO_BITMAP_OFFSET (offsetof(struct tss_struct, io_bitmap) - offsetof(struct tss_struct, x86_tss)) 331 #define INVALID_IO_BITMAP_OFFSET 0x8000 332 333 struct entry_stack { 334 unsigned long words[64]; 335 }; 336 337 struct entry_stack_page { 338 struct entry_stack stack; 339 } __aligned(PAGE_SIZE); 340 341 struct tss_struct { 342 /* 343 * The fixed hardware portion. This must not cross a page boundary 344 * at risk of violating the SDM's advice and potentially triggering 345 * errata. 346 */ 347 struct x86_hw_tss x86_tss; 348 349 /* 350 * The extra 1 is there because the CPU will access an 351 * additional byte beyond the end of the IO permission 352 * bitmap. The extra byte must be all 1 bits, and must 353 * be within the limit. 354 */ 355 unsigned long io_bitmap[IO_BITMAP_LONGS + 1]; 356 } __aligned(PAGE_SIZE); 357 358 DECLARE_PER_CPU_PAGE_ALIGNED(struct tss_struct, cpu_tss_rw); 359 360 /* 361 * sizeof(unsigned long) coming from an extra "long" at the end 362 * of the iobitmap. 363 * 364 * -1? seg base+limit should be pointing to the address of the 365 * last valid byte 366 */ 367 #define __KERNEL_TSS_LIMIT \ 368 (IO_BITMAP_OFFSET + IO_BITMAP_BYTES + sizeof(unsigned long) - 1) 369 370 #ifdef CONFIG_X86_32 371 DECLARE_PER_CPU(unsigned long, cpu_current_top_of_stack); 372 #else 373 /* The RO copy can't be accessed with this_cpu_xyz(), so use the RW copy. */ 374 #define cpu_current_top_of_stack cpu_tss_rw.x86_tss.sp1 375 #endif 376 377 /* 378 * Save the original ist values for checking stack pointers during debugging 379 */ 380 struct orig_ist { 381 unsigned long ist[7]; 382 }; 383 384 #ifdef CONFIG_X86_64 385 DECLARE_PER_CPU(struct orig_ist, orig_ist); 386 387 union irq_stack_union { 388 char irq_stack[IRQ_STACK_SIZE]; 389 /* 390 * GCC hardcodes the stack canary as %gs:40. Since the 391 * irq_stack is the object at %gs:0, we reserve the bottom 392 * 48 bytes of the irq stack for the canary. 393 */ 394 struct { 395 char gs_base[40]; 396 unsigned long stack_canary; 397 }; 398 }; 399 400 DECLARE_PER_CPU_FIRST(union irq_stack_union, irq_stack_union) __visible; 401 DECLARE_INIT_PER_CPU(irq_stack_union); 402 403 static inline unsigned long cpu_kernelmode_gs_base(int cpu) 404 { 405 return (unsigned long)per_cpu(irq_stack_union.gs_base, cpu); 406 } 407 408 DECLARE_PER_CPU(char *, irq_stack_ptr); 409 DECLARE_PER_CPU(unsigned int, irq_count); 410 extern asmlinkage void ignore_sysret(void); 411 412 #if IS_ENABLED(CONFIG_KVM) 413 /* Save actual FS/GS selectors and bases to current->thread */ 414 void save_fsgs_for_kvm(void); 415 #endif 416 #else /* X86_64 */ 417 #ifdef CONFIG_STACKPROTECTOR 418 /* 419 * Make sure stack canary segment base is cached-aligned: 420 * "For Intel Atom processors, avoid non zero segment base address 421 * that is not aligned to cache line boundary at all cost." 422 * (Optim Ref Manual Assembly/Compiler Coding Rule 15.) 423 */ 424 struct stack_canary { 425 char __pad[20]; /* canary at %gs:20 */ 426 unsigned long canary; 427 }; 428 DECLARE_PER_CPU_ALIGNED(struct stack_canary, stack_canary); 429 #endif 430 /* 431 * per-CPU IRQ handling stacks 432 */ 433 struct irq_stack { 434 u32 stack[THREAD_SIZE/sizeof(u32)]; 435 } __aligned(THREAD_SIZE); 436 437 DECLARE_PER_CPU(struct irq_stack *, hardirq_stack); 438 DECLARE_PER_CPU(struct irq_stack *, softirq_stack); 439 #endif /* X86_64 */ 440 441 extern unsigned int fpu_kernel_xstate_size; 442 extern unsigned int fpu_user_xstate_size; 443 444 struct perf_event; 445 446 typedef struct { 447 unsigned long seg; 448 } mm_segment_t; 449 450 struct thread_struct { 451 /* Cached TLS descriptors: */ 452 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES]; 453 #ifdef CONFIG_X86_32 454 unsigned long sp0; 455 #endif 456 unsigned long sp; 457 #ifdef CONFIG_X86_32 458 unsigned long sysenter_cs; 459 #else 460 unsigned short es; 461 unsigned short ds; 462 unsigned short fsindex; 463 unsigned short gsindex; 464 #endif 465 466 #ifdef CONFIG_X86_64 467 unsigned long fsbase; 468 unsigned long gsbase; 469 #else 470 /* 471 * XXX: this could presumably be unsigned short. Alternatively, 472 * 32-bit kernels could be taught to use fsindex instead. 473 */ 474 unsigned long fs; 475 unsigned long gs; 476 #endif 477 478 /* Save middle states of ptrace breakpoints */ 479 struct perf_event *ptrace_bps[HBP_NUM]; 480 /* Debug status used for traps, single steps, etc... */ 481 unsigned long debugreg6; 482 /* Keep track of the exact dr7 value set by the user */ 483 unsigned long ptrace_dr7; 484 /* Fault info: */ 485 unsigned long cr2; 486 unsigned long trap_nr; 487 unsigned long error_code; 488 #ifdef CONFIG_VM86 489 /* Virtual 86 mode info */ 490 struct vm86 *vm86; 491 #endif 492 /* IO permissions: */ 493 unsigned long *io_bitmap_ptr; 494 unsigned long iopl; 495 /* Max allowed port in the bitmap, in bytes: */ 496 unsigned io_bitmap_max; 497 498 mm_segment_t addr_limit; 499 500 unsigned int sig_on_uaccess_err:1; 501 unsigned int uaccess_err:1; /* uaccess failed */ 502 503 /* Floating point and extended processor state */ 504 struct fpu fpu; 505 /* 506 * WARNING: 'fpu' is dynamically-sized. It *MUST* be at 507 * the end. 508 */ 509 }; 510 511 /* Whitelist the FPU state from the task_struct for hardened usercopy. */ 512 static inline void arch_thread_struct_whitelist(unsigned long *offset, 513 unsigned long *size) 514 { 515 *offset = offsetof(struct thread_struct, fpu.state); 516 *size = fpu_kernel_xstate_size; 517 } 518 519 /* 520 * Thread-synchronous status. 521 * 522 * This is different from the flags in that nobody else 523 * ever touches our thread-synchronous status, so we don't 524 * have to worry about atomic accesses. 525 */ 526 #define TS_COMPAT 0x0002 /* 32bit syscall active (64BIT)*/ 527 528 /* 529 * Set IOPL bits in EFLAGS from given mask 530 */ 531 static inline void native_set_iopl_mask(unsigned mask) 532 { 533 #ifdef CONFIG_X86_32 534 unsigned int reg; 535 536 asm volatile ("pushfl;" 537 "popl %0;" 538 "andl %1, %0;" 539 "orl %2, %0;" 540 "pushl %0;" 541 "popfl" 542 : "=&r" (reg) 543 : "i" (~X86_EFLAGS_IOPL), "r" (mask)); 544 #endif 545 } 546 547 static inline void 548 native_load_sp0(unsigned long sp0) 549 { 550 this_cpu_write(cpu_tss_rw.x86_tss.sp0, sp0); 551 } 552 553 static inline void native_swapgs(void) 554 { 555 #ifdef CONFIG_X86_64 556 asm volatile("swapgs" ::: "memory"); 557 #endif 558 } 559 560 static inline unsigned long current_top_of_stack(void) 561 { 562 /* 563 * We can't read directly from tss.sp0: sp0 on x86_32 is special in 564 * and around vm86 mode and sp0 on x86_64 is special because of the 565 * entry trampoline. 566 */ 567 return this_cpu_read_stable(cpu_current_top_of_stack); 568 } 569 570 static inline bool on_thread_stack(void) 571 { 572 return (unsigned long)(current_top_of_stack() - 573 current_stack_pointer) < THREAD_SIZE; 574 } 575 576 #ifdef CONFIG_PARAVIRT_XXL 577 #include <asm/paravirt.h> 578 #else 579 #define __cpuid native_cpuid 580 581 static inline void load_sp0(unsigned long sp0) 582 { 583 native_load_sp0(sp0); 584 } 585 586 #define set_iopl_mask native_set_iopl_mask 587 #endif /* CONFIG_PARAVIRT_XXL */ 588 589 /* Free all resources held by a thread. */ 590 extern void release_thread(struct task_struct *); 591 592 unsigned long get_wchan(struct task_struct *p); 593 594 /* 595 * Generic CPUID function 596 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx 597 * resulting in stale register contents being returned. 598 */ 599 static inline void cpuid(unsigned int op, 600 unsigned int *eax, unsigned int *ebx, 601 unsigned int *ecx, unsigned int *edx) 602 { 603 *eax = op; 604 *ecx = 0; 605 __cpuid(eax, ebx, ecx, edx); 606 } 607 608 /* Some CPUID calls want 'count' to be placed in ecx */ 609 static inline void cpuid_count(unsigned int op, int count, 610 unsigned int *eax, unsigned int *ebx, 611 unsigned int *ecx, unsigned int *edx) 612 { 613 *eax = op; 614 *ecx = count; 615 __cpuid(eax, ebx, ecx, edx); 616 } 617 618 /* 619 * CPUID functions returning a single datum 620 */ 621 static inline unsigned int cpuid_eax(unsigned int op) 622 { 623 unsigned int eax, ebx, ecx, edx; 624 625 cpuid(op, &eax, &ebx, &ecx, &edx); 626 627 return eax; 628 } 629 630 static inline unsigned int cpuid_ebx(unsigned int op) 631 { 632 unsigned int eax, ebx, ecx, edx; 633 634 cpuid(op, &eax, &ebx, &ecx, &edx); 635 636 return ebx; 637 } 638 639 static inline unsigned int cpuid_ecx(unsigned int op) 640 { 641 unsigned int eax, ebx, ecx, edx; 642 643 cpuid(op, &eax, &ebx, &ecx, &edx); 644 645 return ecx; 646 } 647 648 static inline unsigned int cpuid_edx(unsigned int op) 649 { 650 unsigned int eax, ebx, ecx, edx; 651 652 cpuid(op, &eax, &ebx, &ecx, &edx); 653 654 return edx; 655 } 656 657 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */ 658 static __always_inline void rep_nop(void) 659 { 660 asm volatile("rep; nop" ::: "memory"); 661 } 662 663 static __always_inline void cpu_relax(void) 664 { 665 rep_nop(); 666 } 667 668 /* 669 * This function forces the icache and prefetched instruction stream to 670 * catch up with reality in two very specific cases: 671 * 672 * a) Text was modified using one virtual address and is about to be executed 673 * from the same physical page at a different virtual address. 674 * 675 * b) Text was modified on a different CPU, may subsequently be 676 * executed on this CPU, and you want to make sure the new version 677 * gets executed. This generally means you're calling this in a IPI. 678 * 679 * If you're calling this for a different reason, you're probably doing 680 * it wrong. 681 */ 682 static inline void sync_core(void) 683 { 684 /* 685 * There are quite a few ways to do this. IRET-to-self is nice 686 * because it works on every CPU, at any CPL (so it's compatible 687 * with paravirtualization), and it never exits to a hypervisor. 688 * The only down sides are that it's a bit slow (it seems to be 689 * a bit more than 2x slower than the fastest options) and that 690 * it unmasks NMIs. The "push %cs" is needed because, in 691 * paravirtual environments, __KERNEL_CS may not be a valid CS 692 * value when we do IRET directly. 693 * 694 * In case NMI unmasking or performance ever becomes a problem, 695 * the next best option appears to be MOV-to-CR2 and an 696 * unconditional jump. That sequence also works on all CPUs, 697 * but it will fault at CPL3 (i.e. Xen PV). 698 * 699 * CPUID is the conventional way, but it's nasty: it doesn't 700 * exist on some 486-like CPUs, and it usually exits to a 701 * hypervisor. 702 * 703 * Like all of Linux's memory ordering operations, this is a 704 * compiler barrier as well. 705 */ 706 #ifdef CONFIG_X86_32 707 asm volatile ( 708 "pushfl\n\t" 709 "pushl %%cs\n\t" 710 "pushl $1f\n\t" 711 "iret\n\t" 712 "1:" 713 : ASM_CALL_CONSTRAINT : : "memory"); 714 #else 715 unsigned int tmp; 716 717 asm volatile ( 718 UNWIND_HINT_SAVE 719 "mov %%ss, %0\n\t" 720 "pushq %q0\n\t" 721 "pushq %%rsp\n\t" 722 "addq $8, (%%rsp)\n\t" 723 "pushfq\n\t" 724 "mov %%cs, %0\n\t" 725 "pushq %q0\n\t" 726 "pushq $1f\n\t" 727 "iretq\n\t" 728 UNWIND_HINT_RESTORE 729 "1:" 730 : "=&r" (tmp), ASM_CALL_CONSTRAINT : : "cc", "memory"); 731 #endif 732 } 733 734 extern void select_idle_routine(const struct cpuinfo_x86 *c); 735 extern void amd_e400_c1e_apic_setup(void); 736 737 extern unsigned long boot_option_idle_override; 738 739 enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_NOMWAIT, 740 IDLE_POLL}; 741 742 extern void enable_sep_cpu(void); 743 extern int sysenter_setup(void); 744 745 void early_trap_pf_init(void); 746 747 /* Defined in head.S */ 748 extern struct desc_ptr early_gdt_descr; 749 750 extern void switch_to_new_gdt(int); 751 extern void load_direct_gdt(int); 752 extern void load_fixmap_gdt(int); 753 extern void load_percpu_segment(int); 754 extern void cpu_init(void); 755 756 static inline unsigned long get_debugctlmsr(void) 757 { 758 unsigned long debugctlmsr = 0; 759 760 #ifndef CONFIG_X86_DEBUGCTLMSR 761 if (boot_cpu_data.x86 < 6) 762 return 0; 763 #endif 764 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr); 765 766 return debugctlmsr; 767 } 768 769 static inline void update_debugctlmsr(unsigned long debugctlmsr) 770 { 771 #ifndef CONFIG_X86_DEBUGCTLMSR 772 if (boot_cpu_data.x86 < 6) 773 return; 774 #endif 775 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr); 776 } 777 778 extern void set_task_blockstep(struct task_struct *task, bool on); 779 780 /* Boot loader type from the setup header: */ 781 extern int bootloader_type; 782 extern int bootloader_version; 783 784 extern char ignore_fpu_irq; 785 786 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1 787 #define ARCH_HAS_PREFETCHW 788 #define ARCH_HAS_SPINLOCK_PREFETCH 789 790 #ifdef CONFIG_X86_32 791 # define BASE_PREFETCH "" 792 # define ARCH_HAS_PREFETCH 793 #else 794 # define BASE_PREFETCH "prefetcht0 %P1" 795 #endif 796 797 /* 798 * Prefetch instructions for Pentium III (+) and AMD Athlon (+) 799 * 800 * It's not worth to care about 3dnow prefetches for the K6 801 * because they are microcoded there and very slow. 802 */ 803 static inline void prefetch(const void *x) 804 { 805 alternative_input(BASE_PREFETCH, "prefetchnta %P1", 806 X86_FEATURE_XMM, 807 "m" (*(const char *)x)); 808 } 809 810 /* 811 * 3dnow prefetch to get an exclusive cache line. 812 * Useful for spinlocks to avoid one state transition in the 813 * cache coherency protocol: 814 */ 815 static inline void prefetchw(const void *x) 816 { 817 alternative_input(BASE_PREFETCH, "prefetchw %P1", 818 X86_FEATURE_3DNOWPREFETCH, 819 "m" (*(const char *)x)); 820 } 821 822 static inline void spin_lock_prefetch(const void *x) 823 { 824 prefetchw(x); 825 } 826 827 #define TOP_OF_INIT_STACK ((unsigned long)&init_stack + sizeof(init_stack) - \ 828 TOP_OF_KERNEL_STACK_PADDING) 829 830 #define task_top_of_stack(task) ((unsigned long)(task_pt_regs(task) + 1)) 831 832 #define task_pt_regs(task) \ 833 ({ \ 834 unsigned long __ptr = (unsigned long)task_stack_page(task); \ 835 __ptr += THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING; \ 836 ((struct pt_regs *)__ptr) - 1; \ 837 }) 838 839 #ifdef CONFIG_X86_32 840 /* 841 * User space process size: 3GB (default). 842 */ 843 #define IA32_PAGE_OFFSET PAGE_OFFSET 844 #define TASK_SIZE PAGE_OFFSET 845 #define TASK_SIZE_LOW TASK_SIZE 846 #define TASK_SIZE_MAX TASK_SIZE 847 #define DEFAULT_MAP_WINDOW TASK_SIZE 848 #define STACK_TOP TASK_SIZE 849 #define STACK_TOP_MAX STACK_TOP 850 851 #define INIT_THREAD { \ 852 .sp0 = TOP_OF_INIT_STACK, \ 853 .sysenter_cs = __KERNEL_CS, \ 854 .io_bitmap_ptr = NULL, \ 855 .addr_limit = KERNEL_DS, \ 856 } 857 858 #define KSTK_ESP(task) (task_pt_regs(task)->sp) 859 860 #else 861 /* 862 * User space process size. This is the first address outside the user range. 863 * There are a few constraints that determine this: 864 * 865 * On Intel CPUs, if a SYSCALL instruction is at the highest canonical 866 * address, then that syscall will enter the kernel with a 867 * non-canonical return address, and SYSRET will explode dangerously. 868 * We avoid this particular problem by preventing anything executable 869 * from being mapped at the maximum canonical address. 870 * 871 * On AMD CPUs in the Ryzen family, there's a nasty bug in which the 872 * CPUs malfunction if they execute code from the highest canonical page. 873 * They'll speculate right off the end of the canonical space, and 874 * bad things happen. This is worked around in the same way as the 875 * Intel problem. 876 * 877 * With page table isolation enabled, we map the LDT in ... [stay tuned] 878 */ 879 #define TASK_SIZE_MAX ((1UL << __VIRTUAL_MASK_SHIFT) - PAGE_SIZE) 880 881 #define DEFAULT_MAP_WINDOW ((1UL << 47) - PAGE_SIZE) 882 883 /* This decides where the kernel will search for a free chunk of vm 884 * space during mmap's. 885 */ 886 #define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? \ 887 0xc0000000 : 0xFFFFe000) 888 889 #define TASK_SIZE_LOW (test_thread_flag(TIF_ADDR32) ? \ 890 IA32_PAGE_OFFSET : DEFAULT_MAP_WINDOW) 891 #define TASK_SIZE (test_thread_flag(TIF_ADDR32) ? \ 892 IA32_PAGE_OFFSET : TASK_SIZE_MAX) 893 #define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_ADDR32)) ? \ 894 IA32_PAGE_OFFSET : TASK_SIZE_MAX) 895 896 #define STACK_TOP TASK_SIZE_LOW 897 #define STACK_TOP_MAX TASK_SIZE_MAX 898 899 #define INIT_THREAD { \ 900 .addr_limit = KERNEL_DS, \ 901 } 902 903 extern unsigned long KSTK_ESP(struct task_struct *task); 904 905 #endif /* CONFIG_X86_64 */ 906 907 extern void start_thread(struct pt_regs *regs, unsigned long new_ip, 908 unsigned long new_sp); 909 910 /* 911 * This decides where the kernel will search for a free chunk of vm 912 * space during mmap's. 913 */ 914 #define __TASK_UNMAPPED_BASE(task_size) (PAGE_ALIGN(task_size / 3)) 915 #define TASK_UNMAPPED_BASE __TASK_UNMAPPED_BASE(TASK_SIZE_LOW) 916 917 #define KSTK_EIP(task) (task_pt_regs(task)->ip) 918 919 /* Get/set a process' ability to use the timestamp counter instruction */ 920 #define GET_TSC_CTL(adr) get_tsc_mode((adr)) 921 #define SET_TSC_CTL(val) set_tsc_mode((val)) 922 923 extern int get_tsc_mode(unsigned long adr); 924 extern int set_tsc_mode(unsigned int val); 925 926 DECLARE_PER_CPU(u64, msr_misc_features_shadow); 927 928 /* Register/unregister a process' MPX related resource */ 929 #define MPX_ENABLE_MANAGEMENT() mpx_enable_management() 930 #define MPX_DISABLE_MANAGEMENT() mpx_disable_management() 931 932 #ifdef CONFIG_X86_INTEL_MPX 933 extern int mpx_enable_management(void); 934 extern int mpx_disable_management(void); 935 #else 936 static inline int mpx_enable_management(void) 937 { 938 return -EINVAL; 939 } 940 static inline int mpx_disable_management(void) 941 { 942 return -EINVAL; 943 } 944 #endif /* CONFIG_X86_INTEL_MPX */ 945 946 #ifdef CONFIG_CPU_SUP_AMD 947 extern u16 amd_get_nb_id(int cpu); 948 extern u32 amd_get_nodes_per_socket(void); 949 #else 950 static inline u16 amd_get_nb_id(int cpu) { return 0; } 951 static inline u32 amd_get_nodes_per_socket(void) { return 0; } 952 #endif 953 954 static inline uint32_t hypervisor_cpuid_base(const char *sig, uint32_t leaves) 955 { 956 uint32_t base, eax, signature[3]; 957 958 for (base = 0x40000000; base < 0x40010000; base += 0x100) { 959 cpuid(base, &eax, &signature[0], &signature[1], &signature[2]); 960 961 if (!memcmp(sig, signature, 12) && 962 (leaves == 0 || ((eax - base) >= leaves))) 963 return base; 964 } 965 966 return 0; 967 } 968 969 extern unsigned long arch_align_stack(unsigned long sp); 970 extern void free_init_pages(char *what, unsigned long begin, unsigned long end); 971 extern void free_kernel_image_pages(void *begin, void *end); 972 973 void default_idle(void); 974 #ifdef CONFIG_XEN 975 bool xen_set_default_idle(void); 976 #else 977 #define xen_set_default_idle 0 978 #endif 979 980 void stop_this_cpu(void *dummy); 981 void df_debug(struct pt_regs *regs, long error_code); 982 void microcode_check(void); 983 984 enum l1tf_mitigations { 985 L1TF_MITIGATION_OFF, 986 L1TF_MITIGATION_FLUSH_NOWARN, 987 L1TF_MITIGATION_FLUSH, 988 L1TF_MITIGATION_FLUSH_NOSMT, 989 L1TF_MITIGATION_FULL, 990 L1TF_MITIGATION_FULL_FORCE 991 }; 992 993 extern enum l1tf_mitigations l1tf_mitigation; 994 995 #endif /* _ASM_X86_PROCESSOR_H */ 996