11965aae3SH. Peter Anvin #ifndef _ASM_X86_PROCESSOR_H 21965aae3SH. Peter Anvin #define _ASM_X86_PROCESSOR_H 3bb898558SAl Viro 4bb898558SAl Viro #include <asm/processor-flags.h> 5bb898558SAl Viro 6bb898558SAl Viro /* Forward declaration, a strange C thing */ 7bb898558SAl Viro struct task_struct; 8bb898558SAl Viro struct mm_struct; 99fda6a06SBrian Gerst struct vm86; 10bb898558SAl Viro 11bb898558SAl Viro #include <asm/math_emu.h> 12bb898558SAl Viro #include <asm/segment.h> 13bb898558SAl Viro #include <asm/types.h> 14decb4c41SIngo Molnar #include <uapi/asm/sigcontext.h> 15bb898558SAl Viro #include <asm/current.h> 16cd4d09ecSBorislav Petkov #include <asm/cpufeatures.h> 17bb898558SAl Viro #include <asm/page.h> 1854321d94SJeremy Fitzhardinge #include <asm/pgtable_types.h> 19bb898558SAl Viro #include <asm/percpu.h> 20bb898558SAl Viro #include <asm/msr.h> 21bb898558SAl Viro #include <asm/desc_defs.h> 22bb898558SAl Viro #include <asm/nops.h> 23f05e798aSDavid Howells #include <asm/special_insns.h> 2414b9675aSIngo Molnar #include <asm/fpu/types.h> 2576846bf3SJosh Poimboeuf #include <asm/unwind_hints.h> 26bb898558SAl Viro 27bb898558SAl Viro #include <linux/personality.h> 28bb898558SAl Viro #include <linux/cache.h> 29bb898558SAl Viro #include <linux/threads.h> 305cbc19a9SPeter Zijlstra #include <linux/math64.h> 31faa4602eSPeter Zijlstra #include <linux/err.h> 32f05e798aSDavid Howells #include <linux/irqflags.h> 3321729f81STom Lendacky #include <linux/mem_encrypt.h> 34f05e798aSDavid Howells 35f05e798aSDavid Howells /* 36f05e798aSDavid Howells * We handle most unaligned accesses in hardware. On the other hand 37f05e798aSDavid Howells * unaligned DMA can be quite expensive on some Nehalem processors. 38f05e798aSDavid Howells * 39f05e798aSDavid Howells * Based on this we disable the IP header alignment in network drivers. 40f05e798aSDavid Howells */ 41f05e798aSDavid Howells #define NET_IP_ALIGN 0 42bb898558SAl Viro 43b332828cSK.Prasad #define HBP_NUM 4 44bb898558SAl Viro /* 45bb898558SAl Viro * Default implementation of macro that returns current 46bb898558SAl Viro * instruction pointer ("program counter"). 47bb898558SAl Viro */ 48bb898558SAl Viro static inline void *current_text_addr(void) 49bb898558SAl Viro { 50bb898558SAl Viro void *pc; 51bb898558SAl Viro 52bb898558SAl Viro asm volatile("mov $1f, %0; 1:":"=r" (pc)); 53bb898558SAl Viro 54bb898558SAl Viro return pc; 55bb898558SAl Viro } 56bb898558SAl Viro 57b8c1b8eaSIngo Molnar /* 58b8c1b8eaSIngo Molnar * These alignment constraints are for performance in the vSMP case, 59b8c1b8eaSIngo Molnar * but in the task_struct case we must also meet hardware imposed 60b8c1b8eaSIngo Molnar * alignment requirements of the FPU state: 61b8c1b8eaSIngo Molnar */ 62bb898558SAl Viro #ifdef CONFIG_X86_VSMP 63bb898558SAl Viro # define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT) 64bb898558SAl Viro # define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT) 65bb898558SAl Viro #else 66b8c1b8eaSIngo Molnar # define ARCH_MIN_TASKALIGN __alignof__(union fpregs_state) 67bb898558SAl Viro # define ARCH_MIN_MMSTRUCT_ALIGN 0 68bb898558SAl Viro #endif 69bb898558SAl Viro 70e0ba94f1SAlex Shi enum tlb_infos { 71e0ba94f1SAlex Shi ENTRIES, 72e0ba94f1SAlex Shi NR_INFO 73e0ba94f1SAlex Shi }; 74e0ba94f1SAlex Shi 75e0ba94f1SAlex Shi extern u16 __read_mostly tlb_lli_4k[NR_INFO]; 76e0ba94f1SAlex Shi extern u16 __read_mostly tlb_lli_2m[NR_INFO]; 77e0ba94f1SAlex Shi extern u16 __read_mostly tlb_lli_4m[NR_INFO]; 78e0ba94f1SAlex Shi extern u16 __read_mostly tlb_lld_4k[NR_INFO]; 79e0ba94f1SAlex Shi extern u16 __read_mostly tlb_lld_2m[NR_INFO]; 80e0ba94f1SAlex Shi extern u16 __read_mostly tlb_lld_4m[NR_INFO]; 81dd360393SKirill A. Shutemov extern u16 __read_mostly tlb_lld_1g[NR_INFO]; 82c4211f42SAlex Shi 83bb898558SAl Viro /* 84bb898558SAl Viro * CPU type and hardware bug flags. Kept separately for each CPU. 8504402116SMathias Krause * Members of this structure are referenced in head_32.S, so think twice 86bb898558SAl Viro * before touching them. [mj] 87bb898558SAl Viro */ 88bb898558SAl Viro 89bb898558SAl Viro struct cpuinfo_x86 { 90bb898558SAl Viro __u8 x86; /* CPU family */ 91bb898558SAl Viro __u8 x86_vendor; /* CPU vendor */ 92bb898558SAl Viro __u8 x86_model; 93bb898558SAl Viro __u8 x86_mask; 946415813bSMathias Krause #ifdef CONFIG_X86_64 95bb898558SAl Viro /* Number of 4K pages in DTLB/ITLB combined(in pages): */ 96bb898558SAl Viro int x86_tlbsize; 9713c6c532SJan Beulich #endif 98bb898558SAl Viro __u8 x86_virt_bits; 99bb898558SAl Viro __u8 x86_phys_bits; 100bb898558SAl Viro /* CPUID returned core id bits: */ 101bb898558SAl Viro __u8 x86_coreid_bits; 10279a8b9aaSBorislav Petkov __u8 cu_id; 103bb898558SAl Viro /* Max extended CPUID function supported: */ 104bb898558SAl Viro __u32 extended_cpuid_level; 105bb898558SAl Viro /* Maximum supported CPUID level, -1=no CPUID: */ 106bb898558SAl Viro int cpuid_level; 10765fc985bSBorislav Petkov __u32 x86_capability[NCAPINTS + NBUGINTS]; 108bb898558SAl Viro char x86_vendor_id[16]; 109bb898558SAl Viro char x86_model_id[64]; 110bb898558SAl Viro /* in KB - valid for CPUS which support this call: */ 111bb898558SAl Viro int x86_cache_size; 112bb898558SAl Viro int x86_cache_alignment; /* In bytes */ 113cbc82b17SPeter P Waskiewicz Jr /* Cache QoS architectural values: */ 114cbc82b17SPeter P Waskiewicz Jr int x86_cache_max_rmid; /* max index */ 115cbc82b17SPeter P Waskiewicz Jr int x86_cache_occ_scale; /* scale to bytes */ 116bb898558SAl Viro int x86_power; 117bb898558SAl Viro unsigned long loops_per_jiffy; 118bb898558SAl Viro /* cpuid returned max cores value: */ 119bb898558SAl Viro u16 x86_max_cores; 120bb898558SAl Viro u16 apicid; 121bb898558SAl Viro u16 initial_apicid; 122bb898558SAl Viro u16 x86_clflush_size; 123bb898558SAl Viro /* number of cores as seen by the OS: */ 124bb898558SAl Viro u16 booted_cores; 125bb898558SAl Viro /* Physical processor id: */ 126bb898558SAl Viro u16 phys_proc_id; 1271f12e32fSThomas Gleixner /* Logical processor id: */ 1281f12e32fSThomas Gleixner u16 logical_proc_id; 129bb898558SAl Viro /* Core id: */ 130bb898558SAl Viro u16 cpu_core_id; 131bb898558SAl Viro /* Index into per_cpu list: */ 132bb898558SAl Viro u16 cpu_index; 133506ed6b5SAndi Kleen u32 microcode; 1343859a271SKees Cook } __randomize_layout; 135bb898558SAl Viro 13647f10a36SHe Chen struct cpuid_regs { 13747f10a36SHe Chen u32 eax, ebx, ecx, edx; 13847f10a36SHe Chen }; 13947f10a36SHe Chen 14047f10a36SHe Chen enum cpuid_regs_idx { 14147f10a36SHe Chen CPUID_EAX = 0, 14247f10a36SHe Chen CPUID_EBX, 14347f10a36SHe Chen CPUID_ECX, 14447f10a36SHe Chen CPUID_EDX, 14547f10a36SHe Chen }; 14647f10a36SHe Chen 147bb898558SAl Viro #define X86_VENDOR_INTEL 0 148bb898558SAl Viro #define X86_VENDOR_CYRIX 1 149bb898558SAl Viro #define X86_VENDOR_AMD 2 150bb898558SAl Viro #define X86_VENDOR_UMC 3 151bb898558SAl Viro #define X86_VENDOR_CENTAUR 5 152bb898558SAl Viro #define X86_VENDOR_TRANSMETA 7 153bb898558SAl Viro #define X86_VENDOR_NSC 8 154bb898558SAl Viro #define X86_VENDOR_NUM 9 155bb898558SAl Viro 156bb898558SAl Viro #define X86_VENDOR_UNKNOWN 0xff 157bb898558SAl Viro 158bb898558SAl Viro /* 159bb898558SAl Viro * capabilities of CPUs 160bb898558SAl Viro */ 161bb898558SAl Viro extern struct cpuinfo_x86 boot_cpu_data; 162bb898558SAl Viro extern struct cpuinfo_x86 new_cpu_data; 163bb898558SAl Viro 164bb898558SAl Viro extern struct tss_struct doublefault_tss; 1653e0c3737SYinghai Lu extern __u32 cpu_caps_cleared[NCAPINTS]; 1663e0c3737SYinghai Lu extern __u32 cpu_caps_set[NCAPINTS]; 167bb898558SAl Viro 168bb898558SAl Viro #ifdef CONFIG_SMP 1692c773dd3SJan Beulich DECLARE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info); 170bb898558SAl Viro #define cpu_data(cpu) per_cpu(cpu_info, cpu) 171bb898558SAl Viro #else 1727b543a53STejun Heo #define cpu_info boot_cpu_data 173bb898558SAl Viro #define cpu_data(cpu) boot_cpu_data 174bb898558SAl Viro #endif 175bb898558SAl Viro 176bb898558SAl Viro extern const struct seq_operations cpuinfo_op; 177bb898558SAl Viro 178bb898558SAl Viro #define cache_line_size() (boot_cpu_data.x86_cache_alignment) 179bb898558SAl Viro 180bb898558SAl Viro extern void cpu_detect(struct cpuinfo_x86 *c); 181bb898558SAl Viro 182bb898558SAl Viro extern void early_cpu_init(void); 183bb898558SAl Viro extern void identify_boot_cpu(void); 184bb898558SAl Viro extern void identify_secondary_cpu(struct cpuinfo_x86 *); 185bb898558SAl Viro extern void print_cpu_info(struct cpuinfo_x86 *); 18621c3fcf3SYinghai Lu void print_cpu_msr(struct cpuinfo_x86 *); 187bb898558SAl Viro extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c); 18847bdf337SHe Chen extern u32 get_scattered_cpuid_leaf(unsigned int level, 18947bdf337SHe Chen unsigned int sub_leaf, 19047bdf337SHe Chen enum cpuid_regs_idx reg); 191bb898558SAl Viro extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c); 19204a15418SAndreas Herrmann extern void init_amd_cacheinfo(struct cpuinfo_x86 *c); 193bb898558SAl Viro 194bb898558SAl Viro extern void detect_extended_topology(struct cpuinfo_x86 *c); 195bb898558SAl Viro extern void detect_ht(struct cpuinfo_x86 *c); 196bb898558SAl Viro 197d288e1cfSFenghua Yu #ifdef CONFIG_X86_32 198d288e1cfSFenghua Yu extern int have_cpuid_p(void); 199d288e1cfSFenghua Yu #else 200d288e1cfSFenghua Yu static inline int have_cpuid_p(void) 201d288e1cfSFenghua Yu { 202d288e1cfSFenghua Yu return 1; 203d288e1cfSFenghua Yu } 204d288e1cfSFenghua Yu #endif 205bb898558SAl Viro static inline void native_cpuid(unsigned int *eax, unsigned int *ebx, 206bb898558SAl Viro unsigned int *ecx, unsigned int *edx) 207bb898558SAl Viro { 208bb898558SAl Viro /* ecx is often an input as well as an output. */ 20945a94d7cSSuresh Siddha asm volatile("cpuid" 210bb898558SAl Viro : "=a" (*eax), 211bb898558SAl Viro "=b" (*ebx), 212bb898558SAl Viro "=c" (*ecx), 213bb898558SAl Viro "=d" (*edx) 214506ed6b5SAndi Kleen : "0" (*eax), "2" (*ecx) 215506ed6b5SAndi Kleen : "memory"); 216bb898558SAl Viro } 217bb898558SAl Viro 2185dedade6SBorislav Petkov #define native_cpuid_reg(reg) \ 2195dedade6SBorislav Petkov static inline unsigned int native_cpuid_##reg(unsigned int op) \ 2205dedade6SBorislav Petkov { \ 2215dedade6SBorislav Petkov unsigned int eax = op, ebx, ecx = 0, edx; \ 2225dedade6SBorislav Petkov \ 2235dedade6SBorislav Petkov native_cpuid(&eax, &ebx, &ecx, &edx); \ 2245dedade6SBorislav Petkov \ 2255dedade6SBorislav Petkov return reg; \ 2265dedade6SBorislav Petkov } 2275dedade6SBorislav Petkov 2285dedade6SBorislav Petkov /* 2295dedade6SBorislav Petkov * Native CPUID functions returning a single datum. 2305dedade6SBorislav Petkov */ 2315dedade6SBorislav Petkov native_cpuid_reg(eax) 2325dedade6SBorislav Petkov native_cpuid_reg(ebx) 2335dedade6SBorislav Petkov native_cpuid_reg(ecx) 2345dedade6SBorislav Petkov native_cpuid_reg(edx) 2355dedade6SBorislav Petkov 2366c690ee1SAndy Lutomirski /* 2376c690ee1SAndy Lutomirski * Friendlier CR3 helpers. 2386c690ee1SAndy Lutomirski */ 2396c690ee1SAndy Lutomirski static inline unsigned long read_cr3_pa(void) 2406c690ee1SAndy Lutomirski { 2416c690ee1SAndy Lutomirski return __read_cr3() & CR3_ADDR_MASK; 2426c690ee1SAndy Lutomirski } 2436c690ee1SAndy Lutomirski 244eef9c4abSTom Lendacky static inline unsigned long native_read_cr3_pa(void) 245eef9c4abSTom Lendacky { 246eef9c4abSTom Lendacky return __native_read_cr3() & CR3_ADDR_MASK; 247eef9c4abSTom Lendacky } 248eef9c4abSTom Lendacky 249bb898558SAl Viro static inline void load_cr3(pgd_t *pgdir) 250bb898558SAl Viro { 25121729f81STom Lendacky write_cr3(__sme_pa(pgdir)); 252bb898558SAl Viro } 253bb898558SAl Viro 254bb898558SAl Viro #ifdef CONFIG_X86_32 255bb898558SAl Viro /* This is the TSS defined by the hardware. */ 256bb898558SAl Viro struct x86_hw_tss { 257bb898558SAl Viro unsigned short back_link, __blh; 258bb898558SAl Viro unsigned long sp0; 259bb898558SAl Viro unsigned short ss0, __ss0h; 260cf9328ccSAndy Lutomirski unsigned long sp1; 26176e4c490SAndy Lutomirski 26276e4c490SAndy Lutomirski /* 263cf9328ccSAndy Lutomirski * We don't use ring 1, so ss1 is a convenient scratch space in 264cf9328ccSAndy Lutomirski * the same cacheline as sp0. We use ss1 to cache the value in 265cf9328ccSAndy Lutomirski * MSR_IA32_SYSENTER_CS. When we context switch 266cf9328ccSAndy Lutomirski * MSR_IA32_SYSENTER_CS, we first check if the new value being 267cf9328ccSAndy Lutomirski * written matches ss1, and, if it's not, then we wrmsr the new 268cf9328ccSAndy Lutomirski * value and update ss1. 26976e4c490SAndy Lutomirski * 270cf9328ccSAndy Lutomirski * The only reason we context switch MSR_IA32_SYSENTER_CS is 271cf9328ccSAndy Lutomirski * that we set it to zero in vm86 tasks to avoid corrupting the 272cf9328ccSAndy Lutomirski * stack if we were to go through the sysenter path from vm86 273cf9328ccSAndy Lutomirski * mode. 27476e4c490SAndy Lutomirski */ 27576e4c490SAndy Lutomirski unsigned short ss1; /* MSR_IA32_SYSENTER_CS */ 27676e4c490SAndy Lutomirski 27776e4c490SAndy Lutomirski unsigned short __ss1h; 278bb898558SAl Viro unsigned long sp2; 279bb898558SAl Viro unsigned short ss2, __ss2h; 280bb898558SAl Viro unsigned long __cr3; 281bb898558SAl Viro unsigned long ip; 282bb898558SAl Viro unsigned long flags; 283bb898558SAl Viro unsigned long ax; 284bb898558SAl Viro unsigned long cx; 285bb898558SAl Viro unsigned long dx; 286bb898558SAl Viro unsigned long bx; 287bb898558SAl Viro unsigned long sp; 288bb898558SAl Viro unsigned long bp; 289bb898558SAl Viro unsigned long si; 290bb898558SAl Viro unsigned long di; 291bb898558SAl Viro unsigned short es, __esh; 292bb898558SAl Viro unsigned short cs, __csh; 293bb898558SAl Viro unsigned short ss, __ssh; 294bb898558SAl Viro unsigned short ds, __dsh; 295bb898558SAl Viro unsigned short fs, __fsh; 296bb898558SAl Viro unsigned short gs, __gsh; 297bb898558SAl Viro unsigned short ldt, __ldth; 298bb898558SAl Viro unsigned short trace; 299bb898558SAl Viro unsigned short io_bitmap_base; 300bb898558SAl Viro 301bb898558SAl Viro } __attribute__((packed)); 302bb898558SAl Viro #else 303bb898558SAl Viro struct x86_hw_tss { 304bb898558SAl Viro u32 reserved1; 305bb898558SAl Viro u64 sp0; 306bb898558SAl Viro u64 sp1; 307bb898558SAl Viro u64 sp2; 308bb898558SAl Viro u64 reserved2; 309bb898558SAl Viro u64 ist[7]; 310bb898558SAl Viro u32 reserved3; 311bb898558SAl Viro u32 reserved4; 312bb898558SAl Viro u16 reserved5; 313bb898558SAl Viro u16 io_bitmap_base; 314bb898558SAl Viro 315d3273deaSAndy Lutomirski } __attribute__((packed)); 316bb898558SAl Viro #endif 317bb898558SAl Viro 318bb898558SAl Viro /* 319bb898558SAl Viro * IO-bitmap sizes: 320bb898558SAl Viro */ 321bb898558SAl Viro #define IO_BITMAP_BITS 65536 322bb898558SAl Viro #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8) 323bb898558SAl Viro #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long)) 324bb898558SAl Viro #define IO_BITMAP_OFFSET offsetof(struct tss_struct, io_bitmap) 325bb898558SAl Viro #define INVALID_IO_BITMAP_OFFSET 0x8000 326bb898558SAl Viro 327bb898558SAl Viro struct tss_struct { 328bb898558SAl Viro /* 329bb898558SAl Viro * The hardware state: 330bb898558SAl Viro */ 331bb898558SAl Viro struct x86_hw_tss x86_tss; 332bb898558SAl Viro 333bb898558SAl Viro /* 334bb898558SAl Viro * The extra 1 is there because the CPU will access an 335bb898558SAl Viro * additional byte beyond the end of the IO permission 336bb898558SAl Viro * bitmap. The extra byte must be all 1 bits, and must 337bb898558SAl Viro * be within the limit. 338bb898558SAl Viro */ 339bb898558SAl Viro unsigned long io_bitmap[IO_BITMAP_LONGS + 1]; 340bb898558SAl Viro 3416dcc9414SAndy Lutomirski #ifdef CONFIG_X86_32 342bb898558SAl Viro /* 3432a41aa4fSAndy Lutomirski * Space for the temporary SYSENTER stack. 344bb898558SAl Viro */ 3452a41aa4fSAndy Lutomirski unsigned long SYSENTER_stack_canary; 346d828c71fSDenys Vlasenko unsigned long SYSENTER_stack[64]; 3476dcc9414SAndy Lutomirski #endif 348bb898558SAl Viro 349bb898558SAl Viro } ____cacheline_aligned; 350bb898558SAl Viro 35124933b82SAndy Lutomirski DECLARE_PER_CPU_SHARED_ALIGNED(struct tss_struct, cpu_tss); 352bb898558SAl Viro 3534f53ab14SAndy Lutomirski /* 3544f53ab14SAndy Lutomirski * sizeof(unsigned long) coming from an extra "long" at the end 3554f53ab14SAndy Lutomirski * of the iobitmap. 3564f53ab14SAndy Lutomirski * 3574f53ab14SAndy Lutomirski * -1? seg base+limit should be pointing to the address of the 3584f53ab14SAndy Lutomirski * last valid byte 3594f53ab14SAndy Lutomirski */ 3604f53ab14SAndy Lutomirski #define __KERNEL_TSS_LIMIT \ 3614f53ab14SAndy Lutomirski (IO_BITMAP_OFFSET + IO_BITMAP_BYTES + sizeof(unsigned long) - 1) 3624f53ab14SAndy Lutomirski 363a7fcf28dSAndy Lutomirski #ifdef CONFIG_X86_32 364a7fcf28dSAndy Lutomirski DECLARE_PER_CPU(unsigned long, cpu_current_top_of_stack); 365a7fcf28dSAndy Lutomirski #endif 366a7fcf28dSAndy Lutomirski 367bb898558SAl Viro /* 368bb898558SAl Viro * Save the original ist values for checking stack pointers during debugging 369bb898558SAl Viro */ 370bb898558SAl Viro struct orig_ist { 371bb898558SAl Viro unsigned long ist[7]; 372bb898558SAl Viro }; 373bb898558SAl Viro 374bb898558SAl Viro #ifdef CONFIG_X86_64 375bb898558SAl Viro DECLARE_PER_CPU(struct orig_ist, orig_ist); 37626f80bd6SBrian Gerst 377947e76cdSBrian Gerst union irq_stack_union { 378947e76cdSBrian Gerst char irq_stack[IRQ_STACK_SIZE]; 379947e76cdSBrian Gerst /* 380947e76cdSBrian Gerst * GCC hardcodes the stack canary as %gs:40. Since the 381947e76cdSBrian Gerst * irq_stack is the object at %gs:0, we reserve the bottom 382947e76cdSBrian Gerst * 48 bytes of the irq stack for the canary. 383947e76cdSBrian Gerst */ 384947e76cdSBrian Gerst struct { 385947e76cdSBrian Gerst char gs_base[40]; 386947e76cdSBrian Gerst unsigned long stack_canary; 387947e76cdSBrian Gerst }; 388947e76cdSBrian Gerst }; 389947e76cdSBrian Gerst 390277d5b40SAndi Kleen DECLARE_PER_CPU_FIRST(union irq_stack_union, irq_stack_union) __visible; 3912add8e23SBrian Gerst DECLARE_INIT_PER_CPU(irq_stack_union); 3922add8e23SBrian Gerst 39326f80bd6SBrian Gerst DECLARE_PER_CPU(char *, irq_stack_ptr); 3949766cdbcSJaswinder Singh Rajput DECLARE_PER_CPU(unsigned int, irq_count); 3959766cdbcSJaswinder Singh Rajput extern asmlinkage void ignore_sysret(void); 39660a5317fSTejun Heo #else /* X86_64 */ 39760a5317fSTejun Heo #ifdef CONFIG_CC_STACKPROTECTOR 3981ea0d14eSJeremy Fitzhardinge /* 3991ea0d14eSJeremy Fitzhardinge * Make sure stack canary segment base is cached-aligned: 4001ea0d14eSJeremy Fitzhardinge * "For Intel Atom processors, avoid non zero segment base address 4011ea0d14eSJeremy Fitzhardinge * that is not aligned to cache line boundary at all cost." 4021ea0d14eSJeremy Fitzhardinge * (Optim Ref Manual Assembly/Compiler Coding Rule 15.) 4031ea0d14eSJeremy Fitzhardinge */ 4041ea0d14eSJeremy Fitzhardinge struct stack_canary { 4051ea0d14eSJeremy Fitzhardinge char __pad[20]; /* canary at %gs:20 */ 4061ea0d14eSJeremy Fitzhardinge unsigned long canary; 4071ea0d14eSJeremy Fitzhardinge }; 40853f82452SJeremy Fitzhardinge DECLARE_PER_CPU_ALIGNED(struct stack_canary, stack_canary); 409bb898558SAl Viro #endif 410198d208dSSteven Rostedt /* 411198d208dSSteven Rostedt * per-CPU IRQ handling stacks 412198d208dSSteven Rostedt */ 413198d208dSSteven Rostedt struct irq_stack { 414198d208dSSteven Rostedt u32 stack[THREAD_SIZE/sizeof(u32)]; 415198d208dSSteven Rostedt } __aligned(THREAD_SIZE); 416198d208dSSteven Rostedt 417198d208dSSteven Rostedt DECLARE_PER_CPU(struct irq_stack *, hardirq_stack); 418198d208dSSteven Rostedt DECLARE_PER_CPU(struct irq_stack *, softirq_stack); 41960a5317fSTejun Heo #endif /* X86_64 */ 420bb898558SAl Viro 421bf15a8cfSFenghua Yu extern unsigned int fpu_kernel_xstate_size; 422a1141e0bSFenghua Yu extern unsigned int fpu_user_xstate_size; 423bb898558SAl Viro 42424f1e32cSFrederic Weisbecker struct perf_event; 42524f1e32cSFrederic Weisbecker 42613d4ea09SAndy Lutomirski typedef struct { 42713d4ea09SAndy Lutomirski unsigned long seg; 42813d4ea09SAndy Lutomirski } mm_segment_t; 42913d4ea09SAndy Lutomirski 430bb898558SAl Viro struct thread_struct { 431bb898558SAl Viro /* Cached TLS descriptors: */ 432bb898558SAl Viro struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES]; 433bb898558SAl Viro unsigned long sp0; 434bb898558SAl Viro unsigned long sp; 435bb898558SAl Viro #ifdef CONFIG_X86_32 436bb898558SAl Viro unsigned long sysenter_cs; 437bb898558SAl Viro #else 438bb898558SAl Viro unsigned short es; 439bb898558SAl Viro unsigned short ds; 440bb898558SAl Viro unsigned short fsindex; 441bb898558SAl Viro unsigned short gsindex; 442bb898558SAl Viro #endif 443b9d989c7SAndy Lutomirski 444b9d989c7SAndy Lutomirski u32 status; /* thread synchronous flags */ 445b9d989c7SAndy Lutomirski 446d756f4adSAlexey Dobriyan #ifdef CONFIG_X86_64 447296f781aSAndy Lutomirski unsigned long fsbase; 448296f781aSAndy Lutomirski unsigned long gsbase; 449296f781aSAndy Lutomirski #else 450296f781aSAndy Lutomirski /* 451296f781aSAndy Lutomirski * XXX: this could presumably be unsigned short. Alternatively, 452296f781aSAndy Lutomirski * 32-bit kernels could be taught to use fsindex instead. 453296f781aSAndy Lutomirski */ 454bb898558SAl Viro unsigned long fs; 455bb898558SAl Viro unsigned long gs; 456296f781aSAndy Lutomirski #endif 457c5bedc68SIngo Molnar 45824f1e32cSFrederic Weisbecker /* Save middle states of ptrace breakpoints */ 45924f1e32cSFrederic Weisbecker struct perf_event *ptrace_bps[HBP_NUM]; 46024f1e32cSFrederic Weisbecker /* Debug status used for traps, single steps, etc... */ 461bb898558SAl Viro unsigned long debugreg6; 462326264a0SFrederic Weisbecker /* Keep track of the exact dr7 value set by the user */ 463326264a0SFrederic Weisbecker unsigned long ptrace_dr7; 464bb898558SAl Viro /* Fault info: */ 465bb898558SAl Viro unsigned long cr2; 46651e7dc70SSrikar Dronamraju unsigned long trap_nr; 467bb898558SAl Viro unsigned long error_code; 4689fda6a06SBrian Gerst #ifdef CONFIG_VM86 469bb898558SAl Viro /* Virtual 86 mode info */ 4709fda6a06SBrian Gerst struct vm86 *vm86; 471bb898558SAl Viro #endif 472bb898558SAl Viro /* IO permissions: */ 473bb898558SAl Viro unsigned long *io_bitmap_ptr; 474bb898558SAl Viro unsigned long iopl; 475bb898558SAl Viro /* Max allowed port in the bitmap, in bytes: */ 476bb898558SAl Viro unsigned io_bitmap_max; 4770c8c0f03SDave Hansen 47813d4ea09SAndy Lutomirski mm_segment_t addr_limit; 47913d4ea09SAndy Lutomirski 4802a53ccbcSIngo Molnar unsigned int sig_on_uaccess_err:1; 481dfa9a942SAndy Lutomirski unsigned int uaccess_err:1; /* uaccess failed */ 482dfa9a942SAndy Lutomirski 4830c8c0f03SDave Hansen /* Floating point and extended processor state */ 4840c8c0f03SDave Hansen struct fpu fpu; 4850c8c0f03SDave Hansen /* 4860c8c0f03SDave Hansen * WARNING: 'fpu' is dynamically-sized. It *MUST* be at 4870c8c0f03SDave Hansen * the end. 4880c8c0f03SDave Hansen */ 489bb898558SAl Viro }; 490bb898558SAl Viro 491bb898558SAl Viro /* 492b9d989c7SAndy Lutomirski * Thread-synchronous status. 493b9d989c7SAndy Lutomirski * 494b9d989c7SAndy Lutomirski * This is different from the flags in that nobody else 495b9d989c7SAndy Lutomirski * ever touches our thread-synchronous status, so we don't 496b9d989c7SAndy Lutomirski * have to worry about atomic accesses. 497b9d989c7SAndy Lutomirski */ 498b9d989c7SAndy Lutomirski #define TS_COMPAT 0x0002 /* 32bit syscall active (64BIT)*/ 499b9d989c7SAndy Lutomirski 500b9d989c7SAndy Lutomirski /* 501bb898558SAl Viro * Set IOPL bits in EFLAGS from given mask 502bb898558SAl Viro */ 503bb898558SAl Viro static inline void native_set_iopl_mask(unsigned mask) 504bb898558SAl Viro { 505bb898558SAl Viro #ifdef CONFIG_X86_32 506bb898558SAl Viro unsigned int reg; 507bb898558SAl Viro 508bb898558SAl Viro asm volatile ("pushfl;" 509bb898558SAl Viro "popl %0;" 510bb898558SAl Viro "andl %1, %0;" 511bb898558SAl Viro "orl %2, %0;" 512bb898558SAl Viro "pushl %0;" 513bb898558SAl Viro "popfl" 514bb898558SAl Viro : "=&r" (reg) 515bb898558SAl Viro : "i" (~X86_EFLAGS_IOPL), "r" (mask)); 516bb898558SAl Viro #endif 517bb898558SAl Viro } 518bb898558SAl Viro 519bb898558SAl Viro static inline void 520bb898558SAl Viro native_load_sp0(struct tss_struct *tss, struct thread_struct *thread) 521bb898558SAl Viro { 522bb898558SAl Viro tss->x86_tss.sp0 = thread->sp0; 523bb898558SAl Viro #ifdef CONFIG_X86_32 524bb898558SAl Viro /* Only happens when SEP is enabled, no need to test "SEP"arately: */ 525bb898558SAl Viro if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) { 526bb898558SAl Viro tss->x86_tss.ss1 = thread->sysenter_cs; 527bb898558SAl Viro wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0); 528bb898558SAl Viro } 529bb898558SAl Viro #endif 530bb898558SAl Viro } 531bb898558SAl Viro 532bb898558SAl Viro static inline void native_swapgs(void) 533bb898558SAl Viro { 534bb898558SAl Viro #ifdef CONFIG_X86_64 535bb898558SAl Viro asm volatile("swapgs" ::: "memory"); 536bb898558SAl Viro #endif 537bb898558SAl Viro } 538bb898558SAl Viro 539a7fcf28dSAndy Lutomirski static inline unsigned long current_top_of_stack(void) 5408ef46a67SAndy Lutomirski { 541a7fcf28dSAndy Lutomirski #ifdef CONFIG_X86_64 54224933b82SAndy Lutomirski return this_cpu_read_stable(cpu_tss.x86_tss.sp0); 543a7fcf28dSAndy Lutomirski #else 544a7fcf28dSAndy Lutomirski /* sp0 on x86_32 is special in and around vm86 mode. */ 545a7fcf28dSAndy Lutomirski return this_cpu_read_stable(cpu_current_top_of_stack); 546a7fcf28dSAndy Lutomirski #endif 5478ef46a67SAndy Lutomirski } 5488ef46a67SAndy Lutomirski 549bb898558SAl Viro #ifdef CONFIG_PARAVIRT 550bb898558SAl Viro #include <asm/paravirt.h> 551bb898558SAl Viro #else 552bb898558SAl Viro #define __cpuid native_cpuid 553bb898558SAl Viro 554bb898558SAl Viro static inline void load_sp0(struct tss_struct *tss, 555bb898558SAl Viro struct thread_struct *thread) 556bb898558SAl Viro { 557bb898558SAl Viro native_load_sp0(tss, thread); 558bb898558SAl Viro } 559bb898558SAl Viro 560bb898558SAl Viro #define set_iopl_mask native_set_iopl_mask 561bb898558SAl Viro #endif /* CONFIG_PARAVIRT */ 562bb898558SAl Viro 563bb898558SAl Viro /* Free all resources held by a thread. */ 564bb898558SAl Viro extern void release_thread(struct task_struct *); 565bb898558SAl Viro 566bb898558SAl Viro unsigned long get_wchan(struct task_struct *p); 567bb898558SAl Viro 568bb898558SAl Viro /* 569bb898558SAl Viro * Generic CPUID function 570bb898558SAl Viro * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx 571bb898558SAl Viro * resulting in stale register contents being returned. 572bb898558SAl Viro */ 573bb898558SAl Viro static inline void cpuid(unsigned int op, 574bb898558SAl Viro unsigned int *eax, unsigned int *ebx, 575bb898558SAl Viro unsigned int *ecx, unsigned int *edx) 576bb898558SAl Viro { 577bb898558SAl Viro *eax = op; 578bb898558SAl Viro *ecx = 0; 579bb898558SAl Viro __cpuid(eax, ebx, ecx, edx); 580bb898558SAl Viro } 581bb898558SAl Viro 582bb898558SAl Viro /* Some CPUID calls want 'count' to be placed in ecx */ 583bb898558SAl Viro static inline void cpuid_count(unsigned int op, int count, 584bb898558SAl Viro unsigned int *eax, unsigned int *ebx, 585bb898558SAl Viro unsigned int *ecx, unsigned int *edx) 586bb898558SAl Viro { 587bb898558SAl Viro *eax = op; 588bb898558SAl Viro *ecx = count; 589bb898558SAl Viro __cpuid(eax, ebx, ecx, edx); 590bb898558SAl Viro } 591bb898558SAl Viro 592bb898558SAl Viro /* 593bb898558SAl Viro * CPUID functions returning a single datum 594bb898558SAl Viro */ 595bb898558SAl Viro static inline unsigned int cpuid_eax(unsigned int op) 596bb898558SAl Viro { 597bb898558SAl Viro unsigned int eax, ebx, ecx, edx; 598bb898558SAl Viro 599bb898558SAl Viro cpuid(op, &eax, &ebx, &ecx, &edx); 600bb898558SAl Viro 601bb898558SAl Viro return eax; 602bb898558SAl Viro } 603bb898558SAl Viro 604bb898558SAl Viro static inline unsigned int cpuid_ebx(unsigned int op) 605bb898558SAl Viro { 606bb898558SAl Viro unsigned int eax, ebx, ecx, edx; 607bb898558SAl Viro 608bb898558SAl Viro cpuid(op, &eax, &ebx, &ecx, &edx); 609bb898558SAl Viro 610bb898558SAl Viro return ebx; 611bb898558SAl Viro } 612bb898558SAl Viro 613bb898558SAl Viro static inline unsigned int cpuid_ecx(unsigned int op) 614bb898558SAl Viro { 615bb898558SAl Viro unsigned int eax, ebx, ecx, edx; 616bb898558SAl Viro 617bb898558SAl Viro cpuid(op, &eax, &ebx, &ecx, &edx); 618bb898558SAl Viro 619bb898558SAl Viro return ecx; 620bb898558SAl Viro } 621bb898558SAl Viro 622bb898558SAl Viro static inline unsigned int cpuid_edx(unsigned int op) 623bb898558SAl Viro { 624bb898558SAl Viro unsigned int eax, ebx, ecx, edx; 625bb898558SAl Viro 626bb898558SAl Viro cpuid(op, &eax, &ebx, &ecx, &edx); 627bb898558SAl Viro 628bb898558SAl Viro return edx; 629bb898558SAl Viro } 630bb898558SAl Viro 631bb898558SAl Viro /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */ 6320b101e62SDenys Vlasenko static __always_inline void rep_nop(void) 633bb898558SAl Viro { 634bb898558SAl Viro asm volatile("rep; nop" ::: "memory"); 635bb898558SAl Viro } 636bb898558SAl Viro 6370b101e62SDenys Vlasenko static __always_inline void cpu_relax(void) 638bb898558SAl Viro { 639bb898558SAl Viro rep_nop(); 640bb898558SAl Viro } 641bb898558SAl Viro 642c198b121SAndy Lutomirski /* 643c198b121SAndy Lutomirski * This function forces the icache and prefetched instruction stream to 644c198b121SAndy Lutomirski * catch up with reality in two very specific cases: 645c198b121SAndy Lutomirski * 646c198b121SAndy Lutomirski * a) Text was modified using one virtual address and is about to be executed 647c198b121SAndy Lutomirski * from the same physical page at a different virtual address. 648c198b121SAndy Lutomirski * 649c198b121SAndy Lutomirski * b) Text was modified on a different CPU, may subsequently be 650c198b121SAndy Lutomirski * executed on this CPU, and you want to make sure the new version 651c198b121SAndy Lutomirski * gets executed. This generally means you're calling this in a IPI. 652c198b121SAndy Lutomirski * 653c198b121SAndy Lutomirski * If you're calling this for a different reason, you're probably doing 654c198b121SAndy Lutomirski * it wrong. 655c198b121SAndy Lutomirski */ 656bb898558SAl Viro static inline void sync_core(void) 657bb898558SAl Viro { 658c198b121SAndy Lutomirski /* 659c198b121SAndy Lutomirski * There are quite a few ways to do this. IRET-to-self is nice 660c198b121SAndy Lutomirski * because it works on every CPU, at any CPL (so it's compatible 661c198b121SAndy Lutomirski * with paravirtualization), and it never exits to a hypervisor. 662c198b121SAndy Lutomirski * The only down sides are that it's a bit slow (it seems to be 663c198b121SAndy Lutomirski * a bit more than 2x slower than the fastest options) and that 664c198b121SAndy Lutomirski * it unmasks NMIs. The "push %cs" is needed because, in 665c198b121SAndy Lutomirski * paravirtual environments, __KERNEL_CS may not be a valid CS 666c198b121SAndy Lutomirski * value when we do IRET directly. 667c198b121SAndy Lutomirski * 668c198b121SAndy Lutomirski * In case NMI unmasking or performance ever becomes a problem, 669c198b121SAndy Lutomirski * the next best option appears to be MOV-to-CR2 and an 670c198b121SAndy Lutomirski * unconditional jump. That sequence also works on all CPUs, 671ecda85e7SJuergen Gross * but it will fault at CPL3 (i.e. Xen PV). 672c198b121SAndy Lutomirski * 673c198b121SAndy Lutomirski * CPUID is the conventional way, but it's nasty: it doesn't 674c198b121SAndy Lutomirski * exist on some 486-like CPUs, and it usually exits to a 675c198b121SAndy Lutomirski * hypervisor. 676c198b121SAndy Lutomirski * 677c198b121SAndy Lutomirski * Like all of Linux's memory ordering operations, this is a 678c198b121SAndy Lutomirski * compiler barrier as well. 679c198b121SAndy Lutomirski */ 6801c52d859SAndy Lutomirski #ifdef CONFIG_X86_32 681c198b121SAndy Lutomirski asm volatile ( 682c198b121SAndy Lutomirski "pushfl\n\t" 683c198b121SAndy Lutomirski "pushl %%cs\n\t" 684c198b121SAndy Lutomirski "pushl $1f\n\t" 685c198b121SAndy Lutomirski "iret\n\t" 68645c39fb0SH. Peter Anvin "1:" 687*f5caf621SJosh Poimboeuf : ASM_CALL_CONSTRAINT : : "memory"); 68845c39fb0SH. Peter Anvin #else 689c198b121SAndy Lutomirski unsigned int tmp; 690c198b121SAndy Lutomirski 691c198b121SAndy Lutomirski asm volatile ( 69276846bf3SJosh Poimboeuf UNWIND_HINT_SAVE 693c198b121SAndy Lutomirski "mov %%ss, %0\n\t" 694c198b121SAndy Lutomirski "pushq %q0\n\t" 695c198b121SAndy Lutomirski "pushq %%rsp\n\t" 696c198b121SAndy Lutomirski "addq $8, (%%rsp)\n\t" 697c198b121SAndy Lutomirski "pushfq\n\t" 698c198b121SAndy Lutomirski "mov %%cs, %0\n\t" 699c198b121SAndy Lutomirski "pushq %q0\n\t" 700c198b121SAndy Lutomirski "pushq $1f\n\t" 701c198b121SAndy Lutomirski "iretq\n\t" 70276846bf3SJosh Poimboeuf UNWIND_HINT_RESTORE 703c198b121SAndy Lutomirski "1:" 704*f5caf621SJosh Poimboeuf : "=&r" (tmp), ASM_CALL_CONSTRAINT : : "cc", "memory"); 70545c39fb0SH. Peter Anvin #endif 706bb898558SAl Viro } 707bb898558SAl Viro 708bb898558SAl Viro extern void select_idle_routine(const struct cpuinfo_x86 *c); 70907c94a38SBorislav Petkov extern void amd_e400_c1e_apic_setup(void); 710bb898558SAl Viro 711bb898558SAl Viro extern unsigned long boot_option_idle_override; 712bb898558SAl Viro 713d1896049SThomas Renninger enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_NOMWAIT, 71469fb3676SLen Brown IDLE_POLL}; 715d1896049SThomas Renninger 716bb898558SAl Viro extern void enable_sep_cpu(void); 717bb898558SAl Viro extern int sysenter_setup(void); 718bb898558SAl Viro 71929c84391SJan Kiszka extern void early_trap_init(void); 7208170e6beSH. Peter Anvin void early_trap_pf_init(void); 72129c84391SJan Kiszka 722bb898558SAl Viro /* Defined in head.S */ 723bb898558SAl Viro extern struct desc_ptr early_gdt_descr; 724bb898558SAl Viro 725bb898558SAl Viro extern void cpu_set_gdt(int); 726552be871SBrian Gerst extern void switch_to_new_gdt(int); 72745fc8757SThomas Garnier extern void load_direct_gdt(int); 72869218e47SThomas Garnier extern void load_fixmap_gdt(int); 72911e3a840SJeremy Fitzhardinge extern void load_percpu_segment(int); 730bb898558SAl Viro extern void cpu_init(void); 731bb898558SAl Viro 732c2724775SMarkus Metzger static inline unsigned long get_debugctlmsr(void) 733c2724775SMarkus Metzger { 734c2724775SMarkus Metzger unsigned long debugctlmsr = 0; 735c2724775SMarkus Metzger 736c2724775SMarkus Metzger #ifndef CONFIG_X86_DEBUGCTLMSR 737c2724775SMarkus Metzger if (boot_cpu_data.x86 < 6) 738c2724775SMarkus Metzger return 0; 739c2724775SMarkus Metzger #endif 740c2724775SMarkus Metzger rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr); 741c2724775SMarkus Metzger 742c2724775SMarkus Metzger return debugctlmsr; 743c2724775SMarkus Metzger } 744c2724775SMarkus Metzger 745bb898558SAl Viro static inline void update_debugctlmsr(unsigned long debugctlmsr) 746bb898558SAl Viro { 747bb898558SAl Viro #ifndef CONFIG_X86_DEBUGCTLMSR 748bb898558SAl Viro if (boot_cpu_data.x86 < 6) 749bb898558SAl Viro return; 750bb898558SAl Viro #endif 751bb898558SAl Viro wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr); 752bb898558SAl Viro } 753bb898558SAl Viro 7549bd1190aSOleg Nesterov extern void set_task_blockstep(struct task_struct *task, bool on); 7559bd1190aSOleg Nesterov 756bb898558SAl Viro /* Boot loader type from the setup header: */ 757bb898558SAl Viro extern int bootloader_type; 7585031296cSH. Peter Anvin extern int bootloader_version; 759bb898558SAl Viro 760bb898558SAl Viro extern char ignore_fpu_irq; 761bb898558SAl Viro 762bb898558SAl Viro #define HAVE_ARCH_PICK_MMAP_LAYOUT 1 763bb898558SAl Viro #define ARCH_HAS_PREFETCHW 764bb898558SAl Viro #define ARCH_HAS_SPINLOCK_PREFETCH 765bb898558SAl Viro 766bb898558SAl Viro #ifdef CONFIG_X86_32 767a930dc45SBorislav Petkov # define BASE_PREFETCH "" 768bb898558SAl Viro # define ARCH_HAS_PREFETCH 769bb898558SAl Viro #else 770a930dc45SBorislav Petkov # define BASE_PREFETCH "prefetcht0 %P1" 771bb898558SAl Viro #endif 772bb898558SAl Viro 773bb898558SAl Viro /* 774bb898558SAl Viro * Prefetch instructions for Pentium III (+) and AMD Athlon (+) 775bb898558SAl Viro * 776bb898558SAl Viro * It's not worth to care about 3dnow prefetches for the K6 777bb898558SAl Viro * because they are microcoded there and very slow. 778bb898558SAl Viro */ 779bb898558SAl Viro static inline void prefetch(const void *x) 780bb898558SAl Viro { 781a930dc45SBorislav Petkov alternative_input(BASE_PREFETCH, "prefetchnta %P1", 782bb898558SAl Viro X86_FEATURE_XMM, 783a930dc45SBorislav Petkov "m" (*(const char *)x)); 784bb898558SAl Viro } 785bb898558SAl Viro 786bb898558SAl Viro /* 787bb898558SAl Viro * 3dnow prefetch to get an exclusive cache line. 788bb898558SAl Viro * Useful for spinlocks to avoid one state transition in the 789bb898558SAl Viro * cache coherency protocol: 790bb898558SAl Viro */ 791bb898558SAl Viro static inline void prefetchw(const void *x) 792bb898558SAl Viro { 793a930dc45SBorislav Petkov alternative_input(BASE_PREFETCH, "prefetchw %P1", 794a930dc45SBorislav Petkov X86_FEATURE_3DNOWPREFETCH, 795a930dc45SBorislav Petkov "m" (*(const char *)x)); 796bb898558SAl Viro } 797bb898558SAl Viro 798bb898558SAl Viro static inline void spin_lock_prefetch(const void *x) 799bb898558SAl Viro { 800bb898558SAl Viro prefetchw(x); 801bb898558SAl Viro } 802bb898558SAl Viro 803d9e05cc5SAndy Lutomirski #define TOP_OF_INIT_STACK ((unsigned long)&init_stack + sizeof(init_stack) - \ 804d9e05cc5SAndy Lutomirski TOP_OF_KERNEL_STACK_PADDING) 805d9e05cc5SAndy Lutomirski 806bb898558SAl Viro #ifdef CONFIG_X86_32 807bb898558SAl Viro /* 808bb898558SAl Viro * User space process size: 3GB (default). 809bb898558SAl Viro */ 8108f3e474fSDmitry Safonov #define IA32_PAGE_OFFSET PAGE_OFFSET 811bb898558SAl Viro #define TASK_SIZE PAGE_OFFSET 812b569bab7SKirill A. Shutemov #define TASK_SIZE_LOW TASK_SIZE 813d9517346SIngo Molnar #define TASK_SIZE_MAX TASK_SIZE 81444b04912SKirill A. Shutemov #define DEFAULT_MAP_WINDOW TASK_SIZE 815bb898558SAl Viro #define STACK_TOP TASK_SIZE 816bb898558SAl Viro #define STACK_TOP_MAX STACK_TOP 817bb898558SAl Viro 818bb898558SAl Viro #define INIT_THREAD { \ 819d9e05cc5SAndy Lutomirski .sp0 = TOP_OF_INIT_STACK, \ 820bb898558SAl Viro .sysenter_cs = __KERNEL_CS, \ 821bb898558SAl Viro .io_bitmap_ptr = NULL, \ 82213d4ea09SAndy Lutomirski .addr_limit = KERNEL_DS, \ 823bb898558SAl Viro } 824bb898558SAl Viro 825bb898558SAl Viro /* 8265c39403eSDenys Vlasenko * TOP_OF_KERNEL_STACK_PADDING reserves 8 bytes on top of the ring0 stack. 827bb898558SAl Viro * This is necessary to guarantee that the entire "struct pt_regs" 828b595076aSUwe Kleine-König * is accessible even if the CPU haven't stored the SS/ESP registers 829bb898558SAl Viro * on the stack (interrupt gate does not save these registers 830bb898558SAl Viro * when switching to the same priv ring). 831bb898558SAl Viro * Therefore beware: accessing the ss/esp fields of the 832bb898558SAl Viro * "struct pt_regs" is possible, but they may contain the 833bb898558SAl Viro * completely wrong values. 834bb898558SAl Viro */ 835bb898558SAl Viro #define task_pt_regs(task) \ 836bb898558SAl Viro ({ \ 8375c39403eSDenys Vlasenko unsigned long __ptr = (unsigned long)task_stack_page(task); \ 8385c39403eSDenys Vlasenko __ptr += THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING; \ 8395c39403eSDenys Vlasenko ((struct pt_regs *)__ptr) - 1; \ 840bb898558SAl Viro }) 841bb898558SAl Viro 842bb898558SAl Viro #define KSTK_ESP(task) (task_pt_regs(task)->sp) 843bb898558SAl Viro 844bb898558SAl Viro #else 845bb898558SAl Viro /* 84607114f0fSAndy Lutomirski * User space process size. 47bits minus one guard page. The guard 84707114f0fSAndy Lutomirski * page is necessary on Intel CPUs: if a SYSCALL instruction is at 84807114f0fSAndy Lutomirski * the highest possible canonical userspace address, then that 84907114f0fSAndy Lutomirski * syscall will enter the kernel with a non-canonical return 85007114f0fSAndy Lutomirski * address, and SYSRET will explode dangerously. We avoid this 85107114f0fSAndy Lutomirski * particular problem by preventing anything from being mapped 85207114f0fSAndy Lutomirski * at the maximum canonical address. 853bb898558SAl Viro */ 854ee00f4a3SKirill A. Shutemov #define TASK_SIZE_MAX ((1UL << __VIRTUAL_MASK_SHIFT) - PAGE_SIZE) 855bb898558SAl Viro 856ee00f4a3SKirill A. Shutemov #define DEFAULT_MAP_WINDOW ((1UL << 47) - PAGE_SIZE) 857bb898558SAl Viro 858bb898558SAl Viro /* This decides where the kernel will search for a free chunk of vm 859bb898558SAl Viro * space during mmap's. 860bb898558SAl Viro */ 861bb898558SAl Viro #define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? \ 862bb898558SAl Viro 0xc0000000 : 0xFFFFe000) 863bb898558SAl Viro 864b569bab7SKirill A. Shutemov #define TASK_SIZE_LOW (test_thread_flag(TIF_ADDR32) ? \ 865b569bab7SKirill A. Shutemov IA32_PAGE_OFFSET : DEFAULT_MAP_WINDOW) 8666bd33008SH. Peter Anvin #define TASK_SIZE (test_thread_flag(TIF_ADDR32) ? \ 867d9517346SIngo Molnar IA32_PAGE_OFFSET : TASK_SIZE_MAX) 8686bd33008SH. Peter Anvin #define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_ADDR32)) ? \ 869d9517346SIngo Molnar IA32_PAGE_OFFSET : TASK_SIZE_MAX) 870bb898558SAl Viro 871b569bab7SKirill A. Shutemov #define STACK_TOP TASK_SIZE_LOW 872d9517346SIngo Molnar #define STACK_TOP_MAX TASK_SIZE_MAX 873bb898558SAl Viro 874bb898558SAl Viro #define INIT_THREAD { \ 87513d4ea09SAndy Lutomirski .sp0 = TOP_OF_INIT_STACK, \ 87613d4ea09SAndy Lutomirski .addr_limit = KERNEL_DS, \ 877bb898558SAl Viro } 878bb898558SAl Viro 879bb898558SAl Viro #define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.sp0 - 1) 88089240ba0SStefani Seibold extern unsigned long KSTK_ESP(struct task_struct *task); 881d046ff8bSH. J. Lu 882bb898558SAl Viro #endif /* CONFIG_X86_64 */ 883bb898558SAl Viro 884bb898558SAl Viro extern void start_thread(struct pt_regs *regs, unsigned long new_ip, 885bb898558SAl Viro unsigned long new_sp); 886bb898558SAl Viro 887bb898558SAl Viro /* 888bb898558SAl Viro * This decides where the kernel will search for a free chunk of vm 889bb898558SAl Viro * space during mmap's. 890bb898558SAl Viro */ 8918f3e474fSDmitry Safonov #define __TASK_UNMAPPED_BASE(task_size) (PAGE_ALIGN(task_size / 3)) 892b569bab7SKirill A. Shutemov #define TASK_UNMAPPED_BASE __TASK_UNMAPPED_BASE(TASK_SIZE_LOW) 893bb898558SAl Viro 894bb898558SAl Viro #define KSTK_EIP(task) (task_pt_regs(task)->ip) 895bb898558SAl Viro 896bb898558SAl Viro /* Get/set a process' ability to use the timestamp counter instruction */ 897bb898558SAl Viro #define GET_TSC_CTL(adr) get_tsc_mode((adr)) 898bb898558SAl Viro #define SET_TSC_CTL(val) set_tsc_mode((val)) 899bb898558SAl Viro 900bb898558SAl Viro extern int get_tsc_mode(unsigned long adr); 901bb898558SAl Viro extern int set_tsc_mode(unsigned int val); 902bb898558SAl Viro 903e9ea1e7fSKyle Huey DECLARE_PER_CPU(u64, msr_misc_features_shadow); 904e9ea1e7fSKyle Huey 905fe3d197fSDave Hansen /* Register/unregister a process' MPX related resource */ 90646a6e0cfSDave Hansen #define MPX_ENABLE_MANAGEMENT() mpx_enable_management() 90746a6e0cfSDave Hansen #define MPX_DISABLE_MANAGEMENT() mpx_disable_management() 908fe3d197fSDave Hansen 909fe3d197fSDave Hansen #ifdef CONFIG_X86_INTEL_MPX 91046a6e0cfSDave Hansen extern int mpx_enable_management(void); 91146a6e0cfSDave Hansen extern int mpx_disable_management(void); 912fe3d197fSDave Hansen #else 91346a6e0cfSDave Hansen static inline int mpx_enable_management(void) 914fe3d197fSDave Hansen { 915fe3d197fSDave Hansen return -EINVAL; 916fe3d197fSDave Hansen } 91746a6e0cfSDave Hansen static inline int mpx_disable_management(void) 918fe3d197fSDave Hansen { 919fe3d197fSDave Hansen return -EINVAL; 920fe3d197fSDave Hansen } 921fe3d197fSDave Hansen #endif /* CONFIG_X86_INTEL_MPX */ 922fe3d197fSDave Hansen 923bc8e80d5SBorislav Petkov #ifdef CONFIG_CPU_SUP_AMD 9248b84c8dfSDaniel J Blueman extern u16 amd_get_nb_id(int cpu); 925cc2749e4SAravind Gopalakrishnan extern u32 amd_get_nodes_per_socket(void); 926bc8e80d5SBorislav Petkov #else 927bc8e80d5SBorislav Petkov static inline u16 amd_get_nb_id(int cpu) { return 0; } 928bc8e80d5SBorislav Petkov static inline u32 amd_get_nodes_per_socket(void) { return 0; } 929bc8e80d5SBorislav Petkov #endif 9306a812691SAndreas Herrmann 93196e39ac0SJason Wang static inline uint32_t hypervisor_cpuid_base(const char *sig, uint32_t leaves) 93296e39ac0SJason Wang { 93396e39ac0SJason Wang uint32_t base, eax, signature[3]; 93496e39ac0SJason Wang 93596e39ac0SJason Wang for (base = 0x40000000; base < 0x40010000; base += 0x100) { 93696e39ac0SJason Wang cpuid(base, &eax, &signature[0], &signature[1], &signature[2]); 93796e39ac0SJason Wang 93896e39ac0SJason Wang if (!memcmp(sig, signature, 12) && 93996e39ac0SJason Wang (leaves == 0 || ((eax - base) >= leaves))) 94096e39ac0SJason Wang return base; 94196e39ac0SJason Wang } 94296e39ac0SJason Wang 94396e39ac0SJason Wang return 0; 94496e39ac0SJason Wang } 94596e39ac0SJason Wang 946f05e798aSDavid Howells extern unsigned long arch_align_stack(unsigned long sp); 947f05e798aSDavid Howells extern void free_init_pages(char *what, unsigned long begin, unsigned long end); 948f05e798aSDavid Howells 949f05e798aSDavid Howells void default_idle(void); 9506a377ddcSLen Brown #ifdef CONFIG_XEN 9516a377ddcSLen Brown bool xen_set_default_idle(void); 9526a377ddcSLen Brown #else 9536a377ddcSLen Brown #define xen_set_default_idle 0 9546a377ddcSLen Brown #endif 955f05e798aSDavid Howells 956f05e798aSDavid Howells void stop_this_cpu(void *dummy); 9574d067d8eSBorislav Petkov void df_debug(struct pt_regs *regs, long error_code); 9581965aae3SH. Peter Anvin #endif /* _ASM_X86_PROCESSOR_H */ 959