11965aae3SH. Peter Anvin #ifndef _ASM_X86_PROCESSOR_H 21965aae3SH. Peter Anvin #define _ASM_X86_PROCESSOR_H 3bb898558SAl Viro 4bb898558SAl Viro #include <asm/processor-flags.h> 5bb898558SAl Viro 6bb898558SAl Viro /* Forward declaration, a strange C thing */ 7bb898558SAl Viro struct task_struct; 8bb898558SAl Viro struct mm_struct; 9bb898558SAl Viro 10bb898558SAl Viro #include <asm/vm86.h> 11bb898558SAl Viro #include <asm/math_emu.h> 12bb898558SAl Viro #include <asm/segment.h> 13bb898558SAl Viro #include <asm/types.h> 14bb898558SAl Viro #include <asm/sigcontext.h> 15bb898558SAl Viro #include <asm/current.h> 16bb898558SAl Viro #include <asm/cpufeature.h> 17bb898558SAl Viro #include <asm/page.h> 1854321d94SJeremy Fitzhardinge #include <asm/pgtable_types.h> 19bb898558SAl Viro #include <asm/percpu.h> 20bb898558SAl Viro #include <asm/msr.h> 21bb898558SAl Viro #include <asm/desc_defs.h> 22bb898558SAl Viro #include <asm/nops.h> 23f05e798aSDavid Howells #include <asm/special_insns.h> 24bb898558SAl Viro 25bb898558SAl Viro #include <linux/personality.h> 26bb898558SAl Viro #include <linux/cpumask.h> 27bb898558SAl Viro #include <linux/cache.h> 28bb898558SAl Viro #include <linux/threads.h> 295cbc19a9SPeter Zijlstra #include <linux/math64.h> 30bb898558SAl Viro #include <linux/init.h> 31faa4602eSPeter Zijlstra #include <linux/err.h> 32f05e798aSDavid Howells #include <linux/irqflags.h> 33f05e798aSDavid Howells 34f05e798aSDavid Howells /* 35f05e798aSDavid Howells * We handle most unaligned accesses in hardware. On the other hand 36f05e798aSDavid Howells * unaligned DMA can be quite expensive on some Nehalem processors. 37f05e798aSDavid Howells * 38f05e798aSDavid Howells * Based on this we disable the IP header alignment in network drivers. 39f05e798aSDavid Howells */ 40f05e798aSDavid Howells #define NET_IP_ALIGN 0 41bb898558SAl Viro 42b332828cSK.Prasad #define HBP_NUM 4 43bb898558SAl Viro /* 44bb898558SAl Viro * Default implementation of macro that returns current 45bb898558SAl Viro * instruction pointer ("program counter"). 46bb898558SAl Viro */ 47bb898558SAl Viro static inline void *current_text_addr(void) 48bb898558SAl Viro { 49bb898558SAl Viro void *pc; 50bb898558SAl Viro 51bb898558SAl Viro asm volatile("mov $1f, %0; 1:":"=r" (pc)); 52bb898558SAl Viro 53bb898558SAl Viro return pc; 54bb898558SAl Viro } 55bb898558SAl Viro 56bb898558SAl Viro #ifdef CONFIG_X86_VSMP 57bb898558SAl Viro # define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT) 58bb898558SAl Viro # define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT) 59bb898558SAl Viro #else 60bb898558SAl Viro # define ARCH_MIN_TASKALIGN 16 61bb898558SAl Viro # define ARCH_MIN_MMSTRUCT_ALIGN 0 62bb898558SAl Viro #endif 63bb898558SAl Viro 64e0ba94f1SAlex Shi enum tlb_infos { 65e0ba94f1SAlex Shi ENTRIES, 66e0ba94f1SAlex Shi NR_INFO 67e0ba94f1SAlex Shi }; 68e0ba94f1SAlex Shi 69e0ba94f1SAlex Shi extern u16 __read_mostly tlb_lli_4k[NR_INFO]; 70e0ba94f1SAlex Shi extern u16 __read_mostly tlb_lli_2m[NR_INFO]; 71e0ba94f1SAlex Shi extern u16 __read_mostly tlb_lli_4m[NR_INFO]; 72e0ba94f1SAlex Shi extern u16 __read_mostly tlb_lld_4k[NR_INFO]; 73e0ba94f1SAlex Shi extern u16 __read_mostly tlb_lld_2m[NR_INFO]; 74e0ba94f1SAlex Shi extern u16 __read_mostly tlb_lld_4m[NR_INFO]; 75c4211f42SAlex Shi extern s8 __read_mostly tlb_flushall_shift; 76c4211f42SAlex Shi 77bb898558SAl Viro /* 78bb898558SAl Viro * CPU type and hardware bug flags. Kept separately for each CPU. 79bb898558SAl Viro * Members of this structure are referenced in head.S, so think twice 80bb898558SAl Viro * before touching them. [mj] 81bb898558SAl Viro */ 82bb898558SAl Viro 83bb898558SAl Viro struct cpuinfo_x86 { 84bb898558SAl Viro __u8 x86; /* CPU family */ 85bb898558SAl Viro __u8 x86_vendor; /* CPU vendor */ 86bb898558SAl Viro __u8 x86_model; 87bb898558SAl Viro __u8 x86_mask; 88bb898558SAl Viro #ifdef CONFIG_X86_32 89bb898558SAl Viro char wp_works_ok; /* It doesn't on 386's */ 90bb898558SAl Viro 91bb898558SAl Viro /* Problems on some 486Dx4's and old 386's: */ 92bb898558SAl Viro char rfu; 93bb898558SAl Viro char pad0; 9460e019ebSH. Peter Anvin char pad1; 95bb898558SAl Viro #else 96bb898558SAl Viro /* Number of 4K pages in DTLB/ITLB combined(in pages): */ 97bb898558SAl Viro int x86_tlbsize; 9813c6c532SJan Beulich #endif 99bb898558SAl Viro __u8 x86_virt_bits; 100bb898558SAl Viro __u8 x86_phys_bits; 101bb898558SAl Viro /* CPUID returned core id bits: */ 102bb898558SAl Viro __u8 x86_coreid_bits; 103bb898558SAl Viro /* Max extended CPUID function supported: */ 104bb898558SAl Viro __u32 extended_cpuid_level; 105bb898558SAl Viro /* Maximum supported CPUID level, -1=no CPUID: */ 106bb898558SAl Viro int cpuid_level; 10765fc985bSBorislav Petkov __u32 x86_capability[NCAPINTS + NBUGINTS]; 108bb898558SAl Viro char x86_vendor_id[16]; 109bb898558SAl Viro char x86_model_id[64]; 110bb898558SAl Viro /* in KB - valid for CPUS which support this call: */ 111bb898558SAl Viro int x86_cache_size; 112bb898558SAl Viro int x86_cache_alignment; /* In bytes */ 113bb898558SAl Viro int x86_power; 114bb898558SAl Viro unsigned long loops_per_jiffy; 115bb898558SAl Viro /* cpuid returned max cores value: */ 116bb898558SAl Viro u16 x86_max_cores; 117bb898558SAl Viro u16 apicid; 118bb898558SAl Viro u16 initial_apicid; 119bb898558SAl Viro u16 x86_clflush_size; 120bb898558SAl Viro /* number of cores as seen by the OS: */ 121bb898558SAl Viro u16 booted_cores; 122bb898558SAl Viro /* Physical processor id: */ 123bb898558SAl Viro u16 phys_proc_id; 124bb898558SAl Viro /* Core id: */ 125bb898558SAl Viro u16 cpu_core_id; 1266057b4d3SAndreas Herrmann /* Compute unit id */ 1276057b4d3SAndreas Herrmann u8 compute_unit_id; 128bb898558SAl Viro /* Index into per_cpu list: */ 129bb898558SAl Viro u16 cpu_index; 130506ed6b5SAndi Kleen u32 microcode; 131bb898558SAl Viro } __attribute__((__aligned__(SMP_CACHE_BYTES))); 132bb898558SAl Viro 133bb898558SAl Viro #define X86_VENDOR_INTEL 0 134bb898558SAl Viro #define X86_VENDOR_CYRIX 1 135bb898558SAl Viro #define X86_VENDOR_AMD 2 136bb898558SAl Viro #define X86_VENDOR_UMC 3 137bb898558SAl Viro #define X86_VENDOR_CENTAUR 5 138bb898558SAl Viro #define X86_VENDOR_TRANSMETA 7 139bb898558SAl Viro #define X86_VENDOR_NSC 8 140bb898558SAl Viro #define X86_VENDOR_NUM 9 141bb898558SAl Viro 142bb898558SAl Viro #define X86_VENDOR_UNKNOWN 0xff 143bb898558SAl Viro 144bb898558SAl Viro /* 145bb898558SAl Viro * capabilities of CPUs 146bb898558SAl Viro */ 147bb898558SAl Viro extern struct cpuinfo_x86 boot_cpu_data; 148bb898558SAl Viro extern struct cpuinfo_x86 new_cpu_data; 149bb898558SAl Viro 150bb898558SAl Viro extern struct tss_struct doublefault_tss; 1513e0c3737SYinghai Lu extern __u32 cpu_caps_cleared[NCAPINTS]; 1523e0c3737SYinghai Lu extern __u32 cpu_caps_set[NCAPINTS]; 153bb898558SAl Viro 154bb898558SAl Viro #ifdef CONFIG_SMP 1559b8de747SDavid Howells DECLARE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info); 156bb898558SAl Viro #define cpu_data(cpu) per_cpu(cpu_info, cpu) 157bb898558SAl Viro #else 1587b543a53STejun Heo #define cpu_info boot_cpu_data 159bb898558SAl Viro #define cpu_data(cpu) boot_cpu_data 160bb898558SAl Viro #endif 161bb898558SAl Viro 162bb898558SAl Viro extern const struct seq_operations cpuinfo_op; 163bb898558SAl Viro 164bb898558SAl Viro #define cache_line_size() (boot_cpu_data.x86_cache_alignment) 165bb898558SAl Viro 166bb898558SAl Viro extern void cpu_detect(struct cpuinfo_x86 *c); 167148f9bb8SPaul Gortmaker extern void fpu_detect(struct cpuinfo_x86 *c); 168bb898558SAl Viro 169bb898558SAl Viro extern void early_cpu_init(void); 170bb898558SAl Viro extern void identify_boot_cpu(void); 171bb898558SAl Viro extern void identify_secondary_cpu(struct cpuinfo_x86 *); 172bb898558SAl Viro extern void print_cpu_info(struct cpuinfo_x86 *); 17321c3fcf3SYinghai Lu void print_cpu_msr(struct cpuinfo_x86 *); 174bb898558SAl Viro extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c); 175bb898558SAl Viro extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c); 17604a15418SAndreas Herrmann extern void init_amd_cacheinfo(struct cpuinfo_x86 *c); 177bb898558SAl Viro 178bb898558SAl Viro extern void detect_extended_topology(struct cpuinfo_x86 *c); 179bb898558SAl Viro extern void detect_ht(struct cpuinfo_x86 *c); 180bb898558SAl Viro 181d288e1cfSFenghua Yu #ifdef CONFIG_X86_32 182d288e1cfSFenghua Yu extern int have_cpuid_p(void); 183d288e1cfSFenghua Yu #else 184d288e1cfSFenghua Yu static inline int have_cpuid_p(void) 185d288e1cfSFenghua Yu { 186d288e1cfSFenghua Yu return 1; 187d288e1cfSFenghua Yu } 188d288e1cfSFenghua Yu #endif 189bb898558SAl Viro static inline void native_cpuid(unsigned int *eax, unsigned int *ebx, 190bb898558SAl Viro unsigned int *ecx, unsigned int *edx) 191bb898558SAl Viro { 192bb898558SAl Viro /* ecx is often an input as well as an output. */ 19345a94d7cSSuresh Siddha asm volatile("cpuid" 194bb898558SAl Viro : "=a" (*eax), 195bb898558SAl Viro "=b" (*ebx), 196bb898558SAl Viro "=c" (*ecx), 197bb898558SAl Viro "=d" (*edx) 198506ed6b5SAndi Kleen : "0" (*eax), "2" (*ecx) 199506ed6b5SAndi Kleen : "memory"); 200bb898558SAl Viro } 201bb898558SAl Viro 202bb898558SAl Viro static inline void load_cr3(pgd_t *pgdir) 203bb898558SAl Viro { 204bb898558SAl Viro write_cr3(__pa(pgdir)); 205bb898558SAl Viro } 206bb898558SAl Viro 207bb898558SAl Viro #ifdef CONFIG_X86_32 208bb898558SAl Viro /* This is the TSS defined by the hardware. */ 209bb898558SAl Viro struct x86_hw_tss { 210bb898558SAl Viro unsigned short back_link, __blh; 211bb898558SAl Viro unsigned long sp0; 212bb898558SAl Viro unsigned short ss0, __ss0h; 213bb898558SAl Viro unsigned long sp1; 214bb898558SAl Viro /* ss1 caches MSR_IA32_SYSENTER_CS: */ 215bb898558SAl Viro unsigned short ss1, __ss1h; 216bb898558SAl Viro unsigned long sp2; 217bb898558SAl Viro unsigned short ss2, __ss2h; 218bb898558SAl Viro unsigned long __cr3; 219bb898558SAl Viro unsigned long ip; 220bb898558SAl Viro unsigned long flags; 221bb898558SAl Viro unsigned long ax; 222bb898558SAl Viro unsigned long cx; 223bb898558SAl Viro unsigned long dx; 224bb898558SAl Viro unsigned long bx; 225bb898558SAl Viro unsigned long sp; 226bb898558SAl Viro unsigned long bp; 227bb898558SAl Viro unsigned long si; 228bb898558SAl Viro unsigned long di; 229bb898558SAl Viro unsigned short es, __esh; 230bb898558SAl Viro unsigned short cs, __csh; 231bb898558SAl Viro unsigned short ss, __ssh; 232bb898558SAl Viro unsigned short ds, __dsh; 233bb898558SAl Viro unsigned short fs, __fsh; 234bb898558SAl Viro unsigned short gs, __gsh; 235bb898558SAl Viro unsigned short ldt, __ldth; 236bb898558SAl Viro unsigned short trace; 237bb898558SAl Viro unsigned short io_bitmap_base; 238bb898558SAl Viro 239bb898558SAl Viro } __attribute__((packed)); 240bb898558SAl Viro #else 241bb898558SAl Viro struct x86_hw_tss { 242bb898558SAl Viro u32 reserved1; 243bb898558SAl Viro u64 sp0; 244bb898558SAl Viro u64 sp1; 245bb898558SAl Viro u64 sp2; 246bb898558SAl Viro u64 reserved2; 247bb898558SAl Viro u64 ist[7]; 248bb898558SAl Viro u32 reserved3; 249bb898558SAl Viro u32 reserved4; 250bb898558SAl Viro u16 reserved5; 251bb898558SAl Viro u16 io_bitmap_base; 252bb898558SAl Viro 253bb898558SAl Viro } __attribute__((packed)) ____cacheline_aligned; 254bb898558SAl Viro #endif 255bb898558SAl Viro 256bb898558SAl Viro /* 257bb898558SAl Viro * IO-bitmap sizes: 258bb898558SAl Viro */ 259bb898558SAl Viro #define IO_BITMAP_BITS 65536 260bb898558SAl Viro #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8) 261bb898558SAl Viro #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long)) 262bb898558SAl Viro #define IO_BITMAP_OFFSET offsetof(struct tss_struct, io_bitmap) 263bb898558SAl Viro #define INVALID_IO_BITMAP_OFFSET 0x8000 264bb898558SAl Viro 265bb898558SAl Viro struct tss_struct { 266bb898558SAl Viro /* 267bb898558SAl Viro * The hardware state: 268bb898558SAl Viro */ 269bb898558SAl Viro struct x86_hw_tss x86_tss; 270bb898558SAl Viro 271bb898558SAl Viro /* 272bb898558SAl Viro * The extra 1 is there because the CPU will access an 273bb898558SAl Viro * additional byte beyond the end of the IO permission 274bb898558SAl Viro * bitmap. The extra byte must be all 1 bits, and must 275bb898558SAl Viro * be within the limit. 276bb898558SAl Viro */ 277bb898558SAl Viro unsigned long io_bitmap[IO_BITMAP_LONGS + 1]; 278bb898558SAl Viro 279bb898558SAl Viro /* 280bb898558SAl Viro * .. and then another 0x100 bytes for the emergency kernel stack: 281bb898558SAl Viro */ 282bb898558SAl Viro unsigned long stack[64]; 283bb898558SAl Viro 284bb898558SAl Viro } ____cacheline_aligned; 285bb898558SAl Viro 2869b8de747SDavid Howells DECLARE_PER_CPU_SHARED_ALIGNED(struct tss_struct, init_tss); 287bb898558SAl Viro 288bb898558SAl Viro /* 289bb898558SAl Viro * Save the original ist values for checking stack pointers during debugging 290bb898558SAl Viro */ 291bb898558SAl Viro struct orig_ist { 292bb898558SAl Viro unsigned long ist[7]; 293bb898558SAl Viro }; 294bb898558SAl Viro 295bb898558SAl Viro #define MXCSR_DEFAULT 0x1f80 296bb898558SAl Viro 297bb898558SAl Viro struct i387_fsave_struct { 298bb898558SAl Viro u32 cwd; /* FPU Control Word */ 299bb898558SAl Viro u32 swd; /* FPU Status Word */ 300bb898558SAl Viro u32 twd; /* FPU Tag Word */ 301bb898558SAl Viro u32 fip; /* FPU IP Offset */ 302bb898558SAl Viro u32 fcs; /* FPU IP Selector */ 303bb898558SAl Viro u32 foo; /* FPU Operand Pointer Offset */ 304bb898558SAl Viro u32 fos; /* FPU Operand Pointer Selector */ 305bb898558SAl Viro 306bb898558SAl Viro /* 8*10 bytes for each FP-reg = 80 bytes: */ 307bb898558SAl Viro u32 st_space[20]; 308bb898558SAl Viro 309bb898558SAl Viro /* Software status information [not touched by FSAVE ]: */ 310bb898558SAl Viro u32 status; 311bb898558SAl Viro }; 312bb898558SAl Viro 313bb898558SAl Viro struct i387_fxsave_struct { 314bb898558SAl Viro u16 cwd; /* Control Word */ 315bb898558SAl Viro u16 swd; /* Status Word */ 316bb898558SAl Viro u16 twd; /* Tag Word */ 317bb898558SAl Viro u16 fop; /* Last Instruction Opcode */ 318bb898558SAl Viro union { 319bb898558SAl Viro struct { 320bb898558SAl Viro u64 rip; /* Instruction Pointer */ 321bb898558SAl Viro u64 rdp; /* Data Pointer */ 322bb898558SAl Viro }; 323bb898558SAl Viro struct { 324bb898558SAl Viro u32 fip; /* FPU IP Offset */ 325bb898558SAl Viro u32 fcs; /* FPU IP Selector */ 326bb898558SAl Viro u32 foo; /* FPU Operand Offset */ 327bb898558SAl Viro u32 fos; /* FPU Operand Selector */ 328bb898558SAl Viro }; 329bb898558SAl Viro }; 330bb898558SAl Viro u32 mxcsr; /* MXCSR Register State */ 331bb898558SAl Viro u32 mxcsr_mask; /* MXCSR Mask */ 332bb898558SAl Viro 333bb898558SAl Viro /* 8*16 bytes for each FP-reg = 128 bytes: */ 334bb898558SAl Viro u32 st_space[32]; 335bb898558SAl Viro 336bb898558SAl Viro /* 16*16 bytes for each XMM-reg = 256 bytes: */ 337bb898558SAl Viro u32 xmm_space[64]; 338bb898558SAl Viro 339bb898558SAl Viro u32 padding[12]; 340bb898558SAl Viro 341bb898558SAl Viro union { 342bb898558SAl Viro u32 padding1[12]; 343bb898558SAl Viro u32 sw_reserved[12]; 344bb898558SAl Viro }; 345bb898558SAl Viro 346bb898558SAl Viro } __attribute__((aligned(16))); 347bb898558SAl Viro 348bb898558SAl Viro struct i387_soft_struct { 349bb898558SAl Viro u32 cwd; 350bb898558SAl Viro u32 swd; 351bb898558SAl Viro u32 twd; 352bb898558SAl Viro u32 fip; 353bb898558SAl Viro u32 fcs; 354bb898558SAl Viro u32 foo; 355bb898558SAl Viro u32 fos; 356bb898558SAl Viro /* 8*10 bytes for each FP-reg = 80 bytes: */ 357bb898558SAl Viro u32 st_space[20]; 358bb898558SAl Viro u8 ftop; 359bb898558SAl Viro u8 changed; 360bb898558SAl Viro u8 lookahead; 361bb898558SAl Viro u8 no_update; 362bb898558SAl Viro u8 rm; 363bb898558SAl Viro u8 alimit; 364ae6af41fSTejun Heo struct math_emu_info *info; 365bb898558SAl Viro u32 entry_eip; 366bb898558SAl Viro }; 367bb898558SAl Viro 368a30469e7SSuresh Siddha struct ymmh_struct { 369a30469e7SSuresh Siddha /* 16 * 16 bytes for each YMMH-reg = 256 bytes */ 370a30469e7SSuresh Siddha u32 ymmh_space[64]; 371a30469e7SSuresh Siddha }; 372a30469e7SSuresh Siddha 373bb898558SAl Viro struct xsave_hdr_struct { 374bb898558SAl Viro u64 xstate_bv; 375bb898558SAl Viro u64 reserved1[2]; 376bb898558SAl Viro u64 reserved2[5]; 377bb898558SAl Viro } __attribute__((packed)); 378bb898558SAl Viro 379bb898558SAl Viro struct xsave_struct { 380bb898558SAl Viro struct i387_fxsave_struct i387; 381bb898558SAl Viro struct xsave_hdr_struct xsave_hdr; 382a30469e7SSuresh Siddha struct ymmh_struct ymmh; 383bb898558SAl Viro /* new processor state extensions will go here */ 384bb898558SAl Viro } __attribute__ ((packed, aligned (64))); 385bb898558SAl Viro 386bb898558SAl Viro union thread_xstate { 387bb898558SAl Viro struct i387_fsave_struct fsave; 388bb898558SAl Viro struct i387_fxsave_struct fxsave; 389bb898558SAl Viro struct i387_soft_struct soft; 390bb898558SAl Viro struct xsave_struct xsave; 391bb898558SAl Viro }; 392bb898558SAl Viro 39386603283SAvi Kivity struct fpu { 3947e16838dSLinus Torvalds unsigned int last_cpu; 3957e16838dSLinus Torvalds unsigned int has_fpu; 39686603283SAvi Kivity union thread_xstate *state; 39786603283SAvi Kivity }; 39886603283SAvi Kivity 399bb898558SAl Viro #ifdef CONFIG_X86_64 400bb898558SAl Viro DECLARE_PER_CPU(struct orig_ist, orig_ist); 40126f80bd6SBrian Gerst 402947e76cdSBrian Gerst union irq_stack_union { 403947e76cdSBrian Gerst char irq_stack[IRQ_STACK_SIZE]; 404947e76cdSBrian Gerst /* 405947e76cdSBrian Gerst * GCC hardcodes the stack canary as %gs:40. Since the 406947e76cdSBrian Gerst * irq_stack is the object at %gs:0, we reserve the bottom 407947e76cdSBrian Gerst * 48 bytes of the irq stack for the canary. 408947e76cdSBrian Gerst */ 409947e76cdSBrian Gerst struct { 410947e76cdSBrian Gerst char gs_base[40]; 411947e76cdSBrian Gerst unsigned long stack_canary; 412947e76cdSBrian Gerst }; 413947e76cdSBrian Gerst }; 414947e76cdSBrian Gerst 415277d5b40SAndi Kleen DECLARE_PER_CPU_FIRST(union irq_stack_union, irq_stack_union) __visible; 4162add8e23SBrian Gerst DECLARE_INIT_PER_CPU(irq_stack_union); 4172add8e23SBrian Gerst 41826f80bd6SBrian Gerst DECLARE_PER_CPU(char *, irq_stack_ptr); 4199766cdbcSJaswinder Singh Rajput DECLARE_PER_CPU(unsigned int, irq_count); 4209766cdbcSJaswinder Singh Rajput extern asmlinkage void ignore_sysret(void); 42160a5317fSTejun Heo #else /* X86_64 */ 42260a5317fSTejun Heo #ifdef CONFIG_CC_STACKPROTECTOR 4231ea0d14eSJeremy Fitzhardinge /* 4241ea0d14eSJeremy Fitzhardinge * Make sure stack canary segment base is cached-aligned: 4251ea0d14eSJeremy Fitzhardinge * "For Intel Atom processors, avoid non zero segment base address 4261ea0d14eSJeremy Fitzhardinge * that is not aligned to cache line boundary at all cost." 4271ea0d14eSJeremy Fitzhardinge * (Optim Ref Manual Assembly/Compiler Coding Rule 15.) 4281ea0d14eSJeremy Fitzhardinge */ 4291ea0d14eSJeremy Fitzhardinge struct stack_canary { 4301ea0d14eSJeremy Fitzhardinge char __pad[20]; /* canary at %gs:20 */ 4311ea0d14eSJeremy Fitzhardinge unsigned long canary; 4321ea0d14eSJeremy Fitzhardinge }; 43353f82452SJeremy Fitzhardinge DECLARE_PER_CPU_ALIGNED(struct stack_canary, stack_canary); 434bb898558SAl Viro #endif 43560a5317fSTejun Heo #endif /* X86_64 */ 436bb898558SAl Viro 437bb898558SAl Viro extern unsigned int xstate_size; 438bb898558SAl Viro extern void free_thread_xstate(struct task_struct *); 439bb898558SAl Viro extern struct kmem_cache *task_xstate_cachep; 440bb898558SAl Viro 44124f1e32cSFrederic Weisbecker struct perf_event; 44224f1e32cSFrederic Weisbecker 443bb898558SAl Viro struct thread_struct { 444bb898558SAl Viro /* Cached TLS descriptors: */ 445bb898558SAl Viro struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES]; 446bb898558SAl Viro unsigned long sp0; 447bb898558SAl Viro unsigned long sp; 448bb898558SAl Viro #ifdef CONFIG_X86_32 449bb898558SAl Viro unsigned long sysenter_cs; 450bb898558SAl Viro #else 451bb898558SAl Viro unsigned long usersp; /* Copy from PDA */ 452bb898558SAl Viro unsigned short es; 453bb898558SAl Viro unsigned short ds; 454bb898558SAl Viro unsigned short fsindex; 455bb898558SAl Viro unsigned short gsindex; 456bb898558SAl Viro #endif 4570c23590fSAlexey Dobriyan #ifdef CONFIG_X86_32 458bb898558SAl Viro unsigned long ip; 4590c23590fSAlexey Dobriyan #endif 460d756f4adSAlexey Dobriyan #ifdef CONFIG_X86_64 461bb898558SAl Viro unsigned long fs; 462d756f4adSAlexey Dobriyan #endif 463bb898558SAl Viro unsigned long gs; 46424f1e32cSFrederic Weisbecker /* Save middle states of ptrace breakpoints */ 46524f1e32cSFrederic Weisbecker struct perf_event *ptrace_bps[HBP_NUM]; 46624f1e32cSFrederic Weisbecker /* Debug status used for traps, single steps, etc... */ 467bb898558SAl Viro unsigned long debugreg6; 468326264a0SFrederic Weisbecker /* Keep track of the exact dr7 value set by the user */ 469326264a0SFrederic Weisbecker unsigned long ptrace_dr7; 470bb898558SAl Viro /* Fault info: */ 471bb898558SAl Viro unsigned long cr2; 47251e7dc70SSrikar Dronamraju unsigned long trap_nr; 473bb898558SAl Viro unsigned long error_code; 474bb898558SAl Viro /* floating point and extended processor state */ 47586603283SAvi Kivity struct fpu fpu; 476bb898558SAl Viro #ifdef CONFIG_X86_32 477bb898558SAl Viro /* Virtual 86 mode info */ 478bb898558SAl Viro struct vm86_struct __user *vm86_info; 479bb898558SAl Viro unsigned long screen_bitmap; 480bb898558SAl Viro unsigned long v86flags; 481bb898558SAl Viro unsigned long v86mask; 482bb898558SAl Viro unsigned long saved_sp0; 483bb898558SAl Viro unsigned int saved_fs; 484bb898558SAl Viro unsigned int saved_gs; 485bb898558SAl Viro #endif 486bb898558SAl Viro /* IO permissions: */ 487bb898558SAl Viro unsigned long *io_bitmap_ptr; 488bb898558SAl Viro unsigned long iopl; 489bb898558SAl Viro /* Max allowed port in the bitmap, in bytes: */ 490bb898558SAl Viro unsigned io_bitmap_max; 491*c375f15aSVineet Gupta /* 492*c375f15aSVineet Gupta * fpu_counter contains the number of consecutive context switches 493*c375f15aSVineet Gupta * that the FPU is used. If this is over a threshold, the lazy fpu 494*c375f15aSVineet Gupta * saving becomes unlazy to save the trap. This is an unsigned char 495*c375f15aSVineet Gupta * so that after 256 times the counter wraps and the behavior turns 496*c375f15aSVineet Gupta * lazy again; this to deal with bursty apps that only use FPU for 497*c375f15aSVineet Gupta * a short time 498*c375f15aSVineet Gupta */ 499*c375f15aSVineet Gupta unsigned char fpu_counter; 500bb898558SAl Viro }; 501bb898558SAl Viro 502bb898558SAl Viro /* 503bb898558SAl Viro * Set IOPL bits in EFLAGS from given mask 504bb898558SAl Viro */ 505bb898558SAl Viro static inline void native_set_iopl_mask(unsigned mask) 506bb898558SAl Viro { 507bb898558SAl Viro #ifdef CONFIG_X86_32 508bb898558SAl Viro unsigned int reg; 509bb898558SAl Viro 510bb898558SAl Viro asm volatile ("pushfl;" 511bb898558SAl Viro "popl %0;" 512bb898558SAl Viro "andl %1, %0;" 513bb898558SAl Viro "orl %2, %0;" 514bb898558SAl Viro "pushl %0;" 515bb898558SAl Viro "popfl" 516bb898558SAl Viro : "=&r" (reg) 517bb898558SAl Viro : "i" (~X86_EFLAGS_IOPL), "r" (mask)); 518bb898558SAl Viro #endif 519bb898558SAl Viro } 520bb898558SAl Viro 521bb898558SAl Viro static inline void 522bb898558SAl Viro native_load_sp0(struct tss_struct *tss, struct thread_struct *thread) 523bb898558SAl Viro { 524bb898558SAl Viro tss->x86_tss.sp0 = thread->sp0; 525bb898558SAl Viro #ifdef CONFIG_X86_32 526bb898558SAl Viro /* Only happens when SEP is enabled, no need to test "SEP"arately: */ 527bb898558SAl Viro if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) { 528bb898558SAl Viro tss->x86_tss.ss1 = thread->sysenter_cs; 529bb898558SAl Viro wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0); 530bb898558SAl Viro } 531bb898558SAl Viro #endif 532bb898558SAl Viro } 533bb898558SAl Viro 534bb898558SAl Viro static inline void native_swapgs(void) 535bb898558SAl Viro { 536bb898558SAl Viro #ifdef CONFIG_X86_64 537bb898558SAl Viro asm volatile("swapgs" ::: "memory"); 538bb898558SAl Viro #endif 539bb898558SAl Viro } 540bb898558SAl Viro 541bb898558SAl Viro #ifdef CONFIG_PARAVIRT 542bb898558SAl Viro #include <asm/paravirt.h> 543bb898558SAl Viro #else 544bb898558SAl Viro #define __cpuid native_cpuid 545bb898558SAl Viro #define paravirt_enabled() 0 546bb898558SAl Viro 547bb898558SAl Viro static inline void load_sp0(struct tss_struct *tss, 548bb898558SAl Viro struct thread_struct *thread) 549bb898558SAl Viro { 550bb898558SAl Viro native_load_sp0(tss, thread); 551bb898558SAl Viro } 552bb898558SAl Viro 553bb898558SAl Viro #define set_iopl_mask native_set_iopl_mask 554bb898558SAl Viro #endif /* CONFIG_PARAVIRT */ 555bb898558SAl Viro 556bb898558SAl Viro /* 557bb898558SAl Viro * Save the cr4 feature set we're using (ie 558bb898558SAl Viro * Pentium 4MB enable and PPro Global page 559bb898558SAl Viro * enable), so that any CPU's that boot up 560bb898558SAl Viro * after us can get the correct flags. 561bb898558SAl Viro */ 562bb898558SAl Viro extern unsigned long mmu_cr4_features; 563cda846f1SJarkko Sakkinen extern u32 *trampoline_cr4_features; 564bb898558SAl Viro 565bb898558SAl Viro static inline void set_in_cr4(unsigned long mask) 566bb898558SAl Viro { 5672df7a6e9SBrian Gerst unsigned long cr4; 568bb898558SAl Viro 569bb898558SAl Viro mmu_cr4_features |= mask; 570cda846f1SJarkko Sakkinen if (trampoline_cr4_features) 571cda846f1SJarkko Sakkinen *trampoline_cr4_features = mmu_cr4_features; 572bb898558SAl Viro cr4 = read_cr4(); 573bb898558SAl Viro cr4 |= mask; 574bb898558SAl Viro write_cr4(cr4); 575bb898558SAl Viro } 576bb898558SAl Viro 577bb898558SAl Viro static inline void clear_in_cr4(unsigned long mask) 578bb898558SAl Viro { 5792df7a6e9SBrian Gerst unsigned long cr4; 580bb898558SAl Viro 581bb898558SAl Viro mmu_cr4_features &= ~mask; 582cda846f1SJarkko Sakkinen if (trampoline_cr4_features) 583cda846f1SJarkko Sakkinen *trampoline_cr4_features = mmu_cr4_features; 584bb898558SAl Viro cr4 = read_cr4(); 585bb898558SAl Viro cr4 &= ~mask; 586bb898558SAl Viro write_cr4(cr4); 587bb898558SAl Viro } 588bb898558SAl Viro 589bb898558SAl Viro typedef struct { 590bb898558SAl Viro unsigned long seg; 591bb898558SAl Viro } mm_segment_t; 592bb898558SAl Viro 593bb898558SAl Viro 594bb898558SAl Viro /* Free all resources held by a thread. */ 595bb898558SAl Viro extern void release_thread(struct task_struct *); 596bb898558SAl Viro 597bb898558SAl Viro unsigned long get_wchan(struct task_struct *p); 598bb898558SAl Viro 599bb898558SAl Viro /* 600bb898558SAl Viro * Generic CPUID function 601bb898558SAl Viro * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx 602bb898558SAl Viro * resulting in stale register contents being returned. 603bb898558SAl Viro */ 604bb898558SAl Viro static inline void cpuid(unsigned int op, 605bb898558SAl Viro unsigned int *eax, unsigned int *ebx, 606bb898558SAl Viro unsigned int *ecx, unsigned int *edx) 607bb898558SAl Viro { 608bb898558SAl Viro *eax = op; 609bb898558SAl Viro *ecx = 0; 610bb898558SAl Viro __cpuid(eax, ebx, ecx, edx); 611bb898558SAl Viro } 612bb898558SAl Viro 613bb898558SAl Viro /* Some CPUID calls want 'count' to be placed in ecx */ 614bb898558SAl Viro static inline void cpuid_count(unsigned int op, int count, 615bb898558SAl Viro unsigned int *eax, unsigned int *ebx, 616bb898558SAl Viro unsigned int *ecx, unsigned int *edx) 617bb898558SAl Viro { 618bb898558SAl Viro *eax = op; 619bb898558SAl Viro *ecx = count; 620bb898558SAl Viro __cpuid(eax, ebx, ecx, edx); 621bb898558SAl Viro } 622bb898558SAl Viro 623bb898558SAl Viro /* 624bb898558SAl Viro * CPUID functions returning a single datum 625bb898558SAl Viro */ 626bb898558SAl Viro static inline unsigned int cpuid_eax(unsigned int op) 627bb898558SAl Viro { 628bb898558SAl Viro unsigned int eax, ebx, ecx, edx; 629bb898558SAl Viro 630bb898558SAl Viro cpuid(op, &eax, &ebx, &ecx, &edx); 631bb898558SAl Viro 632bb898558SAl Viro return eax; 633bb898558SAl Viro } 634bb898558SAl Viro 635bb898558SAl Viro static inline unsigned int cpuid_ebx(unsigned int op) 636bb898558SAl Viro { 637bb898558SAl Viro unsigned int eax, ebx, ecx, edx; 638bb898558SAl Viro 639bb898558SAl Viro cpuid(op, &eax, &ebx, &ecx, &edx); 640bb898558SAl Viro 641bb898558SAl Viro return ebx; 642bb898558SAl Viro } 643bb898558SAl Viro 644bb898558SAl Viro static inline unsigned int cpuid_ecx(unsigned int op) 645bb898558SAl Viro { 646bb898558SAl Viro unsigned int eax, ebx, ecx, edx; 647bb898558SAl Viro 648bb898558SAl Viro cpuid(op, &eax, &ebx, &ecx, &edx); 649bb898558SAl Viro 650bb898558SAl Viro return ecx; 651bb898558SAl Viro } 652bb898558SAl Viro 653bb898558SAl Viro static inline unsigned int cpuid_edx(unsigned int op) 654bb898558SAl Viro { 655bb898558SAl Viro unsigned int eax, ebx, ecx, edx; 656bb898558SAl Viro 657bb898558SAl Viro cpuid(op, &eax, &ebx, &ecx, &edx); 658bb898558SAl Viro 659bb898558SAl Viro return edx; 660bb898558SAl Viro } 661bb898558SAl Viro 662bb898558SAl Viro /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */ 663bb898558SAl Viro static inline void rep_nop(void) 664bb898558SAl Viro { 665bb898558SAl Viro asm volatile("rep; nop" ::: "memory"); 666bb898558SAl Viro } 667bb898558SAl Viro 668bb898558SAl Viro static inline void cpu_relax(void) 669bb898558SAl Viro { 670bb898558SAl Viro rep_nop(); 671bb898558SAl Viro } 672bb898558SAl Viro 6735367b688SBen Hutchings /* Stop speculative execution and prefetching of modified code. */ 674bb898558SAl Viro static inline void sync_core(void) 675bb898558SAl Viro { 676bb898558SAl Viro int tmp; 677bb898558SAl Viro 678eb068e78SH. Peter Anvin #ifdef CONFIG_M486 67945c39fb0SH. Peter Anvin /* 68045c39fb0SH. Peter Anvin * Do a CPUID if available, otherwise do a jump. The jump 68145c39fb0SH. Peter Anvin * can conveniently enough be the jump around CPUID. 68245c39fb0SH. Peter Anvin */ 68345c39fb0SH. Peter Anvin asm volatile("cmpl %2,%1\n\t" 68445c39fb0SH. Peter Anvin "jl 1f\n\t" 68545c39fb0SH. Peter Anvin "cpuid\n" 68645c39fb0SH. Peter Anvin "1:" 68745c39fb0SH. Peter Anvin : "=a" (tmp) 68845c39fb0SH. Peter Anvin : "rm" (boot_cpu_data.cpuid_level), "ri" (0), "0" (1) 689bb898558SAl Viro : "ebx", "ecx", "edx", "memory"); 69045c39fb0SH. Peter Anvin #else 69145c39fb0SH. Peter Anvin /* 69245c39fb0SH. Peter Anvin * CPUID is a barrier to speculative execution. 69345c39fb0SH. Peter Anvin * Prefetched instructions are automatically 69445c39fb0SH. Peter Anvin * invalidated when modified. 69545c39fb0SH. Peter Anvin */ 69645c39fb0SH. Peter Anvin asm volatile("cpuid" 69745c39fb0SH. Peter Anvin : "=a" (tmp) 69845c39fb0SH. Peter Anvin : "0" (1) 69945c39fb0SH. Peter Anvin : "ebx", "ecx", "edx", "memory"); 70045c39fb0SH. Peter Anvin #endif 701bb898558SAl Viro } 702bb898558SAl Viro 703bb898558SAl Viro static inline void __monitor(const void *eax, unsigned long ecx, 704bb898558SAl Viro unsigned long edx) 705bb898558SAl Viro { 706bb898558SAl Viro /* "monitor %eax, %ecx, %edx;" */ 707bb898558SAl Viro asm volatile(".byte 0x0f, 0x01, 0xc8;" 708bb898558SAl Viro :: "a" (eax), "c" (ecx), "d"(edx)); 709bb898558SAl Viro } 710bb898558SAl Viro 711bb898558SAl Viro static inline void __mwait(unsigned long eax, unsigned long ecx) 712bb898558SAl Viro { 713bb898558SAl Viro /* "mwait %eax, %ecx;" */ 714bb898558SAl Viro asm volatile(".byte 0x0f, 0x01, 0xc9;" 715bb898558SAl Viro :: "a" (eax), "c" (ecx)); 716bb898558SAl Viro } 717bb898558SAl Viro 718bb898558SAl Viro static inline void __sti_mwait(unsigned long eax, unsigned long ecx) 719bb898558SAl Viro { 720bb898558SAl Viro trace_hardirqs_on(); 721bb898558SAl Viro /* "mwait %eax, %ecx;" */ 722bb898558SAl Viro asm volatile("sti; .byte 0x0f, 0x01, 0xc9;" 723bb898558SAl Viro :: "a" (eax), "c" (ecx)); 724bb898558SAl Viro } 725bb898558SAl Viro 726bb898558SAl Viro extern void select_idle_routine(const struct cpuinfo_x86 *c); 72702c68a02SLen Brown extern void init_amd_e400_c1e_mask(void); 728bb898558SAl Viro 729bb898558SAl Viro extern unsigned long boot_option_idle_override; 73002c68a02SLen Brown extern bool amd_e400_c1e_detected; 731bb898558SAl Viro 732d1896049SThomas Renninger enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_NOMWAIT, 73369fb3676SLen Brown IDLE_POLL}; 734d1896049SThomas Renninger 735bb898558SAl Viro extern void enable_sep_cpu(void); 736bb898558SAl Viro extern int sysenter_setup(void); 737bb898558SAl Viro 73829c84391SJan Kiszka extern void early_trap_init(void); 7398170e6beSH. Peter Anvin void early_trap_pf_init(void); 74029c84391SJan Kiszka 741bb898558SAl Viro /* Defined in head.S */ 742bb898558SAl Viro extern struct desc_ptr early_gdt_descr; 743bb898558SAl Viro 744bb898558SAl Viro extern void cpu_set_gdt(int); 745552be871SBrian Gerst extern void switch_to_new_gdt(int); 74611e3a840SJeremy Fitzhardinge extern void load_percpu_segment(int); 747bb898558SAl Viro extern void cpu_init(void); 748bb898558SAl Viro 749c2724775SMarkus Metzger static inline unsigned long get_debugctlmsr(void) 750c2724775SMarkus Metzger { 751c2724775SMarkus Metzger unsigned long debugctlmsr = 0; 752c2724775SMarkus Metzger 753c2724775SMarkus Metzger #ifndef CONFIG_X86_DEBUGCTLMSR 754c2724775SMarkus Metzger if (boot_cpu_data.x86 < 6) 755c2724775SMarkus Metzger return 0; 756c2724775SMarkus Metzger #endif 757c2724775SMarkus Metzger rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr); 758c2724775SMarkus Metzger 759c2724775SMarkus Metzger return debugctlmsr; 760c2724775SMarkus Metzger } 761c2724775SMarkus Metzger 762bb898558SAl Viro static inline void update_debugctlmsr(unsigned long debugctlmsr) 763bb898558SAl Viro { 764bb898558SAl Viro #ifndef CONFIG_X86_DEBUGCTLMSR 765bb898558SAl Viro if (boot_cpu_data.x86 < 6) 766bb898558SAl Viro return; 767bb898558SAl Viro #endif 768bb898558SAl Viro wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr); 769bb898558SAl Viro } 770bb898558SAl Viro 7719bd1190aSOleg Nesterov extern void set_task_blockstep(struct task_struct *task, bool on); 7729bd1190aSOleg Nesterov 773bb898558SAl Viro /* 774bb898558SAl Viro * from system description table in BIOS. Mostly for MCA use, but 775bb898558SAl Viro * others may find it useful: 776bb898558SAl Viro */ 777bb898558SAl Viro extern unsigned int machine_id; 778bb898558SAl Viro extern unsigned int machine_submodel_id; 779bb898558SAl Viro extern unsigned int BIOS_revision; 780bb898558SAl Viro 781bb898558SAl Viro /* Boot loader type from the setup header: */ 782bb898558SAl Viro extern int bootloader_type; 7835031296cSH. Peter Anvin extern int bootloader_version; 784bb898558SAl Viro 785bb898558SAl Viro extern char ignore_fpu_irq; 786bb898558SAl Viro 787bb898558SAl Viro #define HAVE_ARCH_PICK_MMAP_LAYOUT 1 788bb898558SAl Viro #define ARCH_HAS_PREFETCHW 789bb898558SAl Viro #define ARCH_HAS_SPINLOCK_PREFETCH 790bb898558SAl Viro 791bb898558SAl Viro #ifdef CONFIG_X86_32 792bb898558SAl Viro # define BASE_PREFETCH ASM_NOP4 793bb898558SAl Viro # define ARCH_HAS_PREFETCH 794bb898558SAl Viro #else 795bb898558SAl Viro # define BASE_PREFETCH "prefetcht0 (%1)" 796bb898558SAl Viro #endif 797bb898558SAl Viro 798bb898558SAl Viro /* 799bb898558SAl Viro * Prefetch instructions for Pentium III (+) and AMD Athlon (+) 800bb898558SAl Viro * 801bb898558SAl Viro * It's not worth to care about 3dnow prefetches for the K6 802bb898558SAl Viro * because they are microcoded there and very slow. 803bb898558SAl Viro */ 804bb898558SAl Viro static inline void prefetch(const void *x) 805bb898558SAl Viro { 806bb898558SAl Viro alternative_input(BASE_PREFETCH, 807bb898558SAl Viro "prefetchnta (%1)", 808bb898558SAl Viro X86_FEATURE_XMM, 809bb898558SAl Viro "r" (x)); 810bb898558SAl Viro } 811bb898558SAl Viro 812bb898558SAl Viro /* 813bb898558SAl Viro * 3dnow prefetch to get an exclusive cache line. 814bb898558SAl Viro * Useful for spinlocks to avoid one state transition in the 815bb898558SAl Viro * cache coherency protocol: 816bb898558SAl Viro */ 817bb898558SAl Viro static inline void prefetchw(const void *x) 818bb898558SAl Viro { 819bb898558SAl Viro alternative_input(BASE_PREFETCH, 820bb898558SAl Viro "prefetchw (%1)", 821bb898558SAl Viro X86_FEATURE_3DNOW, 822bb898558SAl Viro "r" (x)); 823bb898558SAl Viro } 824bb898558SAl Viro 825bb898558SAl Viro static inline void spin_lock_prefetch(const void *x) 826bb898558SAl Viro { 827bb898558SAl Viro prefetchw(x); 828bb898558SAl Viro } 829bb898558SAl Viro 830bb898558SAl Viro #ifdef CONFIG_X86_32 831bb898558SAl Viro /* 832bb898558SAl Viro * User space process size: 3GB (default). 833bb898558SAl Viro */ 834bb898558SAl Viro #define TASK_SIZE PAGE_OFFSET 835d9517346SIngo Molnar #define TASK_SIZE_MAX TASK_SIZE 836bb898558SAl Viro #define STACK_TOP TASK_SIZE 837bb898558SAl Viro #define STACK_TOP_MAX STACK_TOP 838bb898558SAl Viro 839bb898558SAl Viro #define INIT_THREAD { \ 840bb898558SAl Viro .sp0 = sizeof(init_stack) + (long)&init_stack, \ 841bb898558SAl Viro .vm86_info = NULL, \ 842bb898558SAl Viro .sysenter_cs = __KERNEL_CS, \ 843bb898558SAl Viro .io_bitmap_ptr = NULL, \ 844bb898558SAl Viro } 845bb898558SAl Viro 846bb898558SAl Viro /* 847bb898558SAl Viro * Note that the .io_bitmap member must be extra-big. This is because 848bb898558SAl Viro * the CPU will access an additional byte beyond the end of the IO 849bb898558SAl Viro * permission bitmap. The extra byte must be all 1 bits, and must 850bb898558SAl Viro * be within the limit. 851bb898558SAl Viro */ 852bb898558SAl Viro #define INIT_TSS { \ 853bb898558SAl Viro .x86_tss = { \ 854bb898558SAl Viro .sp0 = sizeof(init_stack) + (long)&init_stack, \ 855bb898558SAl Viro .ss0 = __KERNEL_DS, \ 856bb898558SAl Viro .ss1 = __KERNEL_CS, \ 857bb898558SAl Viro .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, \ 858bb898558SAl Viro }, \ 859bb898558SAl Viro .io_bitmap = { [0 ... IO_BITMAP_LONGS] = ~0 }, \ 860bb898558SAl Viro } 861bb898558SAl Viro 862bb898558SAl Viro extern unsigned long thread_saved_pc(struct task_struct *tsk); 863bb898558SAl Viro 864bb898558SAl Viro #define THREAD_SIZE_LONGS (THREAD_SIZE/sizeof(unsigned long)) 865bb898558SAl Viro #define KSTK_TOP(info) \ 866bb898558SAl Viro ({ \ 867bb898558SAl Viro unsigned long *__ptr = (unsigned long *)(info); \ 868bb898558SAl Viro (unsigned long)(&__ptr[THREAD_SIZE_LONGS]); \ 869bb898558SAl Viro }) 870bb898558SAl Viro 871bb898558SAl Viro /* 872bb898558SAl Viro * The below -8 is to reserve 8 bytes on top of the ring0 stack. 873bb898558SAl Viro * This is necessary to guarantee that the entire "struct pt_regs" 874b595076aSUwe Kleine-König * is accessible even if the CPU haven't stored the SS/ESP registers 875bb898558SAl Viro * on the stack (interrupt gate does not save these registers 876bb898558SAl Viro * when switching to the same priv ring). 877bb898558SAl Viro * Therefore beware: accessing the ss/esp fields of the 878bb898558SAl Viro * "struct pt_regs" is possible, but they may contain the 879bb898558SAl Viro * completely wrong values. 880bb898558SAl Viro */ 881bb898558SAl Viro #define task_pt_regs(task) \ 882bb898558SAl Viro ({ \ 883bb898558SAl Viro struct pt_regs *__regs__; \ 884bb898558SAl Viro __regs__ = (struct pt_regs *)(KSTK_TOP(task_stack_page(task))-8); \ 885bb898558SAl Viro __regs__ - 1; \ 886bb898558SAl Viro }) 887bb898558SAl Viro 888bb898558SAl Viro #define KSTK_ESP(task) (task_pt_regs(task)->sp) 889bb898558SAl Viro 890bb898558SAl Viro #else 891bb898558SAl Viro /* 892bb898558SAl Viro * User space process size. 47bits minus one guard page. 893bb898558SAl Viro */ 894d9517346SIngo Molnar #define TASK_SIZE_MAX ((1UL << 47) - PAGE_SIZE) 895bb898558SAl Viro 896bb898558SAl Viro /* This decides where the kernel will search for a free chunk of vm 897bb898558SAl Viro * space during mmap's. 898bb898558SAl Viro */ 899bb898558SAl Viro #define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? \ 900bb898558SAl Viro 0xc0000000 : 0xFFFFe000) 901bb898558SAl Viro 9026bd33008SH. Peter Anvin #define TASK_SIZE (test_thread_flag(TIF_ADDR32) ? \ 903d9517346SIngo Molnar IA32_PAGE_OFFSET : TASK_SIZE_MAX) 9046bd33008SH. Peter Anvin #define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_ADDR32)) ? \ 905d9517346SIngo Molnar IA32_PAGE_OFFSET : TASK_SIZE_MAX) 906bb898558SAl Viro 907bb898558SAl Viro #define STACK_TOP TASK_SIZE 908d9517346SIngo Molnar #define STACK_TOP_MAX TASK_SIZE_MAX 909bb898558SAl Viro 910bb898558SAl Viro #define INIT_THREAD { \ 911bb898558SAl Viro .sp0 = (unsigned long)&init_stack + sizeof(init_stack) \ 912bb898558SAl Viro } 913bb898558SAl Viro 914bb898558SAl Viro #define INIT_TSS { \ 915bb898558SAl Viro .x86_tss.sp0 = (unsigned long)&init_stack + sizeof(init_stack) \ 916bb898558SAl Viro } 917bb898558SAl Viro 918bb898558SAl Viro /* 919bb898558SAl Viro * Return saved PC of a blocked thread. 920bb898558SAl Viro * What is this good for? it will be always the scheduler or ret_from_fork. 921bb898558SAl Viro */ 922bb898558SAl Viro #define thread_saved_pc(t) (*(unsigned long *)((t)->thread.sp - 8)) 923bb898558SAl Viro 924bb898558SAl Viro #define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.sp0 - 1) 92589240ba0SStefani Seibold extern unsigned long KSTK_ESP(struct task_struct *task); 926d046ff8bSH. J. Lu 927d046ff8bSH. J. Lu /* 928d046ff8bSH. J. Lu * User space RSP while inside the SYSCALL fast path 929d046ff8bSH. J. Lu */ 930d046ff8bSH. J. Lu DECLARE_PER_CPU(unsigned long, old_rsp); 931d046ff8bSH. J. Lu 932bb898558SAl Viro #endif /* CONFIG_X86_64 */ 933bb898558SAl Viro 934bb898558SAl Viro extern void start_thread(struct pt_regs *regs, unsigned long new_ip, 935bb898558SAl Viro unsigned long new_sp); 936bb898558SAl Viro 937bb898558SAl Viro /* 938bb898558SAl Viro * This decides where the kernel will search for a free chunk of vm 939bb898558SAl Viro * space during mmap's. 940bb898558SAl Viro */ 941bb898558SAl Viro #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3)) 942bb898558SAl Viro 943bb898558SAl Viro #define KSTK_EIP(task) (task_pt_regs(task)->ip) 944bb898558SAl Viro 945bb898558SAl Viro /* Get/set a process' ability to use the timestamp counter instruction */ 946bb898558SAl Viro #define GET_TSC_CTL(adr) get_tsc_mode((adr)) 947bb898558SAl Viro #define SET_TSC_CTL(val) set_tsc_mode((val)) 948bb898558SAl Viro 949bb898558SAl Viro extern int get_tsc_mode(unsigned long adr); 950bb898558SAl Viro extern int set_tsc_mode(unsigned int val); 951bb898558SAl Viro 9528b84c8dfSDaniel J Blueman extern u16 amd_get_nb_id(int cpu); 9536a812691SAndreas Herrmann 95496e39ac0SJason Wang static inline uint32_t hypervisor_cpuid_base(const char *sig, uint32_t leaves) 95596e39ac0SJason Wang { 95696e39ac0SJason Wang uint32_t base, eax, signature[3]; 95796e39ac0SJason Wang 95896e39ac0SJason Wang for (base = 0x40000000; base < 0x40010000; base += 0x100) { 95996e39ac0SJason Wang cpuid(base, &eax, &signature[0], &signature[1], &signature[2]); 96096e39ac0SJason Wang 96196e39ac0SJason Wang if (!memcmp(sig, signature, 12) && 96296e39ac0SJason Wang (leaves == 0 || ((eax - base) >= leaves))) 96396e39ac0SJason Wang return base; 96496e39ac0SJason Wang } 96596e39ac0SJason Wang 96696e39ac0SJason Wang return 0; 96796e39ac0SJason Wang } 96896e39ac0SJason Wang 969f05e798aSDavid Howells extern unsigned long arch_align_stack(unsigned long sp); 970f05e798aSDavid Howells extern void free_init_pages(char *what, unsigned long begin, unsigned long end); 971f05e798aSDavid Howells 972f05e798aSDavid Howells void default_idle(void); 9736a377ddcSLen Brown #ifdef CONFIG_XEN 9746a377ddcSLen Brown bool xen_set_default_idle(void); 9756a377ddcSLen Brown #else 9766a377ddcSLen Brown #define xen_set_default_idle 0 9776a377ddcSLen Brown #endif 978f05e798aSDavid Howells 979f05e798aSDavid Howells void stop_this_cpu(void *dummy); 9804d067d8eSBorislav Petkov void df_debug(struct pt_regs *regs, long error_code); 9811965aae3SH. Peter Anvin #endif /* _ASM_X86_PROCESSOR_H */ 982