11965aae3SH. Peter Anvin #ifndef _ASM_X86_PROCESSOR_H 21965aae3SH. Peter Anvin #define _ASM_X86_PROCESSOR_H 3bb898558SAl Viro 4bb898558SAl Viro #include <asm/processor-flags.h> 5bb898558SAl Viro 6bb898558SAl Viro /* Forward declaration, a strange C thing */ 7bb898558SAl Viro struct task_struct; 8bb898558SAl Viro struct mm_struct; 99fda6a06SBrian Gerst struct vm86; 10bb898558SAl Viro 11bb898558SAl Viro #include <asm/math_emu.h> 12bb898558SAl Viro #include <asm/segment.h> 13bb898558SAl Viro #include <asm/types.h> 14decb4c41SIngo Molnar #include <uapi/asm/sigcontext.h> 15bb898558SAl Viro #include <asm/current.h> 16cd4d09ecSBorislav Petkov #include <asm/cpufeatures.h> 17bb898558SAl Viro #include <asm/page.h> 1854321d94SJeremy Fitzhardinge #include <asm/pgtable_types.h> 19bb898558SAl Viro #include <asm/percpu.h> 20bb898558SAl Viro #include <asm/msr.h> 21bb898558SAl Viro #include <asm/desc_defs.h> 22bb898558SAl Viro #include <asm/nops.h> 23f05e798aSDavid Howells #include <asm/special_insns.h> 2414b9675aSIngo Molnar #include <asm/fpu/types.h> 25bb898558SAl Viro 26bb898558SAl Viro #include <linux/personality.h> 27bb898558SAl Viro #include <linux/cache.h> 28bb898558SAl Viro #include <linux/threads.h> 295cbc19a9SPeter Zijlstra #include <linux/math64.h> 30faa4602eSPeter Zijlstra #include <linux/err.h> 31f05e798aSDavid Howells #include <linux/irqflags.h> 32f05e798aSDavid Howells 33f05e798aSDavid Howells /* 34f05e798aSDavid Howells * We handle most unaligned accesses in hardware. On the other hand 35f05e798aSDavid Howells * unaligned DMA can be quite expensive on some Nehalem processors. 36f05e798aSDavid Howells * 37f05e798aSDavid Howells * Based on this we disable the IP header alignment in network drivers. 38f05e798aSDavid Howells */ 39f05e798aSDavid Howells #define NET_IP_ALIGN 0 40bb898558SAl Viro 41b332828cSK.Prasad #define HBP_NUM 4 42bb898558SAl Viro /* 43bb898558SAl Viro * Default implementation of macro that returns current 44bb898558SAl Viro * instruction pointer ("program counter"). 45bb898558SAl Viro */ 46bb898558SAl Viro static inline void *current_text_addr(void) 47bb898558SAl Viro { 48bb898558SAl Viro void *pc; 49bb898558SAl Viro 50bb898558SAl Viro asm volatile("mov $1f, %0; 1:":"=r" (pc)); 51bb898558SAl Viro 52bb898558SAl Viro return pc; 53bb898558SAl Viro } 54bb898558SAl Viro 55b8c1b8eaSIngo Molnar /* 56b8c1b8eaSIngo Molnar * These alignment constraints are for performance in the vSMP case, 57b8c1b8eaSIngo Molnar * but in the task_struct case we must also meet hardware imposed 58b8c1b8eaSIngo Molnar * alignment requirements of the FPU state: 59b8c1b8eaSIngo Molnar */ 60bb898558SAl Viro #ifdef CONFIG_X86_VSMP 61bb898558SAl Viro # define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT) 62bb898558SAl Viro # define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT) 63bb898558SAl Viro #else 64b8c1b8eaSIngo Molnar # define ARCH_MIN_TASKALIGN __alignof__(union fpregs_state) 65bb898558SAl Viro # define ARCH_MIN_MMSTRUCT_ALIGN 0 66bb898558SAl Viro #endif 67bb898558SAl Viro 68e0ba94f1SAlex Shi enum tlb_infos { 69e0ba94f1SAlex Shi ENTRIES, 70e0ba94f1SAlex Shi NR_INFO 71e0ba94f1SAlex Shi }; 72e0ba94f1SAlex Shi 73e0ba94f1SAlex Shi extern u16 __read_mostly tlb_lli_4k[NR_INFO]; 74e0ba94f1SAlex Shi extern u16 __read_mostly tlb_lli_2m[NR_INFO]; 75e0ba94f1SAlex Shi extern u16 __read_mostly tlb_lli_4m[NR_INFO]; 76e0ba94f1SAlex Shi extern u16 __read_mostly tlb_lld_4k[NR_INFO]; 77e0ba94f1SAlex Shi extern u16 __read_mostly tlb_lld_2m[NR_INFO]; 78e0ba94f1SAlex Shi extern u16 __read_mostly tlb_lld_4m[NR_INFO]; 79dd360393SKirill A. Shutemov extern u16 __read_mostly tlb_lld_1g[NR_INFO]; 80c4211f42SAlex Shi 81bb898558SAl Viro /* 82bb898558SAl Viro * CPU type and hardware bug flags. Kept separately for each CPU. 83bb898558SAl Viro * Members of this structure are referenced in head.S, so think twice 84bb898558SAl Viro * before touching them. [mj] 85bb898558SAl Viro */ 86bb898558SAl Viro 87bb898558SAl Viro struct cpuinfo_x86 { 88bb898558SAl Viro __u8 x86; /* CPU family */ 89bb898558SAl Viro __u8 x86_vendor; /* CPU vendor */ 90bb898558SAl Viro __u8 x86_model; 91bb898558SAl Viro __u8 x86_mask; 92bb898558SAl Viro #ifdef CONFIG_X86_32 93bb898558SAl Viro char wp_works_ok; /* It doesn't on 386's */ 94bb898558SAl Viro 95bb898558SAl Viro /* Problems on some 486Dx4's and old 386's: */ 96bb898558SAl Viro char rfu; 97bb898558SAl Viro char pad0; 9860e019ebSH. Peter Anvin char pad1; 99bb898558SAl Viro #else 100bb898558SAl Viro /* Number of 4K pages in DTLB/ITLB combined(in pages): */ 101bb898558SAl Viro int x86_tlbsize; 10213c6c532SJan Beulich #endif 103bb898558SAl Viro __u8 x86_virt_bits; 104bb898558SAl Viro __u8 x86_phys_bits; 105bb898558SAl Viro /* CPUID returned core id bits: */ 106bb898558SAl Viro __u8 x86_coreid_bits; 107bb898558SAl Viro /* Max extended CPUID function supported: */ 108bb898558SAl Viro __u32 extended_cpuid_level; 109bb898558SAl Viro /* Maximum supported CPUID level, -1=no CPUID: */ 110bb898558SAl Viro int cpuid_level; 11165fc985bSBorislav Petkov __u32 x86_capability[NCAPINTS + NBUGINTS]; 112bb898558SAl Viro char x86_vendor_id[16]; 113bb898558SAl Viro char x86_model_id[64]; 114bb898558SAl Viro /* in KB - valid for CPUS which support this call: */ 115bb898558SAl Viro int x86_cache_size; 116bb898558SAl Viro int x86_cache_alignment; /* In bytes */ 117cbc82b17SPeter P Waskiewicz Jr /* Cache QoS architectural values: */ 118cbc82b17SPeter P Waskiewicz Jr int x86_cache_max_rmid; /* max index */ 119cbc82b17SPeter P Waskiewicz Jr int x86_cache_occ_scale; /* scale to bytes */ 120bb898558SAl Viro int x86_power; 121bb898558SAl Viro unsigned long loops_per_jiffy; 122bb898558SAl Viro /* cpuid returned max cores value: */ 123bb898558SAl Viro u16 x86_max_cores; 124bb898558SAl Viro u16 apicid; 125bb898558SAl Viro u16 initial_apicid; 126bb898558SAl Viro u16 x86_clflush_size; 127bb898558SAl Viro /* number of cores as seen by the OS: */ 128bb898558SAl Viro u16 booted_cores; 129bb898558SAl Viro /* Physical processor id: */ 130bb898558SAl Viro u16 phys_proc_id; 1311f12e32fSThomas Gleixner /* Logical processor id: */ 1321f12e32fSThomas Gleixner u16 logical_proc_id; 133bb898558SAl Viro /* Core id: */ 134bb898558SAl Viro u16 cpu_core_id; 135bb898558SAl Viro /* Index into per_cpu list: */ 136bb898558SAl Viro u16 cpu_index; 137506ed6b5SAndi Kleen u32 microcode; 1382c773dd3SJan Beulich }; 139bb898558SAl Viro 140*47f10a36SHe Chen struct cpuid_regs { 141*47f10a36SHe Chen u32 eax, ebx, ecx, edx; 142*47f10a36SHe Chen }; 143*47f10a36SHe Chen 144*47f10a36SHe Chen enum cpuid_regs_idx { 145*47f10a36SHe Chen CPUID_EAX = 0, 146*47f10a36SHe Chen CPUID_EBX, 147*47f10a36SHe Chen CPUID_ECX, 148*47f10a36SHe Chen CPUID_EDX, 149*47f10a36SHe Chen }; 150*47f10a36SHe Chen 151bb898558SAl Viro #define X86_VENDOR_INTEL 0 152bb898558SAl Viro #define X86_VENDOR_CYRIX 1 153bb898558SAl Viro #define X86_VENDOR_AMD 2 154bb898558SAl Viro #define X86_VENDOR_UMC 3 155bb898558SAl Viro #define X86_VENDOR_CENTAUR 5 156bb898558SAl Viro #define X86_VENDOR_TRANSMETA 7 157bb898558SAl Viro #define X86_VENDOR_NSC 8 158bb898558SAl Viro #define X86_VENDOR_NUM 9 159bb898558SAl Viro 160bb898558SAl Viro #define X86_VENDOR_UNKNOWN 0xff 161bb898558SAl Viro 162bb898558SAl Viro /* 163bb898558SAl Viro * capabilities of CPUs 164bb898558SAl Viro */ 165bb898558SAl Viro extern struct cpuinfo_x86 boot_cpu_data; 166bb898558SAl Viro extern struct cpuinfo_x86 new_cpu_data; 167bb898558SAl Viro 168bb898558SAl Viro extern struct tss_struct doublefault_tss; 1693e0c3737SYinghai Lu extern __u32 cpu_caps_cleared[NCAPINTS]; 1703e0c3737SYinghai Lu extern __u32 cpu_caps_set[NCAPINTS]; 171bb898558SAl Viro 172bb898558SAl Viro #ifdef CONFIG_SMP 1732c773dd3SJan Beulich DECLARE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info); 174bb898558SAl Viro #define cpu_data(cpu) per_cpu(cpu_info, cpu) 175bb898558SAl Viro #else 1767b543a53STejun Heo #define cpu_info boot_cpu_data 177bb898558SAl Viro #define cpu_data(cpu) boot_cpu_data 178bb898558SAl Viro #endif 179bb898558SAl Viro 180bb898558SAl Viro extern const struct seq_operations cpuinfo_op; 181bb898558SAl Viro 182bb898558SAl Viro #define cache_line_size() (boot_cpu_data.x86_cache_alignment) 183bb898558SAl Viro 184bb898558SAl Viro extern void cpu_detect(struct cpuinfo_x86 *c); 185bb898558SAl Viro 186bb898558SAl Viro extern void early_cpu_init(void); 187bb898558SAl Viro extern void identify_boot_cpu(void); 188bb898558SAl Viro extern void identify_secondary_cpu(struct cpuinfo_x86 *); 189bb898558SAl Viro extern void print_cpu_info(struct cpuinfo_x86 *); 19021c3fcf3SYinghai Lu void print_cpu_msr(struct cpuinfo_x86 *); 191bb898558SAl Viro extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c); 192bb898558SAl Viro extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c); 19304a15418SAndreas Herrmann extern void init_amd_cacheinfo(struct cpuinfo_x86 *c); 194bb898558SAl Viro 195bb898558SAl Viro extern void detect_extended_topology(struct cpuinfo_x86 *c); 196bb898558SAl Viro extern void detect_ht(struct cpuinfo_x86 *c); 197bb898558SAl Viro 198d288e1cfSFenghua Yu #ifdef CONFIG_X86_32 199d288e1cfSFenghua Yu extern int have_cpuid_p(void); 200d288e1cfSFenghua Yu #else 201d288e1cfSFenghua Yu static inline int have_cpuid_p(void) 202d288e1cfSFenghua Yu { 203d288e1cfSFenghua Yu return 1; 204d288e1cfSFenghua Yu } 205d288e1cfSFenghua Yu #endif 206bb898558SAl Viro static inline void native_cpuid(unsigned int *eax, unsigned int *ebx, 207bb898558SAl Viro unsigned int *ecx, unsigned int *edx) 208bb898558SAl Viro { 209bb898558SAl Viro /* ecx is often an input as well as an output. */ 21045a94d7cSSuresh Siddha asm volatile("cpuid" 211bb898558SAl Viro : "=a" (*eax), 212bb898558SAl Viro "=b" (*ebx), 213bb898558SAl Viro "=c" (*ecx), 214bb898558SAl Viro "=d" (*edx) 215506ed6b5SAndi Kleen : "0" (*eax), "2" (*ecx) 216506ed6b5SAndi Kleen : "memory"); 217bb898558SAl Viro } 218bb898558SAl Viro 219bb898558SAl Viro static inline void load_cr3(pgd_t *pgdir) 220bb898558SAl Viro { 221bb898558SAl Viro write_cr3(__pa(pgdir)); 222bb898558SAl Viro } 223bb898558SAl Viro 224bb898558SAl Viro #ifdef CONFIG_X86_32 225bb898558SAl Viro /* This is the TSS defined by the hardware. */ 226bb898558SAl Viro struct x86_hw_tss { 227bb898558SAl Viro unsigned short back_link, __blh; 228bb898558SAl Viro unsigned long sp0; 229bb898558SAl Viro unsigned short ss0, __ss0h; 230cf9328ccSAndy Lutomirski unsigned long sp1; 23176e4c490SAndy Lutomirski 23276e4c490SAndy Lutomirski /* 233cf9328ccSAndy Lutomirski * We don't use ring 1, so ss1 is a convenient scratch space in 234cf9328ccSAndy Lutomirski * the same cacheline as sp0. We use ss1 to cache the value in 235cf9328ccSAndy Lutomirski * MSR_IA32_SYSENTER_CS. When we context switch 236cf9328ccSAndy Lutomirski * MSR_IA32_SYSENTER_CS, we first check if the new value being 237cf9328ccSAndy Lutomirski * written matches ss1, and, if it's not, then we wrmsr the new 238cf9328ccSAndy Lutomirski * value and update ss1. 23976e4c490SAndy Lutomirski * 240cf9328ccSAndy Lutomirski * The only reason we context switch MSR_IA32_SYSENTER_CS is 241cf9328ccSAndy Lutomirski * that we set it to zero in vm86 tasks to avoid corrupting the 242cf9328ccSAndy Lutomirski * stack if we were to go through the sysenter path from vm86 243cf9328ccSAndy Lutomirski * mode. 24476e4c490SAndy Lutomirski */ 24576e4c490SAndy Lutomirski unsigned short ss1; /* MSR_IA32_SYSENTER_CS */ 24676e4c490SAndy Lutomirski 24776e4c490SAndy Lutomirski unsigned short __ss1h; 248bb898558SAl Viro unsigned long sp2; 249bb898558SAl Viro unsigned short ss2, __ss2h; 250bb898558SAl Viro unsigned long __cr3; 251bb898558SAl Viro unsigned long ip; 252bb898558SAl Viro unsigned long flags; 253bb898558SAl Viro unsigned long ax; 254bb898558SAl Viro unsigned long cx; 255bb898558SAl Viro unsigned long dx; 256bb898558SAl Viro unsigned long bx; 257bb898558SAl Viro unsigned long sp; 258bb898558SAl Viro unsigned long bp; 259bb898558SAl Viro unsigned long si; 260bb898558SAl Viro unsigned long di; 261bb898558SAl Viro unsigned short es, __esh; 262bb898558SAl Viro unsigned short cs, __csh; 263bb898558SAl Viro unsigned short ss, __ssh; 264bb898558SAl Viro unsigned short ds, __dsh; 265bb898558SAl Viro unsigned short fs, __fsh; 266bb898558SAl Viro unsigned short gs, __gsh; 267bb898558SAl Viro unsigned short ldt, __ldth; 268bb898558SAl Viro unsigned short trace; 269bb898558SAl Viro unsigned short io_bitmap_base; 270bb898558SAl Viro 271bb898558SAl Viro } __attribute__((packed)); 272bb898558SAl Viro #else 273bb898558SAl Viro struct x86_hw_tss { 274bb898558SAl Viro u32 reserved1; 275bb898558SAl Viro u64 sp0; 276bb898558SAl Viro u64 sp1; 277bb898558SAl Viro u64 sp2; 278bb898558SAl Viro u64 reserved2; 279bb898558SAl Viro u64 ist[7]; 280bb898558SAl Viro u32 reserved3; 281bb898558SAl Viro u32 reserved4; 282bb898558SAl Viro u16 reserved5; 283bb898558SAl Viro u16 io_bitmap_base; 284bb898558SAl Viro 285bb898558SAl Viro } __attribute__((packed)) ____cacheline_aligned; 286bb898558SAl Viro #endif 287bb898558SAl Viro 288bb898558SAl Viro /* 289bb898558SAl Viro * IO-bitmap sizes: 290bb898558SAl Viro */ 291bb898558SAl Viro #define IO_BITMAP_BITS 65536 292bb898558SAl Viro #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8) 293bb898558SAl Viro #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long)) 294bb898558SAl Viro #define IO_BITMAP_OFFSET offsetof(struct tss_struct, io_bitmap) 295bb898558SAl Viro #define INVALID_IO_BITMAP_OFFSET 0x8000 296bb898558SAl Viro 297bb898558SAl Viro struct tss_struct { 298bb898558SAl Viro /* 299bb898558SAl Viro * The hardware state: 300bb898558SAl Viro */ 301bb898558SAl Viro struct x86_hw_tss x86_tss; 302bb898558SAl Viro 303bb898558SAl Viro /* 304bb898558SAl Viro * The extra 1 is there because the CPU will access an 305bb898558SAl Viro * additional byte beyond the end of the IO permission 306bb898558SAl Viro * bitmap. The extra byte must be all 1 bits, and must 307bb898558SAl Viro * be within the limit. 308bb898558SAl Viro */ 309bb898558SAl Viro unsigned long io_bitmap[IO_BITMAP_LONGS + 1]; 310bb898558SAl Viro 3116dcc9414SAndy Lutomirski #ifdef CONFIG_X86_32 312bb898558SAl Viro /* 3132a41aa4fSAndy Lutomirski * Space for the temporary SYSENTER stack. 314bb898558SAl Viro */ 3152a41aa4fSAndy Lutomirski unsigned long SYSENTER_stack_canary; 316d828c71fSDenys Vlasenko unsigned long SYSENTER_stack[64]; 3176dcc9414SAndy Lutomirski #endif 318bb898558SAl Viro 319bb898558SAl Viro } ____cacheline_aligned; 320bb898558SAl Viro 32124933b82SAndy Lutomirski DECLARE_PER_CPU_SHARED_ALIGNED(struct tss_struct, cpu_tss); 322bb898558SAl Viro 323a7fcf28dSAndy Lutomirski #ifdef CONFIG_X86_32 324a7fcf28dSAndy Lutomirski DECLARE_PER_CPU(unsigned long, cpu_current_top_of_stack); 325a7fcf28dSAndy Lutomirski #endif 326a7fcf28dSAndy Lutomirski 327bb898558SAl Viro /* 328bb898558SAl Viro * Save the original ist values for checking stack pointers during debugging 329bb898558SAl Viro */ 330bb898558SAl Viro struct orig_ist { 331bb898558SAl Viro unsigned long ist[7]; 332bb898558SAl Viro }; 333bb898558SAl Viro 334bb898558SAl Viro #ifdef CONFIG_X86_64 335bb898558SAl Viro DECLARE_PER_CPU(struct orig_ist, orig_ist); 33626f80bd6SBrian Gerst 337947e76cdSBrian Gerst union irq_stack_union { 338947e76cdSBrian Gerst char irq_stack[IRQ_STACK_SIZE]; 339947e76cdSBrian Gerst /* 340947e76cdSBrian Gerst * GCC hardcodes the stack canary as %gs:40. Since the 341947e76cdSBrian Gerst * irq_stack is the object at %gs:0, we reserve the bottom 342947e76cdSBrian Gerst * 48 bytes of the irq stack for the canary. 343947e76cdSBrian Gerst */ 344947e76cdSBrian Gerst struct { 345947e76cdSBrian Gerst char gs_base[40]; 346947e76cdSBrian Gerst unsigned long stack_canary; 347947e76cdSBrian Gerst }; 348947e76cdSBrian Gerst }; 349947e76cdSBrian Gerst 350277d5b40SAndi Kleen DECLARE_PER_CPU_FIRST(union irq_stack_union, irq_stack_union) __visible; 3512add8e23SBrian Gerst DECLARE_INIT_PER_CPU(irq_stack_union); 3522add8e23SBrian Gerst 35326f80bd6SBrian Gerst DECLARE_PER_CPU(char *, irq_stack_ptr); 3549766cdbcSJaswinder Singh Rajput DECLARE_PER_CPU(unsigned int, irq_count); 3559766cdbcSJaswinder Singh Rajput extern asmlinkage void ignore_sysret(void); 35660a5317fSTejun Heo #else /* X86_64 */ 35760a5317fSTejun Heo #ifdef CONFIG_CC_STACKPROTECTOR 3581ea0d14eSJeremy Fitzhardinge /* 3591ea0d14eSJeremy Fitzhardinge * Make sure stack canary segment base is cached-aligned: 3601ea0d14eSJeremy Fitzhardinge * "For Intel Atom processors, avoid non zero segment base address 3611ea0d14eSJeremy Fitzhardinge * that is not aligned to cache line boundary at all cost." 3621ea0d14eSJeremy Fitzhardinge * (Optim Ref Manual Assembly/Compiler Coding Rule 15.) 3631ea0d14eSJeremy Fitzhardinge */ 3641ea0d14eSJeremy Fitzhardinge struct stack_canary { 3651ea0d14eSJeremy Fitzhardinge char __pad[20]; /* canary at %gs:20 */ 3661ea0d14eSJeremy Fitzhardinge unsigned long canary; 3671ea0d14eSJeremy Fitzhardinge }; 36853f82452SJeremy Fitzhardinge DECLARE_PER_CPU_ALIGNED(struct stack_canary, stack_canary); 369bb898558SAl Viro #endif 370198d208dSSteven Rostedt /* 371198d208dSSteven Rostedt * per-CPU IRQ handling stacks 372198d208dSSteven Rostedt */ 373198d208dSSteven Rostedt struct irq_stack { 374198d208dSSteven Rostedt u32 stack[THREAD_SIZE/sizeof(u32)]; 375198d208dSSteven Rostedt } __aligned(THREAD_SIZE); 376198d208dSSteven Rostedt 377198d208dSSteven Rostedt DECLARE_PER_CPU(struct irq_stack *, hardirq_stack); 378198d208dSSteven Rostedt DECLARE_PER_CPU(struct irq_stack *, softirq_stack); 37960a5317fSTejun Heo #endif /* X86_64 */ 380bb898558SAl Viro 381bf15a8cfSFenghua Yu extern unsigned int fpu_kernel_xstate_size; 382a1141e0bSFenghua Yu extern unsigned int fpu_user_xstate_size; 383bb898558SAl Viro 38424f1e32cSFrederic Weisbecker struct perf_event; 38524f1e32cSFrederic Weisbecker 38613d4ea09SAndy Lutomirski typedef struct { 38713d4ea09SAndy Lutomirski unsigned long seg; 38813d4ea09SAndy Lutomirski } mm_segment_t; 38913d4ea09SAndy Lutomirski 390bb898558SAl Viro struct thread_struct { 391bb898558SAl Viro /* Cached TLS descriptors: */ 392bb898558SAl Viro struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES]; 393bb898558SAl Viro unsigned long sp0; 394bb898558SAl Viro unsigned long sp; 395bb898558SAl Viro #ifdef CONFIG_X86_32 396bb898558SAl Viro unsigned long sysenter_cs; 397bb898558SAl Viro #else 398bb898558SAl Viro unsigned short es; 399bb898558SAl Viro unsigned short ds; 400bb898558SAl Viro unsigned short fsindex; 401bb898558SAl Viro unsigned short gsindex; 402bb898558SAl Viro #endif 403b9d989c7SAndy Lutomirski 404b9d989c7SAndy Lutomirski u32 status; /* thread synchronous flags */ 405b9d989c7SAndy Lutomirski 406d756f4adSAlexey Dobriyan #ifdef CONFIG_X86_64 407296f781aSAndy Lutomirski unsigned long fsbase; 408296f781aSAndy Lutomirski unsigned long gsbase; 409296f781aSAndy Lutomirski #else 410296f781aSAndy Lutomirski /* 411296f781aSAndy Lutomirski * XXX: this could presumably be unsigned short. Alternatively, 412296f781aSAndy Lutomirski * 32-bit kernels could be taught to use fsindex instead. 413296f781aSAndy Lutomirski */ 414bb898558SAl Viro unsigned long fs; 415bb898558SAl Viro unsigned long gs; 416296f781aSAndy Lutomirski #endif 417c5bedc68SIngo Molnar 41824f1e32cSFrederic Weisbecker /* Save middle states of ptrace breakpoints */ 41924f1e32cSFrederic Weisbecker struct perf_event *ptrace_bps[HBP_NUM]; 42024f1e32cSFrederic Weisbecker /* Debug status used for traps, single steps, etc... */ 421bb898558SAl Viro unsigned long debugreg6; 422326264a0SFrederic Weisbecker /* Keep track of the exact dr7 value set by the user */ 423326264a0SFrederic Weisbecker unsigned long ptrace_dr7; 424bb898558SAl Viro /* Fault info: */ 425bb898558SAl Viro unsigned long cr2; 42651e7dc70SSrikar Dronamraju unsigned long trap_nr; 427bb898558SAl Viro unsigned long error_code; 4289fda6a06SBrian Gerst #ifdef CONFIG_VM86 429bb898558SAl Viro /* Virtual 86 mode info */ 4309fda6a06SBrian Gerst struct vm86 *vm86; 431bb898558SAl Viro #endif 432bb898558SAl Viro /* IO permissions: */ 433bb898558SAl Viro unsigned long *io_bitmap_ptr; 434bb898558SAl Viro unsigned long iopl; 435bb898558SAl Viro /* Max allowed port in the bitmap, in bytes: */ 436bb898558SAl Viro unsigned io_bitmap_max; 4370c8c0f03SDave Hansen 43813d4ea09SAndy Lutomirski mm_segment_t addr_limit; 43913d4ea09SAndy Lutomirski 4402a53ccbcSIngo Molnar unsigned int sig_on_uaccess_err:1; 441dfa9a942SAndy Lutomirski unsigned int uaccess_err:1; /* uaccess failed */ 442dfa9a942SAndy Lutomirski 4430c8c0f03SDave Hansen /* Floating point and extended processor state */ 4440c8c0f03SDave Hansen struct fpu fpu; 4450c8c0f03SDave Hansen /* 4460c8c0f03SDave Hansen * WARNING: 'fpu' is dynamically-sized. It *MUST* be at 4470c8c0f03SDave Hansen * the end. 4480c8c0f03SDave Hansen */ 449bb898558SAl Viro }; 450bb898558SAl Viro 451bb898558SAl Viro /* 452b9d989c7SAndy Lutomirski * Thread-synchronous status. 453b9d989c7SAndy Lutomirski * 454b9d989c7SAndy Lutomirski * This is different from the flags in that nobody else 455b9d989c7SAndy Lutomirski * ever touches our thread-synchronous status, so we don't 456b9d989c7SAndy Lutomirski * have to worry about atomic accesses. 457b9d989c7SAndy Lutomirski */ 458b9d989c7SAndy Lutomirski #define TS_COMPAT 0x0002 /* 32bit syscall active (64BIT)*/ 459b9d989c7SAndy Lutomirski 460b9d989c7SAndy Lutomirski /* 461bb898558SAl Viro * Set IOPL bits in EFLAGS from given mask 462bb898558SAl Viro */ 463bb898558SAl Viro static inline void native_set_iopl_mask(unsigned mask) 464bb898558SAl Viro { 465bb898558SAl Viro #ifdef CONFIG_X86_32 466bb898558SAl Viro unsigned int reg; 467bb898558SAl Viro 468bb898558SAl Viro asm volatile ("pushfl;" 469bb898558SAl Viro "popl %0;" 470bb898558SAl Viro "andl %1, %0;" 471bb898558SAl Viro "orl %2, %0;" 472bb898558SAl Viro "pushl %0;" 473bb898558SAl Viro "popfl" 474bb898558SAl Viro : "=&r" (reg) 475bb898558SAl Viro : "i" (~X86_EFLAGS_IOPL), "r" (mask)); 476bb898558SAl Viro #endif 477bb898558SAl Viro } 478bb898558SAl Viro 479bb898558SAl Viro static inline void 480bb898558SAl Viro native_load_sp0(struct tss_struct *tss, struct thread_struct *thread) 481bb898558SAl Viro { 482bb898558SAl Viro tss->x86_tss.sp0 = thread->sp0; 483bb898558SAl Viro #ifdef CONFIG_X86_32 484bb898558SAl Viro /* Only happens when SEP is enabled, no need to test "SEP"arately: */ 485bb898558SAl Viro if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) { 486bb898558SAl Viro tss->x86_tss.ss1 = thread->sysenter_cs; 487bb898558SAl Viro wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0); 488bb898558SAl Viro } 489bb898558SAl Viro #endif 490bb898558SAl Viro } 491bb898558SAl Viro 492bb898558SAl Viro static inline void native_swapgs(void) 493bb898558SAl Viro { 494bb898558SAl Viro #ifdef CONFIG_X86_64 495bb898558SAl Viro asm volatile("swapgs" ::: "memory"); 496bb898558SAl Viro #endif 497bb898558SAl Viro } 498bb898558SAl Viro 499a7fcf28dSAndy Lutomirski static inline unsigned long current_top_of_stack(void) 5008ef46a67SAndy Lutomirski { 501a7fcf28dSAndy Lutomirski #ifdef CONFIG_X86_64 50224933b82SAndy Lutomirski return this_cpu_read_stable(cpu_tss.x86_tss.sp0); 503a7fcf28dSAndy Lutomirski #else 504a7fcf28dSAndy Lutomirski /* sp0 on x86_32 is special in and around vm86 mode. */ 505a7fcf28dSAndy Lutomirski return this_cpu_read_stable(cpu_current_top_of_stack); 506a7fcf28dSAndy Lutomirski #endif 5078ef46a67SAndy Lutomirski } 5088ef46a67SAndy Lutomirski 509bb898558SAl Viro #ifdef CONFIG_PARAVIRT 510bb898558SAl Viro #include <asm/paravirt.h> 511bb898558SAl Viro #else 512bb898558SAl Viro #define __cpuid native_cpuid 513bb898558SAl Viro 514bb898558SAl Viro static inline void load_sp0(struct tss_struct *tss, 515bb898558SAl Viro struct thread_struct *thread) 516bb898558SAl Viro { 517bb898558SAl Viro native_load_sp0(tss, thread); 518bb898558SAl Viro } 519bb898558SAl Viro 520bb898558SAl Viro #define set_iopl_mask native_set_iopl_mask 521bb898558SAl Viro #endif /* CONFIG_PARAVIRT */ 522bb898558SAl Viro 523bb898558SAl Viro /* Free all resources held by a thread. */ 524bb898558SAl Viro extern void release_thread(struct task_struct *); 525bb898558SAl Viro 526bb898558SAl Viro unsigned long get_wchan(struct task_struct *p); 527bb898558SAl Viro 528bb898558SAl Viro /* 529bb898558SAl Viro * Generic CPUID function 530bb898558SAl Viro * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx 531bb898558SAl Viro * resulting in stale register contents being returned. 532bb898558SAl Viro */ 533bb898558SAl Viro static inline void cpuid(unsigned int op, 534bb898558SAl Viro unsigned int *eax, unsigned int *ebx, 535bb898558SAl Viro unsigned int *ecx, unsigned int *edx) 536bb898558SAl Viro { 537bb898558SAl Viro *eax = op; 538bb898558SAl Viro *ecx = 0; 539bb898558SAl Viro __cpuid(eax, ebx, ecx, edx); 540bb898558SAl Viro } 541bb898558SAl Viro 542bb898558SAl Viro /* Some CPUID calls want 'count' to be placed in ecx */ 543bb898558SAl Viro static inline void cpuid_count(unsigned int op, int count, 544bb898558SAl Viro unsigned int *eax, unsigned int *ebx, 545bb898558SAl Viro unsigned int *ecx, unsigned int *edx) 546bb898558SAl Viro { 547bb898558SAl Viro *eax = op; 548bb898558SAl Viro *ecx = count; 549bb898558SAl Viro __cpuid(eax, ebx, ecx, edx); 550bb898558SAl Viro } 551bb898558SAl Viro 552bb898558SAl Viro /* 553bb898558SAl Viro * CPUID functions returning a single datum 554bb898558SAl Viro */ 555bb898558SAl Viro static inline unsigned int cpuid_eax(unsigned int op) 556bb898558SAl Viro { 557bb898558SAl Viro unsigned int eax, ebx, ecx, edx; 558bb898558SAl Viro 559bb898558SAl Viro cpuid(op, &eax, &ebx, &ecx, &edx); 560bb898558SAl Viro 561bb898558SAl Viro return eax; 562bb898558SAl Viro } 563bb898558SAl Viro 564bb898558SAl Viro static inline unsigned int cpuid_ebx(unsigned int op) 565bb898558SAl Viro { 566bb898558SAl Viro unsigned int eax, ebx, ecx, edx; 567bb898558SAl Viro 568bb898558SAl Viro cpuid(op, &eax, &ebx, &ecx, &edx); 569bb898558SAl Viro 570bb898558SAl Viro return ebx; 571bb898558SAl Viro } 572bb898558SAl Viro 573bb898558SAl Viro static inline unsigned int cpuid_ecx(unsigned int op) 574bb898558SAl Viro { 575bb898558SAl Viro unsigned int eax, ebx, ecx, edx; 576bb898558SAl Viro 577bb898558SAl Viro cpuid(op, &eax, &ebx, &ecx, &edx); 578bb898558SAl Viro 579bb898558SAl Viro return ecx; 580bb898558SAl Viro } 581bb898558SAl Viro 582bb898558SAl Viro static inline unsigned int cpuid_edx(unsigned int op) 583bb898558SAl Viro { 584bb898558SAl Viro unsigned int eax, ebx, ecx, edx; 585bb898558SAl Viro 586bb898558SAl Viro cpuid(op, &eax, &ebx, &ecx, &edx); 587bb898558SAl Viro 588bb898558SAl Viro return edx; 589bb898558SAl Viro } 590bb898558SAl Viro 591bb898558SAl Viro /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */ 5920b101e62SDenys Vlasenko static __always_inline void rep_nop(void) 593bb898558SAl Viro { 594bb898558SAl Viro asm volatile("rep; nop" ::: "memory"); 595bb898558SAl Viro } 596bb898558SAl Viro 5970b101e62SDenys Vlasenko static __always_inline void cpu_relax(void) 598bb898558SAl Viro { 599bb898558SAl Viro rep_nop(); 600bb898558SAl Viro } 601bb898558SAl Viro 6023a6bfbc9SDavidlohr Bueso #define cpu_relax_lowlatency() cpu_relax() 6033a6bfbc9SDavidlohr Bueso 6045367b688SBen Hutchings /* Stop speculative execution and prefetching of modified code. */ 605bb898558SAl Viro static inline void sync_core(void) 606bb898558SAl Viro { 607bb898558SAl Viro int tmp; 608bb898558SAl Viro 609eb068e78SH. Peter Anvin #ifdef CONFIG_M486 61045c39fb0SH. Peter Anvin /* 61145c39fb0SH. Peter Anvin * Do a CPUID if available, otherwise do a jump. The jump 61245c39fb0SH. Peter Anvin * can conveniently enough be the jump around CPUID. 61345c39fb0SH. Peter Anvin */ 61445c39fb0SH. Peter Anvin asm volatile("cmpl %2,%1\n\t" 61545c39fb0SH. Peter Anvin "jl 1f\n\t" 61645c39fb0SH. Peter Anvin "cpuid\n" 61745c39fb0SH. Peter Anvin "1:" 61845c39fb0SH. Peter Anvin : "=a" (tmp) 61945c39fb0SH. Peter Anvin : "rm" (boot_cpu_data.cpuid_level), "ri" (0), "0" (1) 620bb898558SAl Viro : "ebx", "ecx", "edx", "memory"); 62145c39fb0SH. Peter Anvin #else 62245c39fb0SH. Peter Anvin /* 62345c39fb0SH. Peter Anvin * CPUID is a barrier to speculative execution. 62445c39fb0SH. Peter Anvin * Prefetched instructions are automatically 62545c39fb0SH. Peter Anvin * invalidated when modified. 62645c39fb0SH. Peter Anvin */ 62745c39fb0SH. Peter Anvin asm volatile("cpuid" 62845c39fb0SH. Peter Anvin : "=a" (tmp) 62945c39fb0SH. Peter Anvin : "0" (1) 63045c39fb0SH. Peter Anvin : "ebx", "ecx", "edx", "memory"); 63145c39fb0SH. Peter Anvin #endif 632bb898558SAl Viro } 633bb898558SAl Viro 634bb898558SAl Viro extern void select_idle_routine(const struct cpuinfo_x86 *c); 63502c68a02SLen Brown extern void init_amd_e400_c1e_mask(void); 636bb898558SAl Viro 637bb898558SAl Viro extern unsigned long boot_option_idle_override; 63802c68a02SLen Brown extern bool amd_e400_c1e_detected; 639bb898558SAl Viro 640d1896049SThomas Renninger enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_NOMWAIT, 64169fb3676SLen Brown IDLE_POLL}; 642d1896049SThomas Renninger 643bb898558SAl Viro extern void enable_sep_cpu(void); 644bb898558SAl Viro extern int sysenter_setup(void); 645bb898558SAl Viro 64629c84391SJan Kiszka extern void early_trap_init(void); 6478170e6beSH. Peter Anvin void early_trap_pf_init(void); 64829c84391SJan Kiszka 649bb898558SAl Viro /* Defined in head.S */ 650bb898558SAl Viro extern struct desc_ptr early_gdt_descr; 651bb898558SAl Viro 652bb898558SAl Viro extern void cpu_set_gdt(int); 653552be871SBrian Gerst extern void switch_to_new_gdt(int); 65411e3a840SJeremy Fitzhardinge extern void load_percpu_segment(int); 655bb898558SAl Viro extern void cpu_init(void); 656bb898558SAl Viro 657c2724775SMarkus Metzger static inline unsigned long get_debugctlmsr(void) 658c2724775SMarkus Metzger { 659c2724775SMarkus Metzger unsigned long debugctlmsr = 0; 660c2724775SMarkus Metzger 661c2724775SMarkus Metzger #ifndef CONFIG_X86_DEBUGCTLMSR 662c2724775SMarkus Metzger if (boot_cpu_data.x86 < 6) 663c2724775SMarkus Metzger return 0; 664c2724775SMarkus Metzger #endif 665c2724775SMarkus Metzger rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr); 666c2724775SMarkus Metzger 667c2724775SMarkus Metzger return debugctlmsr; 668c2724775SMarkus Metzger } 669c2724775SMarkus Metzger 670bb898558SAl Viro static inline void update_debugctlmsr(unsigned long debugctlmsr) 671bb898558SAl Viro { 672bb898558SAl Viro #ifndef CONFIG_X86_DEBUGCTLMSR 673bb898558SAl Viro if (boot_cpu_data.x86 < 6) 674bb898558SAl Viro return; 675bb898558SAl Viro #endif 676bb898558SAl Viro wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr); 677bb898558SAl Viro } 678bb898558SAl Viro 6799bd1190aSOleg Nesterov extern void set_task_blockstep(struct task_struct *task, bool on); 6809bd1190aSOleg Nesterov 681bb898558SAl Viro /* Boot loader type from the setup header: */ 682bb898558SAl Viro extern int bootloader_type; 6835031296cSH. Peter Anvin extern int bootloader_version; 684bb898558SAl Viro 685bb898558SAl Viro extern char ignore_fpu_irq; 686bb898558SAl Viro 687bb898558SAl Viro #define HAVE_ARCH_PICK_MMAP_LAYOUT 1 688bb898558SAl Viro #define ARCH_HAS_PREFETCHW 689bb898558SAl Viro #define ARCH_HAS_SPINLOCK_PREFETCH 690bb898558SAl Viro 691bb898558SAl Viro #ifdef CONFIG_X86_32 692a930dc45SBorislav Petkov # define BASE_PREFETCH "" 693bb898558SAl Viro # define ARCH_HAS_PREFETCH 694bb898558SAl Viro #else 695a930dc45SBorislav Petkov # define BASE_PREFETCH "prefetcht0 %P1" 696bb898558SAl Viro #endif 697bb898558SAl Viro 698bb898558SAl Viro /* 699bb898558SAl Viro * Prefetch instructions for Pentium III (+) and AMD Athlon (+) 700bb898558SAl Viro * 701bb898558SAl Viro * It's not worth to care about 3dnow prefetches for the K6 702bb898558SAl Viro * because they are microcoded there and very slow. 703bb898558SAl Viro */ 704bb898558SAl Viro static inline void prefetch(const void *x) 705bb898558SAl Viro { 706a930dc45SBorislav Petkov alternative_input(BASE_PREFETCH, "prefetchnta %P1", 707bb898558SAl Viro X86_FEATURE_XMM, 708a930dc45SBorislav Petkov "m" (*(const char *)x)); 709bb898558SAl Viro } 710bb898558SAl Viro 711bb898558SAl Viro /* 712bb898558SAl Viro * 3dnow prefetch to get an exclusive cache line. 713bb898558SAl Viro * Useful for spinlocks to avoid one state transition in the 714bb898558SAl Viro * cache coherency protocol: 715bb898558SAl Viro */ 716bb898558SAl Viro static inline void prefetchw(const void *x) 717bb898558SAl Viro { 718a930dc45SBorislav Petkov alternative_input(BASE_PREFETCH, "prefetchw %P1", 719a930dc45SBorislav Petkov X86_FEATURE_3DNOWPREFETCH, 720a930dc45SBorislav Petkov "m" (*(const char *)x)); 721bb898558SAl Viro } 722bb898558SAl Viro 723bb898558SAl Viro static inline void spin_lock_prefetch(const void *x) 724bb898558SAl Viro { 725bb898558SAl Viro prefetchw(x); 726bb898558SAl Viro } 727bb898558SAl Viro 728d9e05cc5SAndy Lutomirski #define TOP_OF_INIT_STACK ((unsigned long)&init_stack + sizeof(init_stack) - \ 729d9e05cc5SAndy Lutomirski TOP_OF_KERNEL_STACK_PADDING) 730d9e05cc5SAndy Lutomirski 731bb898558SAl Viro #ifdef CONFIG_X86_32 732bb898558SAl Viro /* 733bb898558SAl Viro * User space process size: 3GB (default). 734bb898558SAl Viro */ 735bb898558SAl Viro #define TASK_SIZE PAGE_OFFSET 736d9517346SIngo Molnar #define TASK_SIZE_MAX TASK_SIZE 737bb898558SAl Viro #define STACK_TOP TASK_SIZE 738bb898558SAl Viro #define STACK_TOP_MAX STACK_TOP 739bb898558SAl Viro 740bb898558SAl Viro #define INIT_THREAD { \ 741d9e05cc5SAndy Lutomirski .sp0 = TOP_OF_INIT_STACK, \ 742bb898558SAl Viro .sysenter_cs = __KERNEL_CS, \ 743bb898558SAl Viro .io_bitmap_ptr = NULL, \ 74413d4ea09SAndy Lutomirski .addr_limit = KERNEL_DS, \ 745bb898558SAl Viro } 746bb898558SAl Viro 747bb898558SAl Viro /* 7485c39403eSDenys Vlasenko * TOP_OF_KERNEL_STACK_PADDING reserves 8 bytes on top of the ring0 stack. 749bb898558SAl Viro * This is necessary to guarantee that the entire "struct pt_regs" 750b595076aSUwe Kleine-König * is accessible even if the CPU haven't stored the SS/ESP registers 751bb898558SAl Viro * on the stack (interrupt gate does not save these registers 752bb898558SAl Viro * when switching to the same priv ring). 753bb898558SAl Viro * Therefore beware: accessing the ss/esp fields of the 754bb898558SAl Viro * "struct pt_regs" is possible, but they may contain the 755bb898558SAl Viro * completely wrong values. 756bb898558SAl Viro */ 757bb898558SAl Viro #define task_pt_regs(task) \ 758bb898558SAl Viro ({ \ 7595c39403eSDenys Vlasenko unsigned long __ptr = (unsigned long)task_stack_page(task); \ 7605c39403eSDenys Vlasenko __ptr += THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING; \ 7615c39403eSDenys Vlasenko ((struct pt_regs *)__ptr) - 1; \ 762bb898558SAl Viro }) 763bb898558SAl Viro 764bb898558SAl Viro #define KSTK_ESP(task) (task_pt_regs(task)->sp) 765bb898558SAl Viro 766bb898558SAl Viro #else 767bb898558SAl Viro /* 76807114f0fSAndy Lutomirski * User space process size. 47bits minus one guard page. The guard 76907114f0fSAndy Lutomirski * page is necessary on Intel CPUs: if a SYSCALL instruction is at 77007114f0fSAndy Lutomirski * the highest possible canonical userspace address, then that 77107114f0fSAndy Lutomirski * syscall will enter the kernel with a non-canonical return 77207114f0fSAndy Lutomirski * address, and SYSRET will explode dangerously. We avoid this 77307114f0fSAndy Lutomirski * particular problem by preventing anything from being mapped 77407114f0fSAndy Lutomirski * at the maximum canonical address. 775bb898558SAl Viro */ 776d9517346SIngo Molnar #define TASK_SIZE_MAX ((1UL << 47) - PAGE_SIZE) 777bb898558SAl Viro 778bb898558SAl Viro /* This decides where the kernel will search for a free chunk of vm 779bb898558SAl Viro * space during mmap's. 780bb898558SAl Viro */ 781bb898558SAl Viro #define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? \ 782bb898558SAl Viro 0xc0000000 : 0xFFFFe000) 783bb898558SAl Viro 7846bd33008SH. Peter Anvin #define TASK_SIZE (test_thread_flag(TIF_ADDR32) ? \ 785d9517346SIngo Molnar IA32_PAGE_OFFSET : TASK_SIZE_MAX) 7866bd33008SH. Peter Anvin #define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_ADDR32)) ? \ 787d9517346SIngo Molnar IA32_PAGE_OFFSET : TASK_SIZE_MAX) 788bb898558SAl Viro 789bb898558SAl Viro #define STACK_TOP TASK_SIZE 790d9517346SIngo Molnar #define STACK_TOP_MAX TASK_SIZE_MAX 791bb898558SAl Viro 792bb898558SAl Viro #define INIT_THREAD { \ 79313d4ea09SAndy Lutomirski .sp0 = TOP_OF_INIT_STACK, \ 79413d4ea09SAndy Lutomirski .addr_limit = KERNEL_DS, \ 795bb898558SAl Viro } 796bb898558SAl Viro 797bb898558SAl Viro #define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.sp0 - 1) 79889240ba0SStefani Seibold extern unsigned long KSTK_ESP(struct task_struct *task); 799d046ff8bSH. J. Lu 800bb898558SAl Viro #endif /* CONFIG_X86_64 */ 801bb898558SAl Viro 802ffcb043bSBrian Gerst extern unsigned long thread_saved_pc(struct task_struct *tsk); 803ffcb043bSBrian Gerst 804bb898558SAl Viro extern void start_thread(struct pt_regs *regs, unsigned long new_ip, 805bb898558SAl Viro unsigned long new_sp); 806bb898558SAl Viro 807bb898558SAl Viro /* 808bb898558SAl Viro * This decides where the kernel will search for a free chunk of vm 809bb898558SAl Viro * space during mmap's. 810bb898558SAl Viro */ 811bb898558SAl Viro #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3)) 812bb898558SAl Viro 813bb898558SAl Viro #define KSTK_EIP(task) (task_pt_regs(task)->ip) 814bb898558SAl Viro 815bb898558SAl Viro /* Get/set a process' ability to use the timestamp counter instruction */ 816bb898558SAl Viro #define GET_TSC_CTL(adr) get_tsc_mode((adr)) 817bb898558SAl Viro #define SET_TSC_CTL(val) set_tsc_mode((val)) 818bb898558SAl Viro 819bb898558SAl Viro extern int get_tsc_mode(unsigned long adr); 820bb898558SAl Viro extern int set_tsc_mode(unsigned int val); 821bb898558SAl Viro 822fe3d197fSDave Hansen /* Register/unregister a process' MPX related resource */ 82346a6e0cfSDave Hansen #define MPX_ENABLE_MANAGEMENT() mpx_enable_management() 82446a6e0cfSDave Hansen #define MPX_DISABLE_MANAGEMENT() mpx_disable_management() 825fe3d197fSDave Hansen 826fe3d197fSDave Hansen #ifdef CONFIG_X86_INTEL_MPX 82746a6e0cfSDave Hansen extern int mpx_enable_management(void); 82846a6e0cfSDave Hansen extern int mpx_disable_management(void); 829fe3d197fSDave Hansen #else 83046a6e0cfSDave Hansen static inline int mpx_enable_management(void) 831fe3d197fSDave Hansen { 832fe3d197fSDave Hansen return -EINVAL; 833fe3d197fSDave Hansen } 83446a6e0cfSDave Hansen static inline int mpx_disable_management(void) 835fe3d197fSDave Hansen { 836fe3d197fSDave Hansen return -EINVAL; 837fe3d197fSDave Hansen } 838fe3d197fSDave Hansen #endif /* CONFIG_X86_INTEL_MPX */ 839fe3d197fSDave Hansen 8408b84c8dfSDaniel J Blueman extern u16 amd_get_nb_id(int cpu); 841cc2749e4SAravind Gopalakrishnan extern u32 amd_get_nodes_per_socket(void); 8426a812691SAndreas Herrmann 84396e39ac0SJason Wang static inline uint32_t hypervisor_cpuid_base(const char *sig, uint32_t leaves) 84496e39ac0SJason Wang { 84596e39ac0SJason Wang uint32_t base, eax, signature[3]; 84696e39ac0SJason Wang 84796e39ac0SJason Wang for (base = 0x40000000; base < 0x40010000; base += 0x100) { 84896e39ac0SJason Wang cpuid(base, &eax, &signature[0], &signature[1], &signature[2]); 84996e39ac0SJason Wang 85096e39ac0SJason Wang if (!memcmp(sig, signature, 12) && 85196e39ac0SJason Wang (leaves == 0 || ((eax - base) >= leaves))) 85296e39ac0SJason Wang return base; 85396e39ac0SJason Wang } 85496e39ac0SJason Wang 85596e39ac0SJason Wang return 0; 85696e39ac0SJason Wang } 85796e39ac0SJason Wang 858f05e798aSDavid Howells extern unsigned long arch_align_stack(unsigned long sp); 859f05e798aSDavid Howells extern void free_init_pages(char *what, unsigned long begin, unsigned long end); 860f05e798aSDavid Howells 861f05e798aSDavid Howells void default_idle(void); 8626a377ddcSLen Brown #ifdef CONFIG_XEN 8636a377ddcSLen Brown bool xen_set_default_idle(void); 8646a377ddcSLen Brown #else 8656a377ddcSLen Brown #define xen_set_default_idle 0 8666a377ddcSLen Brown #endif 867f05e798aSDavid Howells 868f05e798aSDavid Howells void stop_this_cpu(void *dummy); 8694d067d8eSBorislav Petkov void df_debug(struct pt_regs *regs, long error_code); 8701965aae3SH. Peter Anvin #endif /* _ASM_X86_PROCESSOR_H */ 871