1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 21965aae3SH. Peter Anvin #ifndef _ASM_X86_PROCESSOR_H 31965aae3SH. Peter Anvin #define _ASM_X86_PROCESSOR_H 4bb898558SAl Viro 5bb898558SAl Viro #include <asm/processor-flags.h> 6bb898558SAl Viro 7bb898558SAl Viro /* Forward declaration, a strange C thing */ 8bb898558SAl Viro struct task_struct; 9bb898558SAl Viro struct mm_struct; 109fda6a06SBrian Gerst struct vm86; 11bb898558SAl Viro 12bb898558SAl Viro #include <asm/math_emu.h> 13bb898558SAl Viro #include <asm/segment.h> 14bb898558SAl Viro #include <asm/types.h> 15decb4c41SIngo Molnar #include <uapi/asm/sigcontext.h> 16bb898558SAl Viro #include <asm/current.h> 17cd4d09ecSBorislav Petkov #include <asm/cpufeatures.h> 18bb898558SAl Viro #include <asm/page.h> 1954321d94SJeremy Fitzhardinge #include <asm/pgtable_types.h> 20bb898558SAl Viro #include <asm/percpu.h> 21bb898558SAl Viro #include <asm/msr.h> 22bb898558SAl Viro #include <asm/desc_defs.h> 23bb898558SAl Viro #include <asm/nops.h> 24f05e798aSDavid Howells #include <asm/special_insns.h> 2514b9675aSIngo Molnar #include <asm/fpu/types.h> 2676846bf3SJosh Poimboeuf #include <asm/unwind_hints.h> 27bb898558SAl Viro 28bb898558SAl Viro #include <linux/personality.h> 29bb898558SAl Viro #include <linux/cache.h> 30bb898558SAl Viro #include <linux/threads.h> 315cbc19a9SPeter Zijlstra #include <linux/math64.h> 32faa4602eSPeter Zijlstra #include <linux/err.h> 33f05e798aSDavid Howells #include <linux/irqflags.h> 3421729f81STom Lendacky #include <linux/mem_encrypt.h> 35f05e798aSDavid Howells 36f05e798aSDavid Howells /* 37f05e798aSDavid Howells * We handle most unaligned accesses in hardware. On the other hand 38f05e798aSDavid Howells * unaligned DMA can be quite expensive on some Nehalem processors. 39f05e798aSDavid Howells * 40f05e798aSDavid Howells * Based on this we disable the IP header alignment in network drivers. 41f05e798aSDavid Howells */ 42f05e798aSDavid Howells #define NET_IP_ALIGN 0 43bb898558SAl Viro 44b332828cSK.Prasad #define HBP_NUM 4 45bb898558SAl Viro 46b8c1b8eaSIngo Molnar /* 47b8c1b8eaSIngo Molnar * These alignment constraints are for performance in the vSMP case, 48b8c1b8eaSIngo Molnar * but in the task_struct case we must also meet hardware imposed 49b8c1b8eaSIngo Molnar * alignment requirements of the FPU state: 50b8c1b8eaSIngo Molnar */ 51bb898558SAl Viro #ifdef CONFIG_X86_VSMP 52bb898558SAl Viro # define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT) 53bb898558SAl Viro # define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT) 54bb898558SAl Viro #else 55b8c1b8eaSIngo Molnar # define ARCH_MIN_TASKALIGN __alignof__(union fpregs_state) 56bb898558SAl Viro # define ARCH_MIN_MMSTRUCT_ALIGN 0 57bb898558SAl Viro #endif 58bb898558SAl Viro 59e0ba94f1SAlex Shi enum tlb_infos { 60e0ba94f1SAlex Shi ENTRIES, 61e0ba94f1SAlex Shi NR_INFO 62e0ba94f1SAlex Shi }; 63e0ba94f1SAlex Shi 64e0ba94f1SAlex Shi extern u16 __read_mostly tlb_lli_4k[NR_INFO]; 65e0ba94f1SAlex Shi extern u16 __read_mostly tlb_lli_2m[NR_INFO]; 66e0ba94f1SAlex Shi extern u16 __read_mostly tlb_lli_4m[NR_INFO]; 67e0ba94f1SAlex Shi extern u16 __read_mostly tlb_lld_4k[NR_INFO]; 68e0ba94f1SAlex Shi extern u16 __read_mostly tlb_lld_2m[NR_INFO]; 69e0ba94f1SAlex Shi extern u16 __read_mostly tlb_lld_4m[NR_INFO]; 70dd360393SKirill A. Shutemov extern u16 __read_mostly tlb_lld_1g[NR_INFO]; 71c4211f42SAlex Shi 72bb898558SAl Viro /* 73bb898558SAl Viro * CPU type and hardware bug flags. Kept separately for each CPU. 7404402116SMathias Krause * Members of this structure are referenced in head_32.S, so think twice 75bb898558SAl Viro * before touching them. [mj] 76bb898558SAl Viro */ 77bb898558SAl Viro 78bb898558SAl Viro struct cpuinfo_x86 { 79bb898558SAl Viro __u8 x86; /* CPU family */ 80bb898558SAl Viro __u8 x86_vendor; /* CPU vendor */ 81bb898558SAl Viro __u8 x86_model; 82b399151cSJia Zhang __u8 x86_stepping; 836415813bSMathias Krause #ifdef CONFIG_X86_64 84bb898558SAl Viro /* Number of 4K pages in DTLB/ITLB combined(in pages): */ 85bb898558SAl Viro int x86_tlbsize; 8613c6c532SJan Beulich #endif 87bb898558SAl Viro __u8 x86_virt_bits; 88bb898558SAl Viro __u8 x86_phys_bits; 89bb898558SAl Viro /* CPUID returned core id bits: */ 90bb898558SAl Viro __u8 x86_coreid_bits; 9179a8b9aaSBorislav Petkov __u8 cu_id; 92bb898558SAl Viro /* Max extended CPUID function supported: */ 93bb898558SAl Viro __u32 extended_cpuid_level; 94bb898558SAl Viro /* Maximum supported CPUID level, -1=no CPUID: */ 95bb898558SAl Viro int cpuid_level; 9665fc985bSBorislav Petkov __u32 x86_capability[NCAPINTS + NBUGINTS]; 97bb898558SAl Viro char x86_vendor_id[16]; 98bb898558SAl Viro char x86_model_id[64]; 99bb898558SAl Viro /* in KB - valid for CPUS which support this call: */ 10024dbc600SGustavo A. R. Silva unsigned int x86_cache_size; 101bb898558SAl Viro int x86_cache_alignment; /* In bytes */ 102cbc82b17SPeter P Waskiewicz Jr /* Cache QoS architectural values: */ 103cbc82b17SPeter P Waskiewicz Jr int x86_cache_max_rmid; /* max index */ 104cbc82b17SPeter P Waskiewicz Jr int x86_cache_occ_scale; /* scale to bytes */ 105bb898558SAl Viro int x86_power; 106bb898558SAl Viro unsigned long loops_per_jiffy; 107bb898558SAl Viro /* cpuid returned max cores value: */ 108bb898558SAl Viro u16 x86_max_cores; 109bb898558SAl Viro u16 apicid; 110bb898558SAl Viro u16 initial_apicid; 111bb898558SAl Viro u16 x86_clflush_size; 112bb898558SAl Viro /* number of cores as seen by the OS: */ 113bb898558SAl Viro u16 booted_cores; 114bb898558SAl Viro /* Physical processor id: */ 115bb898558SAl Viro u16 phys_proc_id; 1161f12e32fSThomas Gleixner /* Logical processor id: */ 1171f12e32fSThomas Gleixner u16 logical_proc_id; 118bb898558SAl Viro /* Core id: */ 119bb898558SAl Viro u16 cpu_core_id; 120bb898558SAl Viro /* Index into per_cpu list: */ 121bb898558SAl Viro u16 cpu_index; 122506ed6b5SAndi Kleen u32 microcode; 123cc51e542SAndi Kleen /* Address space bits used by the cache internally */ 124cc51e542SAndi Kleen u8 x86_cache_bits; 12530bb9811SAndi Kleen unsigned initialized : 1; 1263859a271SKees Cook } __randomize_layout; 127bb898558SAl Viro 12847f10a36SHe Chen struct cpuid_regs { 12947f10a36SHe Chen u32 eax, ebx, ecx, edx; 13047f10a36SHe Chen }; 13147f10a36SHe Chen 13247f10a36SHe Chen enum cpuid_regs_idx { 13347f10a36SHe Chen CPUID_EAX = 0, 13447f10a36SHe Chen CPUID_EBX, 13547f10a36SHe Chen CPUID_ECX, 13647f10a36SHe Chen CPUID_EDX, 13747f10a36SHe Chen }; 13847f10a36SHe Chen 139bb898558SAl Viro #define X86_VENDOR_INTEL 0 140bb898558SAl Viro #define X86_VENDOR_CYRIX 1 141bb898558SAl Viro #define X86_VENDOR_AMD 2 142bb898558SAl Viro #define X86_VENDOR_UMC 3 143bb898558SAl Viro #define X86_VENDOR_CENTAUR 5 144bb898558SAl Viro #define X86_VENDOR_TRANSMETA 7 145bb898558SAl Viro #define X86_VENDOR_NSC 8 146c9661c1eSPu Wen #define X86_VENDOR_HYGON 9 147c9661c1eSPu Wen #define X86_VENDOR_NUM 10 148bb898558SAl Viro 149bb898558SAl Viro #define X86_VENDOR_UNKNOWN 0xff 150bb898558SAl Viro 151bb898558SAl Viro /* 152bb898558SAl Viro * capabilities of CPUs 153bb898558SAl Viro */ 154bb898558SAl Viro extern struct cpuinfo_x86 boot_cpu_data; 155bb898558SAl Viro extern struct cpuinfo_x86 new_cpu_data; 156bb898558SAl Viro 1577fb983b4SAndy Lutomirski extern struct x86_hw_tss doublefault_tss; 1586cbd2171SThomas Gleixner extern __u32 cpu_caps_cleared[NCAPINTS + NBUGINTS]; 1596cbd2171SThomas Gleixner extern __u32 cpu_caps_set[NCAPINTS + NBUGINTS]; 160bb898558SAl Viro 161bb898558SAl Viro #ifdef CONFIG_SMP 1622c773dd3SJan Beulich DECLARE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info); 163bb898558SAl Viro #define cpu_data(cpu) per_cpu(cpu_info, cpu) 164bb898558SAl Viro #else 1657b543a53STejun Heo #define cpu_info boot_cpu_data 166bb898558SAl Viro #define cpu_data(cpu) boot_cpu_data 167bb898558SAl Viro #endif 168bb898558SAl Viro 169bb898558SAl Viro extern const struct seq_operations cpuinfo_op; 170bb898558SAl Viro 171bb898558SAl Viro #define cache_line_size() (boot_cpu_data.x86_cache_alignment) 172bb898558SAl Viro 173bb898558SAl Viro extern void cpu_detect(struct cpuinfo_x86 *c); 174bb898558SAl Viro 1759df95169SVlastimil Babka static inline unsigned long long l1tf_pfn_limit(void) 17617dbca11SAndi Kleen { 177cc51e542SAndi Kleen return BIT_ULL(boot_cpu_data.x86_cache_bits - 1 - PAGE_SHIFT); 17817dbca11SAndi Kleen } 17917dbca11SAndi Kleen 180bb898558SAl Viro extern void early_cpu_init(void); 181bb898558SAl Viro extern void identify_boot_cpu(void); 182bb898558SAl Viro extern void identify_secondary_cpu(struct cpuinfo_x86 *); 183bb898558SAl Viro extern void print_cpu_info(struct cpuinfo_x86 *); 18421c3fcf3SYinghai Lu void print_cpu_msr(struct cpuinfo_x86 *); 185bb898558SAl Viro 186d288e1cfSFenghua Yu #ifdef CONFIG_X86_32 187d288e1cfSFenghua Yu extern int have_cpuid_p(void); 188d288e1cfSFenghua Yu #else 189d288e1cfSFenghua Yu static inline int have_cpuid_p(void) 190d288e1cfSFenghua Yu { 191d288e1cfSFenghua Yu return 1; 192d288e1cfSFenghua Yu } 193d288e1cfSFenghua Yu #endif 194bb898558SAl Viro static inline void native_cpuid(unsigned int *eax, unsigned int *ebx, 195bb898558SAl Viro unsigned int *ecx, unsigned int *edx) 196bb898558SAl Viro { 197bb898558SAl Viro /* ecx is often an input as well as an output. */ 19845a94d7cSSuresh Siddha asm volatile("cpuid" 199bb898558SAl Viro : "=a" (*eax), 200bb898558SAl Viro "=b" (*ebx), 201bb898558SAl Viro "=c" (*ecx), 202bb898558SAl Viro "=d" (*edx) 203506ed6b5SAndi Kleen : "0" (*eax), "2" (*ecx) 204506ed6b5SAndi Kleen : "memory"); 205bb898558SAl Viro } 206bb898558SAl Viro 2075dedade6SBorislav Petkov #define native_cpuid_reg(reg) \ 2085dedade6SBorislav Petkov static inline unsigned int native_cpuid_##reg(unsigned int op) \ 2095dedade6SBorislav Petkov { \ 2105dedade6SBorislav Petkov unsigned int eax = op, ebx, ecx = 0, edx; \ 2115dedade6SBorislav Petkov \ 2125dedade6SBorislav Petkov native_cpuid(&eax, &ebx, &ecx, &edx); \ 2135dedade6SBorislav Petkov \ 2145dedade6SBorislav Petkov return reg; \ 2155dedade6SBorislav Petkov } 2165dedade6SBorislav Petkov 2175dedade6SBorislav Petkov /* 2185dedade6SBorislav Petkov * Native CPUID functions returning a single datum. 2195dedade6SBorislav Petkov */ 2205dedade6SBorislav Petkov native_cpuid_reg(eax) 2215dedade6SBorislav Petkov native_cpuid_reg(ebx) 2225dedade6SBorislav Petkov native_cpuid_reg(ecx) 2235dedade6SBorislav Petkov native_cpuid_reg(edx) 2245dedade6SBorislav Petkov 2256c690ee1SAndy Lutomirski /* 2266c690ee1SAndy Lutomirski * Friendlier CR3 helpers. 2276c690ee1SAndy Lutomirski */ 2286c690ee1SAndy Lutomirski static inline unsigned long read_cr3_pa(void) 2296c690ee1SAndy Lutomirski { 2306c690ee1SAndy Lutomirski return __read_cr3() & CR3_ADDR_MASK; 2316c690ee1SAndy Lutomirski } 2326c690ee1SAndy Lutomirski 233eef9c4abSTom Lendacky static inline unsigned long native_read_cr3_pa(void) 234eef9c4abSTom Lendacky { 235eef9c4abSTom Lendacky return __native_read_cr3() & CR3_ADDR_MASK; 236eef9c4abSTom Lendacky } 237eef9c4abSTom Lendacky 238bb898558SAl Viro static inline void load_cr3(pgd_t *pgdir) 239bb898558SAl Viro { 24021729f81STom Lendacky write_cr3(__sme_pa(pgdir)); 241bb898558SAl Viro } 242bb898558SAl Viro 2437fb983b4SAndy Lutomirski /* 2447fb983b4SAndy Lutomirski * Note that while the legacy 'TSS' name comes from 'Task State Segment', 2457fb983b4SAndy Lutomirski * on modern x86 CPUs the TSS also holds information important to 64-bit mode, 2467fb983b4SAndy Lutomirski * unrelated to the task-switch mechanism: 2477fb983b4SAndy Lutomirski */ 248bb898558SAl Viro #ifdef CONFIG_X86_32 249bb898558SAl Viro /* This is the TSS defined by the hardware. */ 250bb898558SAl Viro struct x86_hw_tss { 251bb898558SAl Viro unsigned short back_link, __blh; 252bb898558SAl Viro unsigned long sp0; 253bb898558SAl Viro unsigned short ss0, __ss0h; 254cf9328ccSAndy Lutomirski unsigned long sp1; 25576e4c490SAndy Lutomirski 25676e4c490SAndy Lutomirski /* 257cf9328ccSAndy Lutomirski * We don't use ring 1, so ss1 is a convenient scratch space in 258cf9328ccSAndy Lutomirski * the same cacheline as sp0. We use ss1 to cache the value in 259cf9328ccSAndy Lutomirski * MSR_IA32_SYSENTER_CS. When we context switch 260cf9328ccSAndy Lutomirski * MSR_IA32_SYSENTER_CS, we first check if the new value being 261cf9328ccSAndy Lutomirski * written matches ss1, and, if it's not, then we wrmsr the new 262cf9328ccSAndy Lutomirski * value and update ss1. 26376e4c490SAndy Lutomirski * 264cf9328ccSAndy Lutomirski * The only reason we context switch MSR_IA32_SYSENTER_CS is 265cf9328ccSAndy Lutomirski * that we set it to zero in vm86 tasks to avoid corrupting the 266cf9328ccSAndy Lutomirski * stack if we were to go through the sysenter path from vm86 267cf9328ccSAndy Lutomirski * mode. 26876e4c490SAndy Lutomirski */ 26976e4c490SAndy Lutomirski unsigned short ss1; /* MSR_IA32_SYSENTER_CS */ 27076e4c490SAndy Lutomirski 27176e4c490SAndy Lutomirski unsigned short __ss1h; 272bb898558SAl Viro unsigned long sp2; 273bb898558SAl Viro unsigned short ss2, __ss2h; 274bb898558SAl Viro unsigned long __cr3; 275bb898558SAl Viro unsigned long ip; 276bb898558SAl Viro unsigned long flags; 277bb898558SAl Viro unsigned long ax; 278bb898558SAl Viro unsigned long cx; 279bb898558SAl Viro unsigned long dx; 280bb898558SAl Viro unsigned long bx; 281bb898558SAl Viro unsigned long sp; 282bb898558SAl Viro unsigned long bp; 283bb898558SAl Viro unsigned long si; 284bb898558SAl Viro unsigned long di; 285bb898558SAl Viro unsigned short es, __esh; 286bb898558SAl Viro unsigned short cs, __csh; 287bb898558SAl Viro unsigned short ss, __ssh; 288bb898558SAl Viro unsigned short ds, __dsh; 289bb898558SAl Viro unsigned short fs, __fsh; 290bb898558SAl Viro unsigned short gs, __gsh; 291bb898558SAl Viro unsigned short ldt, __ldth; 292bb898558SAl Viro unsigned short trace; 293bb898558SAl Viro unsigned short io_bitmap_base; 294bb898558SAl Viro 295bb898558SAl Viro } __attribute__((packed)); 296bb898558SAl Viro #else 297bb898558SAl Viro struct x86_hw_tss { 298bb898558SAl Viro u32 reserved1; 299bb898558SAl Viro u64 sp0; 3009aaefe7bSAndy Lutomirski 3019aaefe7bSAndy Lutomirski /* 3029aaefe7bSAndy Lutomirski * We store cpu_current_top_of_stack in sp1 so it's always accessible. 3039aaefe7bSAndy Lutomirski * Linux does not use ring 1, so sp1 is not otherwise needed. 3049aaefe7bSAndy Lutomirski */ 305bb898558SAl Viro u64 sp1; 3069aaefe7bSAndy Lutomirski 30798f05b51SAndy Lutomirski /* 30898f05b51SAndy Lutomirski * Since Linux does not use ring 2, the 'sp2' slot is unused by 30998f05b51SAndy Lutomirski * hardware. entry_SYSCALL_64 uses it as scratch space to stash 31098f05b51SAndy Lutomirski * the user RSP value. 31198f05b51SAndy Lutomirski */ 312bb898558SAl Viro u64 sp2; 31398f05b51SAndy Lutomirski 314bb898558SAl Viro u64 reserved2; 315bb898558SAl Viro u64 ist[7]; 316bb898558SAl Viro u32 reserved3; 317bb898558SAl Viro u32 reserved4; 318bb898558SAl Viro u16 reserved5; 319bb898558SAl Viro u16 io_bitmap_base; 320bb898558SAl Viro 321d3273deaSAndy Lutomirski } __attribute__((packed)); 322bb898558SAl Viro #endif 323bb898558SAl Viro 324bb898558SAl Viro /* 325bb898558SAl Viro * IO-bitmap sizes: 326bb898558SAl Viro */ 327bb898558SAl Viro #define IO_BITMAP_BITS 65536 328bb898558SAl Viro #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8) 329bb898558SAl Viro #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long)) 3307fb983b4SAndy Lutomirski #define IO_BITMAP_OFFSET (offsetof(struct tss_struct, io_bitmap) - offsetof(struct tss_struct, x86_tss)) 331bb898558SAl Viro #define INVALID_IO_BITMAP_OFFSET 0x8000 332bb898558SAl Viro 3334fe2d8b1SDave Hansen struct entry_stack { 3340f9a4810SAndy Lutomirski unsigned long words[64]; 3350f9a4810SAndy Lutomirski }; 3360f9a4810SAndy Lutomirski 3374fe2d8b1SDave Hansen struct entry_stack_page { 3384fe2d8b1SDave Hansen struct entry_stack stack; 339c482feefSAndy Lutomirski } __aligned(PAGE_SIZE); 3401a935bc3SAndy Lutomirski 341bb898558SAl Viro struct tss_struct { 342bb898558SAl Viro /* 3431a935bc3SAndy Lutomirski * The fixed hardware portion. This must not cross a page boundary 3441a935bc3SAndy Lutomirski * at risk of violating the SDM's advice and potentially triggering 3451a935bc3SAndy Lutomirski * errata. 346bb898558SAl Viro */ 347bb898558SAl Viro struct x86_hw_tss x86_tss; 348bb898558SAl Viro 349bb898558SAl Viro /* 350bb898558SAl Viro * The extra 1 is there because the CPU will access an 351bb898558SAl Viro * additional byte beyond the end of the IO permission 352bb898558SAl Viro * bitmap. The extra byte must be all 1 bits, and must 353bb898558SAl Viro * be within the limit. 354bb898558SAl Viro */ 355bb898558SAl Viro unsigned long io_bitmap[IO_BITMAP_LONGS + 1]; 3561a935bc3SAndy Lutomirski } __aligned(PAGE_SIZE); 357bb898558SAl Viro 358c482feefSAndy Lutomirski DECLARE_PER_CPU_PAGE_ALIGNED(struct tss_struct, cpu_tss_rw); 359bb898558SAl Viro 3604f53ab14SAndy Lutomirski /* 3614f53ab14SAndy Lutomirski * sizeof(unsigned long) coming from an extra "long" at the end 3624f53ab14SAndy Lutomirski * of the iobitmap. 3634f53ab14SAndy Lutomirski * 3644f53ab14SAndy Lutomirski * -1? seg base+limit should be pointing to the address of the 3654f53ab14SAndy Lutomirski * last valid byte 3664f53ab14SAndy Lutomirski */ 3674f53ab14SAndy Lutomirski #define __KERNEL_TSS_LIMIT \ 3684f53ab14SAndy Lutomirski (IO_BITMAP_OFFSET + IO_BITMAP_BYTES + sizeof(unsigned long) - 1) 3694f53ab14SAndy Lutomirski 370a7fcf28dSAndy Lutomirski #ifdef CONFIG_X86_32 371a7fcf28dSAndy Lutomirski DECLARE_PER_CPU(unsigned long, cpu_current_top_of_stack); 3729aaefe7bSAndy Lutomirski #else 373c482feefSAndy Lutomirski /* The RO copy can't be accessed with this_cpu_xyz(), so use the RW copy. */ 374c482feefSAndy Lutomirski #define cpu_current_top_of_stack cpu_tss_rw.x86_tss.sp1 375a7fcf28dSAndy Lutomirski #endif 376a7fcf28dSAndy Lutomirski 377bb898558SAl Viro /* 378bb898558SAl Viro * Save the original ist values for checking stack pointers during debugging 379bb898558SAl Viro */ 380bb898558SAl Viro struct orig_ist { 381bb898558SAl Viro unsigned long ist[7]; 382bb898558SAl Viro }; 383bb898558SAl Viro 384bb898558SAl Viro #ifdef CONFIG_X86_64 385bb898558SAl Viro DECLARE_PER_CPU(struct orig_ist, orig_ist); 38626f80bd6SBrian Gerst 387947e76cdSBrian Gerst union irq_stack_union { 388947e76cdSBrian Gerst char irq_stack[IRQ_STACK_SIZE]; 389947e76cdSBrian Gerst /* 390947e76cdSBrian Gerst * GCC hardcodes the stack canary as %gs:40. Since the 391947e76cdSBrian Gerst * irq_stack is the object at %gs:0, we reserve the bottom 392947e76cdSBrian Gerst * 48 bytes of the irq stack for the canary. 393947e76cdSBrian Gerst */ 394947e76cdSBrian Gerst struct { 395947e76cdSBrian Gerst char gs_base[40]; 396947e76cdSBrian Gerst unsigned long stack_canary; 397947e76cdSBrian Gerst }; 398947e76cdSBrian Gerst }; 399947e76cdSBrian Gerst 400277d5b40SAndi Kleen DECLARE_PER_CPU_FIRST(union irq_stack_union, irq_stack_union) __visible; 4012add8e23SBrian Gerst DECLARE_INIT_PER_CPU(irq_stack_union); 4022add8e23SBrian Gerst 40335060ed6SVitaly Kuznetsov static inline unsigned long cpu_kernelmode_gs_base(int cpu) 40435060ed6SVitaly Kuznetsov { 40535060ed6SVitaly Kuznetsov return (unsigned long)per_cpu(irq_stack_union.gs_base, cpu); 40635060ed6SVitaly Kuznetsov } 40735060ed6SVitaly Kuznetsov 40826f80bd6SBrian Gerst DECLARE_PER_CPU(char *, irq_stack_ptr); 4099766cdbcSJaswinder Singh Rajput DECLARE_PER_CPU(unsigned int, irq_count); 4109766cdbcSJaswinder Singh Rajput extern asmlinkage void ignore_sysret(void); 41142b933b5SVitaly Kuznetsov 41242b933b5SVitaly Kuznetsov #if IS_ENABLED(CONFIG_KVM) 41342b933b5SVitaly Kuznetsov /* Save actual FS/GS selectors and bases to current->thread */ 41442b933b5SVitaly Kuznetsov void save_fsgs_for_kvm(void); 41542b933b5SVitaly Kuznetsov #endif 41660a5317fSTejun Heo #else /* X86_64 */ 417050e9baaSLinus Torvalds #ifdef CONFIG_STACKPROTECTOR 4181ea0d14eSJeremy Fitzhardinge /* 4191ea0d14eSJeremy Fitzhardinge * Make sure stack canary segment base is cached-aligned: 4201ea0d14eSJeremy Fitzhardinge * "For Intel Atom processors, avoid non zero segment base address 4211ea0d14eSJeremy Fitzhardinge * that is not aligned to cache line boundary at all cost." 4221ea0d14eSJeremy Fitzhardinge * (Optim Ref Manual Assembly/Compiler Coding Rule 15.) 4231ea0d14eSJeremy Fitzhardinge */ 4241ea0d14eSJeremy Fitzhardinge struct stack_canary { 4251ea0d14eSJeremy Fitzhardinge char __pad[20]; /* canary at %gs:20 */ 4261ea0d14eSJeremy Fitzhardinge unsigned long canary; 4271ea0d14eSJeremy Fitzhardinge }; 42853f82452SJeremy Fitzhardinge DECLARE_PER_CPU_ALIGNED(struct stack_canary, stack_canary); 429bb898558SAl Viro #endif 430198d208dSSteven Rostedt /* 431198d208dSSteven Rostedt * per-CPU IRQ handling stacks 432198d208dSSteven Rostedt */ 433198d208dSSteven Rostedt struct irq_stack { 434198d208dSSteven Rostedt u32 stack[THREAD_SIZE/sizeof(u32)]; 435198d208dSSteven Rostedt } __aligned(THREAD_SIZE); 436198d208dSSteven Rostedt 437198d208dSSteven Rostedt DECLARE_PER_CPU(struct irq_stack *, hardirq_stack); 438198d208dSSteven Rostedt DECLARE_PER_CPU(struct irq_stack *, softirq_stack); 43960a5317fSTejun Heo #endif /* X86_64 */ 440bb898558SAl Viro 441bf15a8cfSFenghua Yu extern unsigned int fpu_kernel_xstate_size; 442a1141e0bSFenghua Yu extern unsigned int fpu_user_xstate_size; 443bb898558SAl Viro 44424f1e32cSFrederic Weisbecker struct perf_event; 44524f1e32cSFrederic Weisbecker 44613d4ea09SAndy Lutomirski typedef struct { 44713d4ea09SAndy Lutomirski unsigned long seg; 44813d4ea09SAndy Lutomirski } mm_segment_t; 44913d4ea09SAndy Lutomirski 450bb898558SAl Viro struct thread_struct { 451bb898558SAl Viro /* Cached TLS descriptors: */ 452bb898558SAl Viro struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES]; 453d375cf15SAndy Lutomirski #ifdef CONFIG_X86_32 454bb898558SAl Viro unsigned long sp0; 455d375cf15SAndy Lutomirski #endif 456bb898558SAl Viro unsigned long sp; 457bb898558SAl Viro #ifdef CONFIG_X86_32 458bb898558SAl Viro unsigned long sysenter_cs; 459bb898558SAl Viro #else 460bb898558SAl Viro unsigned short es; 461bb898558SAl Viro unsigned short ds; 462bb898558SAl Viro unsigned short fsindex; 463bb898558SAl Viro unsigned short gsindex; 464bb898558SAl Viro #endif 465b9d989c7SAndy Lutomirski 466d756f4adSAlexey Dobriyan #ifdef CONFIG_X86_64 467296f781aSAndy Lutomirski unsigned long fsbase; 468296f781aSAndy Lutomirski unsigned long gsbase; 469296f781aSAndy Lutomirski #else 470296f781aSAndy Lutomirski /* 471296f781aSAndy Lutomirski * XXX: this could presumably be unsigned short. Alternatively, 472296f781aSAndy Lutomirski * 32-bit kernels could be taught to use fsindex instead. 473296f781aSAndy Lutomirski */ 474bb898558SAl Viro unsigned long fs; 475bb898558SAl Viro unsigned long gs; 476296f781aSAndy Lutomirski #endif 477c5bedc68SIngo Molnar 47824f1e32cSFrederic Weisbecker /* Save middle states of ptrace breakpoints */ 47924f1e32cSFrederic Weisbecker struct perf_event *ptrace_bps[HBP_NUM]; 48024f1e32cSFrederic Weisbecker /* Debug status used for traps, single steps, etc... */ 481bb898558SAl Viro unsigned long debugreg6; 482326264a0SFrederic Weisbecker /* Keep track of the exact dr7 value set by the user */ 483326264a0SFrederic Weisbecker unsigned long ptrace_dr7; 484bb898558SAl Viro /* Fault info: */ 485bb898558SAl Viro unsigned long cr2; 48651e7dc70SSrikar Dronamraju unsigned long trap_nr; 487bb898558SAl Viro unsigned long error_code; 4889fda6a06SBrian Gerst #ifdef CONFIG_VM86 489bb898558SAl Viro /* Virtual 86 mode info */ 4909fda6a06SBrian Gerst struct vm86 *vm86; 491bb898558SAl Viro #endif 492bb898558SAl Viro /* IO permissions: */ 493bb898558SAl Viro unsigned long *io_bitmap_ptr; 494bb898558SAl Viro unsigned long iopl; 495bb898558SAl Viro /* Max allowed port in the bitmap, in bytes: */ 496bb898558SAl Viro unsigned io_bitmap_max; 4970c8c0f03SDave Hansen 49813d4ea09SAndy Lutomirski mm_segment_t addr_limit; 49913d4ea09SAndy Lutomirski 5002a53ccbcSIngo Molnar unsigned int sig_on_uaccess_err:1; 501dfa9a942SAndy Lutomirski unsigned int uaccess_err:1; /* uaccess failed */ 502dfa9a942SAndy Lutomirski 5030c8c0f03SDave Hansen /* Floating point and extended processor state */ 5040c8c0f03SDave Hansen struct fpu fpu; 5050c8c0f03SDave Hansen /* 5060c8c0f03SDave Hansen * WARNING: 'fpu' is dynamically-sized. It *MUST* be at 5070c8c0f03SDave Hansen * the end. 5080c8c0f03SDave Hansen */ 509bb898558SAl Viro }; 510bb898558SAl Viro 511f7d83c1cSKees Cook /* Whitelist the FPU state from the task_struct for hardened usercopy. */ 512f7d83c1cSKees Cook static inline void arch_thread_struct_whitelist(unsigned long *offset, 513f7d83c1cSKees Cook unsigned long *size) 514f7d83c1cSKees Cook { 515f7d83c1cSKees Cook *offset = offsetof(struct thread_struct, fpu.state); 516f7d83c1cSKees Cook *size = fpu_kernel_xstate_size; 517f7d83c1cSKees Cook } 518f7d83c1cSKees Cook 519bb898558SAl Viro /* 520b9d989c7SAndy Lutomirski * Thread-synchronous status. 521b9d989c7SAndy Lutomirski * 522b9d989c7SAndy Lutomirski * This is different from the flags in that nobody else 523b9d989c7SAndy Lutomirski * ever touches our thread-synchronous status, so we don't 524b9d989c7SAndy Lutomirski * have to worry about atomic accesses. 525b9d989c7SAndy Lutomirski */ 526b9d989c7SAndy Lutomirski #define TS_COMPAT 0x0002 /* 32bit syscall active (64BIT)*/ 527b9d989c7SAndy Lutomirski 528b9d989c7SAndy Lutomirski /* 529bb898558SAl Viro * Set IOPL bits in EFLAGS from given mask 530bb898558SAl Viro */ 531bb898558SAl Viro static inline void native_set_iopl_mask(unsigned mask) 532bb898558SAl Viro { 533bb898558SAl Viro #ifdef CONFIG_X86_32 534bb898558SAl Viro unsigned int reg; 535bb898558SAl Viro 536bb898558SAl Viro asm volatile ("pushfl;" 537bb898558SAl Viro "popl %0;" 538bb898558SAl Viro "andl %1, %0;" 539bb898558SAl Viro "orl %2, %0;" 540bb898558SAl Viro "pushl %0;" 541bb898558SAl Viro "popfl" 542bb898558SAl Viro : "=&r" (reg) 543bb898558SAl Viro : "i" (~X86_EFLAGS_IOPL), "r" (mask)); 544bb898558SAl Viro #endif 545bb898558SAl Viro } 546bb898558SAl Viro 547bb898558SAl Viro static inline void 548da51da18SAndy Lutomirski native_load_sp0(unsigned long sp0) 549bb898558SAl Viro { 550c482feefSAndy Lutomirski this_cpu_write(cpu_tss_rw.x86_tss.sp0, sp0); 551bb898558SAl Viro } 552bb898558SAl Viro 553bb898558SAl Viro static inline void native_swapgs(void) 554bb898558SAl Viro { 555bb898558SAl Viro #ifdef CONFIG_X86_64 556bb898558SAl Viro asm volatile("swapgs" ::: "memory"); 557bb898558SAl Viro #endif 558bb898558SAl Viro } 559bb898558SAl Viro 560a7fcf28dSAndy Lutomirski static inline unsigned long current_top_of_stack(void) 5618ef46a67SAndy Lutomirski { 5629aaefe7bSAndy Lutomirski /* 5639aaefe7bSAndy Lutomirski * We can't read directly from tss.sp0: sp0 on x86_32 is special in 5649aaefe7bSAndy Lutomirski * and around vm86 mode and sp0 on x86_64 is special because of the 5659aaefe7bSAndy Lutomirski * entry trampoline. 5669aaefe7bSAndy Lutomirski */ 567a7fcf28dSAndy Lutomirski return this_cpu_read_stable(cpu_current_top_of_stack); 5688ef46a67SAndy Lutomirski } 5698ef46a67SAndy Lutomirski 5703383642cSAndy Lutomirski static inline bool on_thread_stack(void) 5713383642cSAndy Lutomirski { 5723383642cSAndy Lutomirski return (unsigned long)(current_top_of_stack() - 5733383642cSAndy Lutomirski current_stack_pointer) < THREAD_SIZE; 5743383642cSAndy Lutomirski } 5753383642cSAndy Lutomirski 5769bad5658SJuergen Gross #ifdef CONFIG_PARAVIRT_XXL 577bb898558SAl Viro #include <asm/paravirt.h> 578bb898558SAl Viro #else 579bb898558SAl Viro #define __cpuid native_cpuid 580bb898558SAl Viro 581da51da18SAndy Lutomirski static inline void load_sp0(unsigned long sp0) 582bb898558SAl Viro { 583da51da18SAndy Lutomirski native_load_sp0(sp0); 584bb898558SAl Viro } 585bb898558SAl Viro 586bb898558SAl Viro #define set_iopl_mask native_set_iopl_mask 5879bad5658SJuergen Gross #endif /* CONFIG_PARAVIRT_XXL */ 588bb898558SAl Viro 589bb898558SAl Viro /* Free all resources held by a thread. */ 590bb898558SAl Viro extern void release_thread(struct task_struct *); 591bb898558SAl Viro 592bb898558SAl Viro unsigned long get_wchan(struct task_struct *p); 593bb898558SAl Viro 594bb898558SAl Viro /* 595bb898558SAl Viro * Generic CPUID function 596bb898558SAl Viro * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx 597bb898558SAl Viro * resulting in stale register contents being returned. 598bb898558SAl Viro */ 599bb898558SAl Viro static inline void cpuid(unsigned int op, 600bb898558SAl Viro unsigned int *eax, unsigned int *ebx, 601bb898558SAl Viro unsigned int *ecx, unsigned int *edx) 602bb898558SAl Viro { 603bb898558SAl Viro *eax = op; 604bb898558SAl Viro *ecx = 0; 605bb898558SAl Viro __cpuid(eax, ebx, ecx, edx); 606bb898558SAl Viro } 607bb898558SAl Viro 608bb898558SAl Viro /* Some CPUID calls want 'count' to be placed in ecx */ 609bb898558SAl Viro static inline void cpuid_count(unsigned int op, int count, 610bb898558SAl Viro unsigned int *eax, unsigned int *ebx, 611bb898558SAl Viro unsigned int *ecx, unsigned int *edx) 612bb898558SAl Viro { 613bb898558SAl Viro *eax = op; 614bb898558SAl Viro *ecx = count; 615bb898558SAl Viro __cpuid(eax, ebx, ecx, edx); 616bb898558SAl Viro } 617bb898558SAl Viro 618bb898558SAl Viro /* 619bb898558SAl Viro * CPUID functions returning a single datum 620bb898558SAl Viro */ 621bb898558SAl Viro static inline unsigned int cpuid_eax(unsigned int op) 622bb898558SAl Viro { 623bb898558SAl Viro unsigned int eax, ebx, ecx, edx; 624bb898558SAl Viro 625bb898558SAl Viro cpuid(op, &eax, &ebx, &ecx, &edx); 626bb898558SAl Viro 627bb898558SAl Viro return eax; 628bb898558SAl Viro } 629bb898558SAl Viro 630bb898558SAl Viro static inline unsigned int cpuid_ebx(unsigned int op) 631bb898558SAl Viro { 632bb898558SAl Viro unsigned int eax, ebx, ecx, edx; 633bb898558SAl Viro 634bb898558SAl Viro cpuid(op, &eax, &ebx, &ecx, &edx); 635bb898558SAl Viro 636bb898558SAl Viro return ebx; 637bb898558SAl Viro } 638bb898558SAl Viro 639bb898558SAl Viro static inline unsigned int cpuid_ecx(unsigned int op) 640bb898558SAl Viro { 641bb898558SAl Viro unsigned int eax, ebx, ecx, edx; 642bb898558SAl Viro 643bb898558SAl Viro cpuid(op, &eax, &ebx, &ecx, &edx); 644bb898558SAl Viro 645bb898558SAl Viro return ecx; 646bb898558SAl Viro } 647bb898558SAl Viro 648bb898558SAl Viro static inline unsigned int cpuid_edx(unsigned int op) 649bb898558SAl Viro { 650bb898558SAl Viro unsigned int eax, ebx, ecx, edx; 651bb898558SAl Viro 652bb898558SAl Viro cpuid(op, &eax, &ebx, &ecx, &edx); 653bb898558SAl Viro 654bb898558SAl Viro return edx; 655bb898558SAl Viro } 656bb898558SAl Viro 657bb898558SAl Viro /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */ 6580b101e62SDenys Vlasenko static __always_inline void rep_nop(void) 659bb898558SAl Viro { 660bb898558SAl Viro asm volatile("rep; nop" ::: "memory"); 661bb898558SAl Viro } 662bb898558SAl Viro 6630b101e62SDenys Vlasenko static __always_inline void cpu_relax(void) 664bb898558SAl Viro { 665bb898558SAl Viro rep_nop(); 666bb898558SAl Viro } 667bb898558SAl Viro 668c198b121SAndy Lutomirski /* 669c198b121SAndy Lutomirski * This function forces the icache and prefetched instruction stream to 670c198b121SAndy Lutomirski * catch up with reality in two very specific cases: 671c198b121SAndy Lutomirski * 672c198b121SAndy Lutomirski * a) Text was modified using one virtual address and is about to be executed 673c198b121SAndy Lutomirski * from the same physical page at a different virtual address. 674c198b121SAndy Lutomirski * 675c198b121SAndy Lutomirski * b) Text was modified on a different CPU, may subsequently be 676c198b121SAndy Lutomirski * executed on this CPU, and you want to make sure the new version 677c198b121SAndy Lutomirski * gets executed. This generally means you're calling this in a IPI. 678c198b121SAndy Lutomirski * 679c198b121SAndy Lutomirski * If you're calling this for a different reason, you're probably doing 680c198b121SAndy Lutomirski * it wrong. 681c198b121SAndy Lutomirski */ 682bb898558SAl Viro static inline void sync_core(void) 683bb898558SAl Viro { 684c198b121SAndy Lutomirski /* 685c198b121SAndy Lutomirski * There are quite a few ways to do this. IRET-to-self is nice 686c198b121SAndy Lutomirski * because it works on every CPU, at any CPL (so it's compatible 687c198b121SAndy Lutomirski * with paravirtualization), and it never exits to a hypervisor. 688c198b121SAndy Lutomirski * The only down sides are that it's a bit slow (it seems to be 689c198b121SAndy Lutomirski * a bit more than 2x slower than the fastest options) and that 690c198b121SAndy Lutomirski * it unmasks NMIs. The "push %cs" is needed because, in 691c198b121SAndy Lutomirski * paravirtual environments, __KERNEL_CS may not be a valid CS 692c198b121SAndy Lutomirski * value when we do IRET directly. 693c198b121SAndy Lutomirski * 694c198b121SAndy Lutomirski * In case NMI unmasking or performance ever becomes a problem, 695c198b121SAndy Lutomirski * the next best option appears to be MOV-to-CR2 and an 696c198b121SAndy Lutomirski * unconditional jump. That sequence also works on all CPUs, 697ecda85e7SJuergen Gross * but it will fault at CPL3 (i.e. Xen PV). 698c198b121SAndy Lutomirski * 699c198b121SAndy Lutomirski * CPUID is the conventional way, but it's nasty: it doesn't 700c198b121SAndy Lutomirski * exist on some 486-like CPUs, and it usually exits to a 701c198b121SAndy Lutomirski * hypervisor. 702c198b121SAndy Lutomirski * 703c198b121SAndy Lutomirski * Like all of Linux's memory ordering operations, this is a 704c198b121SAndy Lutomirski * compiler barrier as well. 705c198b121SAndy Lutomirski */ 7061c52d859SAndy Lutomirski #ifdef CONFIG_X86_32 707c198b121SAndy Lutomirski asm volatile ( 708c198b121SAndy Lutomirski "pushfl\n\t" 709c198b121SAndy Lutomirski "pushl %%cs\n\t" 710c198b121SAndy Lutomirski "pushl $1f\n\t" 711c198b121SAndy Lutomirski "iret\n\t" 71245c39fb0SH. Peter Anvin "1:" 713f5caf621SJosh Poimboeuf : ASM_CALL_CONSTRAINT : : "memory"); 71445c39fb0SH. Peter Anvin #else 715c198b121SAndy Lutomirski unsigned int tmp; 716c198b121SAndy Lutomirski 717c198b121SAndy Lutomirski asm volatile ( 71876846bf3SJosh Poimboeuf UNWIND_HINT_SAVE 719c198b121SAndy Lutomirski "mov %%ss, %0\n\t" 720c198b121SAndy Lutomirski "pushq %q0\n\t" 721c198b121SAndy Lutomirski "pushq %%rsp\n\t" 722c198b121SAndy Lutomirski "addq $8, (%%rsp)\n\t" 723c198b121SAndy Lutomirski "pushfq\n\t" 724c198b121SAndy Lutomirski "mov %%cs, %0\n\t" 725c198b121SAndy Lutomirski "pushq %q0\n\t" 726c198b121SAndy Lutomirski "pushq $1f\n\t" 727c198b121SAndy Lutomirski "iretq\n\t" 72876846bf3SJosh Poimboeuf UNWIND_HINT_RESTORE 729c198b121SAndy Lutomirski "1:" 730f5caf621SJosh Poimboeuf : "=&r" (tmp), ASM_CALL_CONSTRAINT : : "cc", "memory"); 73145c39fb0SH. Peter Anvin #endif 732bb898558SAl Viro } 733bb898558SAl Viro 734bb898558SAl Viro extern void select_idle_routine(const struct cpuinfo_x86 *c); 73507c94a38SBorislav Petkov extern void amd_e400_c1e_apic_setup(void); 736bb898558SAl Viro 737bb898558SAl Viro extern unsigned long boot_option_idle_override; 738bb898558SAl Viro 739d1896049SThomas Renninger enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_NOMWAIT, 74069fb3676SLen Brown IDLE_POLL}; 741d1896049SThomas Renninger 742bb898558SAl Viro extern void enable_sep_cpu(void); 743bb898558SAl Viro extern int sysenter_setup(void); 744bb898558SAl Viro 7458170e6beSH. Peter Anvin void early_trap_pf_init(void); 74629c84391SJan Kiszka 747bb898558SAl Viro /* Defined in head.S */ 748bb898558SAl Viro extern struct desc_ptr early_gdt_descr; 749bb898558SAl Viro 750552be871SBrian Gerst extern void switch_to_new_gdt(int); 75145fc8757SThomas Garnier extern void load_direct_gdt(int); 75269218e47SThomas Garnier extern void load_fixmap_gdt(int); 75311e3a840SJeremy Fitzhardinge extern void load_percpu_segment(int); 754bb898558SAl Viro extern void cpu_init(void); 755bb898558SAl Viro 756c2724775SMarkus Metzger static inline unsigned long get_debugctlmsr(void) 757c2724775SMarkus Metzger { 758c2724775SMarkus Metzger unsigned long debugctlmsr = 0; 759c2724775SMarkus Metzger 760c2724775SMarkus Metzger #ifndef CONFIG_X86_DEBUGCTLMSR 761c2724775SMarkus Metzger if (boot_cpu_data.x86 < 6) 762c2724775SMarkus Metzger return 0; 763c2724775SMarkus Metzger #endif 764c2724775SMarkus Metzger rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr); 765c2724775SMarkus Metzger 766c2724775SMarkus Metzger return debugctlmsr; 767c2724775SMarkus Metzger } 768c2724775SMarkus Metzger 769bb898558SAl Viro static inline void update_debugctlmsr(unsigned long debugctlmsr) 770bb898558SAl Viro { 771bb898558SAl Viro #ifndef CONFIG_X86_DEBUGCTLMSR 772bb898558SAl Viro if (boot_cpu_data.x86 < 6) 773bb898558SAl Viro return; 774bb898558SAl Viro #endif 775bb898558SAl Viro wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr); 776bb898558SAl Viro } 777bb898558SAl Viro 7789bd1190aSOleg Nesterov extern void set_task_blockstep(struct task_struct *task, bool on); 7799bd1190aSOleg Nesterov 780bb898558SAl Viro /* Boot loader type from the setup header: */ 781bb898558SAl Viro extern int bootloader_type; 7825031296cSH. Peter Anvin extern int bootloader_version; 783bb898558SAl Viro 784bb898558SAl Viro extern char ignore_fpu_irq; 785bb898558SAl Viro 786bb898558SAl Viro #define HAVE_ARCH_PICK_MMAP_LAYOUT 1 787bb898558SAl Viro #define ARCH_HAS_PREFETCHW 788bb898558SAl Viro #define ARCH_HAS_SPINLOCK_PREFETCH 789bb898558SAl Viro 790bb898558SAl Viro #ifdef CONFIG_X86_32 791a930dc45SBorislav Petkov # define BASE_PREFETCH "" 792bb898558SAl Viro # define ARCH_HAS_PREFETCH 793bb898558SAl Viro #else 794a930dc45SBorislav Petkov # define BASE_PREFETCH "prefetcht0 %P1" 795bb898558SAl Viro #endif 796bb898558SAl Viro 797bb898558SAl Viro /* 798bb898558SAl Viro * Prefetch instructions for Pentium III (+) and AMD Athlon (+) 799bb898558SAl Viro * 800bb898558SAl Viro * It's not worth to care about 3dnow prefetches for the K6 801bb898558SAl Viro * because they are microcoded there and very slow. 802bb898558SAl Viro */ 803bb898558SAl Viro static inline void prefetch(const void *x) 804bb898558SAl Viro { 805a930dc45SBorislav Petkov alternative_input(BASE_PREFETCH, "prefetchnta %P1", 806bb898558SAl Viro X86_FEATURE_XMM, 807a930dc45SBorislav Petkov "m" (*(const char *)x)); 808bb898558SAl Viro } 809bb898558SAl Viro 810bb898558SAl Viro /* 811bb898558SAl Viro * 3dnow prefetch to get an exclusive cache line. 812bb898558SAl Viro * Useful for spinlocks to avoid one state transition in the 813bb898558SAl Viro * cache coherency protocol: 814bb898558SAl Viro */ 815bb898558SAl Viro static inline void prefetchw(const void *x) 816bb898558SAl Viro { 817a930dc45SBorislav Petkov alternative_input(BASE_PREFETCH, "prefetchw %P1", 818a930dc45SBorislav Petkov X86_FEATURE_3DNOWPREFETCH, 819a930dc45SBorislav Petkov "m" (*(const char *)x)); 820bb898558SAl Viro } 821bb898558SAl Viro 822bb898558SAl Viro static inline void spin_lock_prefetch(const void *x) 823bb898558SAl Viro { 824bb898558SAl Viro prefetchw(x); 825bb898558SAl Viro } 826bb898558SAl Viro 827d9e05cc5SAndy Lutomirski #define TOP_OF_INIT_STACK ((unsigned long)&init_stack + sizeof(init_stack) - \ 828d9e05cc5SAndy Lutomirski TOP_OF_KERNEL_STACK_PADDING) 829d9e05cc5SAndy Lutomirski 8303500130bSAndy Lutomirski #define task_top_of_stack(task) ((unsigned long)(task_pt_regs(task) + 1)) 8313500130bSAndy Lutomirski 832d375cf15SAndy Lutomirski #define task_pt_regs(task) \ 833d375cf15SAndy Lutomirski ({ \ 834d375cf15SAndy Lutomirski unsigned long __ptr = (unsigned long)task_stack_page(task); \ 835d375cf15SAndy Lutomirski __ptr += THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING; \ 836d375cf15SAndy Lutomirski ((struct pt_regs *)__ptr) - 1; \ 837d375cf15SAndy Lutomirski }) 838d375cf15SAndy Lutomirski 839bb898558SAl Viro #ifdef CONFIG_X86_32 840bb898558SAl Viro /* 841bb898558SAl Viro * User space process size: 3GB (default). 842bb898558SAl Viro */ 8438f3e474fSDmitry Safonov #define IA32_PAGE_OFFSET PAGE_OFFSET 844bb898558SAl Viro #define TASK_SIZE PAGE_OFFSET 845b569bab7SKirill A. Shutemov #define TASK_SIZE_LOW TASK_SIZE 846d9517346SIngo Molnar #define TASK_SIZE_MAX TASK_SIZE 84744b04912SKirill A. Shutemov #define DEFAULT_MAP_WINDOW TASK_SIZE 848bb898558SAl Viro #define STACK_TOP TASK_SIZE 849bb898558SAl Viro #define STACK_TOP_MAX STACK_TOP 850bb898558SAl Viro 851bb898558SAl Viro #define INIT_THREAD { \ 852d9e05cc5SAndy Lutomirski .sp0 = TOP_OF_INIT_STACK, \ 853bb898558SAl Viro .sysenter_cs = __KERNEL_CS, \ 854bb898558SAl Viro .io_bitmap_ptr = NULL, \ 85513d4ea09SAndy Lutomirski .addr_limit = KERNEL_DS, \ 856bb898558SAl Viro } 857bb898558SAl Viro 858bb898558SAl Viro #define KSTK_ESP(task) (task_pt_regs(task)->sp) 859bb898558SAl Viro 860bb898558SAl Viro #else 861bb898558SAl Viro /* 862f55f0501SAndy Lutomirski * User space process size. This is the first address outside the user range. 863f55f0501SAndy Lutomirski * There are a few constraints that determine this: 864f55f0501SAndy Lutomirski * 865f55f0501SAndy Lutomirski * On Intel CPUs, if a SYSCALL instruction is at the highest canonical 866f55f0501SAndy Lutomirski * address, then that syscall will enter the kernel with a 867f55f0501SAndy Lutomirski * non-canonical return address, and SYSRET will explode dangerously. 868f55f0501SAndy Lutomirski * We avoid this particular problem by preventing anything executable 869f55f0501SAndy Lutomirski * from being mapped at the maximum canonical address. 870f55f0501SAndy Lutomirski * 871f55f0501SAndy Lutomirski * On AMD CPUs in the Ryzen family, there's a nasty bug in which the 872f55f0501SAndy Lutomirski * CPUs malfunction if they execute code from the highest canonical page. 873f55f0501SAndy Lutomirski * They'll speculate right off the end of the canonical space, and 874f55f0501SAndy Lutomirski * bad things happen. This is worked around in the same way as the 875f55f0501SAndy Lutomirski * Intel problem. 876f55f0501SAndy Lutomirski * 877f55f0501SAndy Lutomirski * With page table isolation enabled, we map the LDT in ... [stay tuned] 878bb898558SAl Viro */ 879ee00f4a3SKirill A. Shutemov #define TASK_SIZE_MAX ((1UL << __VIRTUAL_MASK_SHIFT) - PAGE_SIZE) 880bb898558SAl Viro 881ee00f4a3SKirill A. Shutemov #define DEFAULT_MAP_WINDOW ((1UL << 47) - PAGE_SIZE) 882bb898558SAl Viro 883bb898558SAl Viro /* This decides where the kernel will search for a free chunk of vm 884bb898558SAl Viro * space during mmap's. 885bb898558SAl Viro */ 886bb898558SAl Viro #define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? \ 887bb898558SAl Viro 0xc0000000 : 0xFFFFe000) 888bb898558SAl Viro 889b569bab7SKirill A. Shutemov #define TASK_SIZE_LOW (test_thread_flag(TIF_ADDR32) ? \ 890b569bab7SKirill A. Shutemov IA32_PAGE_OFFSET : DEFAULT_MAP_WINDOW) 8916bd33008SH. Peter Anvin #define TASK_SIZE (test_thread_flag(TIF_ADDR32) ? \ 892d9517346SIngo Molnar IA32_PAGE_OFFSET : TASK_SIZE_MAX) 8936bd33008SH. Peter Anvin #define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_ADDR32)) ? \ 894d9517346SIngo Molnar IA32_PAGE_OFFSET : TASK_SIZE_MAX) 895bb898558SAl Viro 896b569bab7SKirill A. Shutemov #define STACK_TOP TASK_SIZE_LOW 897d9517346SIngo Molnar #define STACK_TOP_MAX TASK_SIZE_MAX 898bb898558SAl Viro 899bb898558SAl Viro #define INIT_THREAD { \ 90013d4ea09SAndy Lutomirski .addr_limit = KERNEL_DS, \ 901bb898558SAl Viro } 902bb898558SAl Viro 90389240ba0SStefani Seibold extern unsigned long KSTK_ESP(struct task_struct *task); 904d046ff8bSH. J. Lu 905bb898558SAl Viro #endif /* CONFIG_X86_64 */ 906bb898558SAl Viro 907bb898558SAl Viro extern void start_thread(struct pt_regs *regs, unsigned long new_ip, 908bb898558SAl Viro unsigned long new_sp); 909bb898558SAl Viro 910bb898558SAl Viro /* 911bb898558SAl Viro * This decides where the kernel will search for a free chunk of vm 912bb898558SAl Viro * space during mmap's. 913bb898558SAl Viro */ 9148f3e474fSDmitry Safonov #define __TASK_UNMAPPED_BASE(task_size) (PAGE_ALIGN(task_size / 3)) 915b569bab7SKirill A. Shutemov #define TASK_UNMAPPED_BASE __TASK_UNMAPPED_BASE(TASK_SIZE_LOW) 916bb898558SAl Viro 917bb898558SAl Viro #define KSTK_EIP(task) (task_pt_regs(task)->ip) 918bb898558SAl Viro 919bb898558SAl Viro /* Get/set a process' ability to use the timestamp counter instruction */ 920bb898558SAl Viro #define GET_TSC_CTL(adr) get_tsc_mode((adr)) 921bb898558SAl Viro #define SET_TSC_CTL(val) set_tsc_mode((val)) 922bb898558SAl Viro 923bb898558SAl Viro extern int get_tsc_mode(unsigned long adr); 924bb898558SAl Viro extern int set_tsc_mode(unsigned int val); 925bb898558SAl Viro 926e9ea1e7fSKyle Huey DECLARE_PER_CPU(u64, msr_misc_features_shadow); 927e9ea1e7fSKyle Huey 928fe3d197fSDave Hansen /* Register/unregister a process' MPX related resource */ 92946a6e0cfSDave Hansen #define MPX_ENABLE_MANAGEMENT() mpx_enable_management() 93046a6e0cfSDave Hansen #define MPX_DISABLE_MANAGEMENT() mpx_disable_management() 931fe3d197fSDave Hansen 932fe3d197fSDave Hansen #ifdef CONFIG_X86_INTEL_MPX 93346a6e0cfSDave Hansen extern int mpx_enable_management(void); 93446a6e0cfSDave Hansen extern int mpx_disable_management(void); 935fe3d197fSDave Hansen #else 93646a6e0cfSDave Hansen static inline int mpx_enable_management(void) 937fe3d197fSDave Hansen { 938fe3d197fSDave Hansen return -EINVAL; 939fe3d197fSDave Hansen } 94046a6e0cfSDave Hansen static inline int mpx_disable_management(void) 941fe3d197fSDave Hansen { 942fe3d197fSDave Hansen return -EINVAL; 943fe3d197fSDave Hansen } 944fe3d197fSDave Hansen #endif /* CONFIG_X86_INTEL_MPX */ 945fe3d197fSDave Hansen 946bc8e80d5SBorislav Petkov #ifdef CONFIG_CPU_SUP_AMD 9478b84c8dfSDaniel J Blueman extern u16 amd_get_nb_id(int cpu); 948cc2749e4SAravind Gopalakrishnan extern u32 amd_get_nodes_per_socket(void); 949bc8e80d5SBorislav Petkov #else 950bc8e80d5SBorislav Petkov static inline u16 amd_get_nb_id(int cpu) { return 0; } 951bc8e80d5SBorislav Petkov static inline u32 amd_get_nodes_per_socket(void) { return 0; } 952bc8e80d5SBorislav Petkov #endif 9536a812691SAndreas Herrmann 95496e39ac0SJason Wang static inline uint32_t hypervisor_cpuid_base(const char *sig, uint32_t leaves) 95596e39ac0SJason Wang { 95696e39ac0SJason Wang uint32_t base, eax, signature[3]; 95796e39ac0SJason Wang 95896e39ac0SJason Wang for (base = 0x40000000; base < 0x40010000; base += 0x100) { 95996e39ac0SJason Wang cpuid(base, &eax, &signature[0], &signature[1], &signature[2]); 96096e39ac0SJason Wang 96196e39ac0SJason Wang if (!memcmp(sig, signature, 12) && 96296e39ac0SJason Wang (leaves == 0 || ((eax - base) >= leaves))) 96396e39ac0SJason Wang return base; 96496e39ac0SJason Wang } 96596e39ac0SJason Wang 96696e39ac0SJason Wang return 0; 96796e39ac0SJason Wang } 96896e39ac0SJason Wang 969f05e798aSDavid Howells extern unsigned long arch_align_stack(unsigned long sp); 970e5cb113fSAlexey Dobriyan void free_init_pages(const char *what, unsigned long begin, unsigned long end); 9716ea2738eSDave Hansen extern void free_kernel_image_pages(void *begin, void *end); 972f05e798aSDavid Howells 973f05e798aSDavid Howells void default_idle(void); 9746a377ddcSLen Brown #ifdef CONFIG_XEN 9756a377ddcSLen Brown bool xen_set_default_idle(void); 9766a377ddcSLen Brown #else 9776a377ddcSLen Brown #define xen_set_default_idle 0 9786a377ddcSLen Brown #endif 979f05e798aSDavid Howells 980f05e798aSDavid Howells void stop_this_cpu(void *dummy); 9814d067d8eSBorislav Petkov void df_debug(struct pt_regs *regs, long error_code); 9821008c52cSBorislav Petkov void microcode_check(void); 983d90a7a0eSJiri Kosina 984d90a7a0eSJiri Kosina enum l1tf_mitigations { 985d90a7a0eSJiri Kosina L1TF_MITIGATION_OFF, 986d90a7a0eSJiri Kosina L1TF_MITIGATION_FLUSH_NOWARN, 987d90a7a0eSJiri Kosina L1TF_MITIGATION_FLUSH, 988d90a7a0eSJiri Kosina L1TF_MITIGATION_FLUSH_NOSMT, 989d90a7a0eSJiri Kosina L1TF_MITIGATION_FULL, 990d90a7a0eSJiri Kosina L1TF_MITIGATION_FULL_FORCE 991d90a7a0eSJiri Kosina }; 992d90a7a0eSJiri Kosina 993d90a7a0eSJiri Kosina extern enum l1tf_mitigations l1tf_mitigation; 994d90a7a0eSJiri Kosina 995bc124170SThomas Gleixner enum mds_mitigations { 996bc124170SThomas Gleixner MDS_MITIGATION_OFF, 997bc124170SThomas Gleixner MDS_MITIGATION_FULL, 998*22dd8365SThomas Gleixner MDS_MITIGATION_VMWERV, 999bc124170SThomas Gleixner }; 1000bc124170SThomas Gleixner 10011965aae3SH. Peter Anvin #endif /* _ASM_X86_PROCESSOR_H */ 1002