1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 21965aae3SH. Peter Anvin #ifndef _ASM_X86_PROCESSOR_H 31965aae3SH. Peter Anvin #define _ASM_X86_PROCESSOR_H 4bb898558SAl Viro 5bb898558SAl Viro #include <asm/processor-flags.h> 6bb898558SAl Viro 7bb898558SAl Viro /* Forward declaration, a strange C thing */ 8bb898558SAl Viro struct task_struct; 9bb898558SAl Viro struct mm_struct; 109fda6a06SBrian Gerst struct vm86; 11bb898558SAl Viro 12bb898558SAl Viro #include <asm/math_emu.h> 13bb898558SAl Viro #include <asm/segment.h> 14bb898558SAl Viro #include <asm/types.h> 15decb4c41SIngo Molnar #include <uapi/asm/sigcontext.h> 16bb898558SAl Viro #include <asm/current.h> 17cd4d09ecSBorislav Petkov #include <asm/cpufeatures.h> 18bb898558SAl Viro #include <asm/page.h> 1954321d94SJeremy Fitzhardinge #include <asm/pgtable_types.h> 20bb898558SAl Viro #include <asm/percpu.h> 21bb898558SAl Viro #include <asm/msr.h> 22bb898558SAl Viro #include <asm/desc_defs.h> 23bb898558SAl Viro #include <asm/nops.h> 24f05e798aSDavid Howells #include <asm/special_insns.h> 2514b9675aSIngo Molnar #include <asm/fpu/types.h> 2676846bf3SJosh Poimboeuf #include <asm/unwind_hints.h> 27bb898558SAl Viro 28bb898558SAl Viro #include <linux/personality.h> 29bb898558SAl Viro #include <linux/cache.h> 30bb898558SAl Viro #include <linux/threads.h> 315cbc19a9SPeter Zijlstra #include <linux/math64.h> 32faa4602eSPeter Zijlstra #include <linux/err.h> 33f05e798aSDavid Howells #include <linux/irqflags.h> 3421729f81STom Lendacky #include <linux/mem_encrypt.h> 35f05e798aSDavid Howells 36f05e798aSDavid Howells /* 37f05e798aSDavid Howells * We handle most unaligned accesses in hardware. On the other hand 38f05e798aSDavid Howells * unaligned DMA can be quite expensive on some Nehalem processors. 39f05e798aSDavid Howells * 40f05e798aSDavid Howells * Based on this we disable the IP header alignment in network drivers. 41f05e798aSDavid Howells */ 42f05e798aSDavid Howells #define NET_IP_ALIGN 0 43bb898558SAl Viro 44b332828cSK.Prasad #define HBP_NUM 4 45bb898558SAl Viro /* 46bb898558SAl Viro * Default implementation of macro that returns current 47bb898558SAl Viro * instruction pointer ("program counter"). 48bb898558SAl Viro */ 49bb898558SAl Viro static inline void *current_text_addr(void) 50bb898558SAl Viro { 51bb898558SAl Viro void *pc; 52bb898558SAl Viro 53bb898558SAl Viro asm volatile("mov $1f, %0; 1:":"=r" (pc)); 54bb898558SAl Viro 55bb898558SAl Viro return pc; 56bb898558SAl Viro } 57bb898558SAl Viro 58b8c1b8eaSIngo Molnar /* 59b8c1b8eaSIngo Molnar * These alignment constraints are for performance in the vSMP case, 60b8c1b8eaSIngo Molnar * but in the task_struct case we must also meet hardware imposed 61b8c1b8eaSIngo Molnar * alignment requirements of the FPU state: 62b8c1b8eaSIngo Molnar */ 63bb898558SAl Viro #ifdef CONFIG_X86_VSMP 64bb898558SAl Viro # define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT) 65bb898558SAl Viro # define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT) 66bb898558SAl Viro #else 67b8c1b8eaSIngo Molnar # define ARCH_MIN_TASKALIGN __alignof__(union fpregs_state) 68bb898558SAl Viro # define ARCH_MIN_MMSTRUCT_ALIGN 0 69bb898558SAl Viro #endif 70bb898558SAl Viro 71e0ba94f1SAlex Shi enum tlb_infos { 72e0ba94f1SAlex Shi ENTRIES, 73e0ba94f1SAlex Shi NR_INFO 74e0ba94f1SAlex Shi }; 75e0ba94f1SAlex Shi 76e0ba94f1SAlex Shi extern u16 __read_mostly tlb_lli_4k[NR_INFO]; 77e0ba94f1SAlex Shi extern u16 __read_mostly tlb_lli_2m[NR_INFO]; 78e0ba94f1SAlex Shi extern u16 __read_mostly tlb_lli_4m[NR_INFO]; 79e0ba94f1SAlex Shi extern u16 __read_mostly tlb_lld_4k[NR_INFO]; 80e0ba94f1SAlex Shi extern u16 __read_mostly tlb_lld_2m[NR_INFO]; 81e0ba94f1SAlex Shi extern u16 __read_mostly tlb_lld_4m[NR_INFO]; 82dd360393SKirill A. Shutemov extern u16 __read_mostly tlb_lld_1g[NR_INFO]; 83c4211f42SAlex Shi 84bb898558SAl Viro /* 85bb898558SAl Viro * CPU type and hardware bug flags. Kept separately for each CPU. 8604402116SMathias Krause * Members of this structure are referenced in head_32.S, so think twice 87bb898558SAl Viro * before touching them. [mj] 88bb898558SAl Viro */ 89bb898558SAl Viro 90bb898558SAl Viro struct cpuinfo_x86 { 91bb898558SAl Viro __u8 x86; /* CPU family */ 92bb898558SAl Viro __u8 x86_vendor; /* CPU vendor */ 93bb898558SAl Viro __u8 x86_model; 94b399151cSJia Zhang __u8 x86_stepping; 956415813bSMathias Krause #ifdef CONFIG_X86_64 96bb898558SAl Viro /* Number of 4K pages in DTLB/ITLB combined(in pages): */ 97bb898558SAl Viro int x86_tlbsize; 9813c6c532SJan Beulich #endif 99bb898558SAl Viro __u8 x86_virt_bits; 100bb898558SAl Viro __u8 x86_phys_bits; 101bb898558SAl Viro /* CPUID returned core id bits: */ 102bb898558SAl Viro __u8 x86_coreid_bits; 10379a8b9aaSBorislav Petkov __u8 cu_id; 104bb898558SAl Viro /* Max extended CPUID function supported: */ 105bb898558SAl Viro __u32 extended_cpuid_level; 106bb898558SAl Viro /* Maximum supported CPUID level, -1=no CPUID: */ 107bb898558SAl Viro int cpuid_level; 10865fc985bSBorislav Petkov __u32 x86_capability[NCAPINTS + NBUGINTS]; 109bb898558SAl Viro char x86_vendor_id[16]; 110bb898558SAl Viro char x86_model_id[64]; 111bb898558SAl Viro /* in KB - valid for CPUS which support this call: */ 11224dbc600SGustavo A. R. Silva unsigned int x86_cache_size; 113bb898558SAl Viro int x86_cache_alignment; /* In bytes */ 114cbc82b17SPeter P Waskiewicz Jr /* Cache QoS architectural values: */ 115cbc82b17SPeter P Waskiewicz Jr int x86_cache_max_rmid; /* max index */ 116cbc82b17SPeter P Waskiewicz Jr int x86_cache_occ_scale; /* scale to bytes */ 117bb898558SAl Viro int x86_power; 118bb898558SAl Viro unsigned long loops_per_jiffy; 119bb898558SAl Viro /* cpuid returned max cores value: */ 120bb898558SAl Viro u16 x86_max_cores; 121bb898558SAl Viro u16 apicid; 122bb898558SAl Viro u16 initial_apicid; 123bb898558SAl Viro u16 x86_clflush_size; 124bb898558SAl Viro /* number of cores as seen by the OS: */ 125bb898558SAl Viro u16 booted_cores; 126bb898558SAl Viro /* Physical processor id: */ 127bb898558SAl Viro u16 phys_proc_id; 1281f12e32fSThomas Gleixner /* Logical processor id: */ 1291f12e32fSThomas Gleixner u16 logical_proc_id; 130bb898558SAl Viro /* Core id: */ 131bb898558SAl Viro u16 cpu_core_id; 132bb898558SAl Viro /* Index into per_cpu list: */ 133bb898558SAl Viro u16 cpu_index; 134506ed6b5SAndi Kleen u32 microcode; 13530bb9811SAndi Kleen unsigned initialized : 1; 1363859a271SKees Cook } __randomize_layout; 137bb898558SAl Viro 13847f10a36SHe Chen struct cpuid_regs { 13947f10a36SHe Chen u32 eax, ebx, ecx, edx; 14047f10a36SHe Chen }; 14147f10a36SHe Chen 14247f10a36SHe Chen enum cpuid_regs_idx { 14347f10a36SHe Chen CPUID_EAX = 0, 14447f10a36SHe Chen CPUID_EBX, 14547f10a36SHe Chen CPUID_ECX, 14647f10a36SHe Chen CPUID_EDX, 14747f10a36SHe Chen }; 14847f10a36SHe Chen 149bb898558SAl Viro #define X86_VENDOR_INTEL 0 150bb898558SAl Viro #define X86_VENDOR_CYRIX 1 151bb898558SAl Viro #define X86_VENDOR_AMD 2 152bb898558SAl Viro #define X86_VENDOR_UMC 3 153bb898558SAl Viro #define X86_VENDOR_CENTAUR 5 154bb898558SAl Viro #define X86_VENDOR_TRANSMETA 7 155bb898558SAl Viro #define X86_VENDOR_NSC 8 156bb898558SAl Viro #define X86_VENDOR_NUM 9 157bb898558SAl Viro 158bb898558SAl Viro #define X86_VENDOR_UNKNOWN 0xff 159bb898558SAl Viro 160bb898558SAl Viro /* 161bb898558SAl Viro * capabilities of CPUs 162bb898558SAl Viro */ 163bb898558SAl Viro extern struct cpuinfo_x86 boot_cpu_data; 164bb898558SAl Viro extern struct cpuinfo_x86 new_cpu_data; 165bb898558SAl Viro 1667fb983b4SAndy Lutomirski extern struct x86_hw_tss doublefault_tss; 1676cbd2171SThomas Gleixner extern __u32 cpu_caps_cleared[NCAPINTS + NBUGINTS]; 1686cbd2171SThomas Gleixner extern __u32 cpu_caps_set[NCAPINTS + NBUGINTS]; 169bb898558SAl Viro 170bb898558SAl Viro #ifdef CONFIG_SMP 1712c773dd3SJan Beulich DECLARE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info); 172bb898558SAl Viro #define cpu_data(cpu) per_cpu(cpu_info, cpu) 173bb898558SAl Viro #else 1747b543a53STejun Heo #define cpu_info boot_cpu_data 175bb898558SAl Viro #define cpu_data(cpu) boot_cpu_data 176bb898558SAl Viro #endif 177bb898558SAl Viro 178bb898558SAl Viro extern const struct seq_operations cpuinfo_op; 179bb898558SAl Viro 180bb898558SAl Viro #define cache_line_size() (boot_cpu_data.x86_cache_alignment) 181bb898558SAl Viro 182bb898558SAl Viro extern void cpu_detect(struct cpuinfo_x86 *c); 183bb898558SAl Viro 184bb898558SAl Viro extern void early_cpu_init(void); 185bb898558SAl Viro extern void identify_boot_cpu(void); 186bb898558SAl Viro extern void identify_secondary_cpu(struct cpuinfo_x86 *); 187bb898558SAl Viro extern void print_cpu_info(struct cpuinfo_x86 *); 18821c3fcf3SYinghai Lu void print_cpu_msr(struct cpuinfo_x86 *); 189bb898558SAl Viro extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c); 19047bdf337SHe Chen extern u32 get_scattered_cpuid_leaf(unsigned int level, 19147bdf337SHe Chen unsigned int sub_leaf, 19247bdf337SHe Chen enum cpuid_regs_idx reg); 193bb898558SAl Viro extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c); 19404a15418SAndreas Herrmann extern void init_amd_cacheinfo(struct cpuinfo_x86 *c); 195bb898558SAl Viro 196bb898558SAl Viro extern void detect_extended_topology(struct cpuinfo_x86 *c); 197bb898558SAl Viro extern void detect_ht(struct cpuinfo_x86 *c); 198bb898558SAl Viro 199d288e1cfSFenghua Yu #ifdef CONFIG_X86_32 200d288e1cfSFenghua Yu extern int have_cpuid_p(void); 201d288e1cfSFenghua Yu #else 202d288e1cfSFenghua Yu static inline int have_cpuid_p(void) 203d288e1cfSFenghua Yu { 204d288e1cfSFenghua Yu return 1; 205d288e1cfSFenghua Yu } 206d288e1cfSFenghua Yu #endif 207bb898558SAl Viro static inline void native_cpuid(unsigned int *eax, unsigned int *ebx, 208bb898558SAl Viro unsigned int *ecx, unsigned int *edx) 209bb898558SAl Viro { 210bb898558SAl Viro /* ecx is often an input as well as an output. */ 21145a94d7cSSuresh Siddha asm volatile("cpuid" 212bb898558SAl Viro : "=a" (*eax), 213bb898558SAl Viro "=b" (*ebx), 214bb898558SAl Viro "=c" (*ecx), 215bb898558SAl Viro "=d" (*edx) 216506ed6b5SAndi Kleen : "0" (*eax), "2" (*ecx) 217506ed6b5SAndi Kleen : "memory"); 218bb898558SAl Viro } 219bb898558SAl Viro 2205dedade6SBorislav Petkov #define native_cpuid_reg(reg) \ 2215dedade6SBorislav Petkov static inline unsigned int native_cpuid_##reg(unsigned int op) \ 2225dedade6SBorislav Petkov { \ 2235dedade6SBorislav Petkov unsigned int eax = op, ebx, ecx = 0, edx; \ 2245dedade6SBorislav Petkov \ 2255dedade6SBorislav Petkov native_cpuid(&eax, &ebx, &ecx, &edx); \ 2265dedade6SBorislav Petkov \ 2275dedade6SBorislav Petkov return reg; \ 2285dedade6SBorislav Petkov } 2295dedade6SBorislav Petkov 2305dedade6SBorislav Petkov /* 2315dedade6SBorislav Petkov * Native CPUID functions returning a single datum. 2325dedade6SBorislav Petkov */ 2335dedade6SBorislav Petkov native_cpuid_reg(eax) 2345dedade6SBorislav Petkov native_cpuid_reg(ebx) 2355dedade6SBorislav Petkov native_cpuid_reg(ecx) 2365dedade6SBorislav Petkov native_cpuid_reg(edx) 2375dedade6SBorislav Petkov 2386c690ee1SAndy Lutomirski /* 2396c690ee1SAndy Lutomirski * Friendlier CR3 helpers. 2406c690ee1SAndy Lutomirski */ 2416c690ee1SAndy Lutomirski static inline unsigned long read_cr3_pa(void) 2426c690ee1SAndy Lutomirski { 2436c690ee1SAndy Lutomirski return __read_cr3() & CR3_ADDR_MASK; 2446c690ee1SAndy Lutomirski } 2456c690ee1SAndy Lutomirski 246eef9c4abSTom Lendacky static inline unsigned long native_read_cr3_pa(void) 247eef9c4abSTom Lendacky { 248eef9c4abSTom Lendacky return __native_read_cr3() & CR3_ADDR_MASK; 249eef9c4abSTom Lendacky } 250eef9c4abSTom Lendacky 251bb898558SAl Viro static inline void load_cr3(pgd_t *pgdir) 252bb898558SAl Viro { 25321729f81STom Lendacky write_cr3(__sme_pa(pgdir)); 254bb898558SAl Viro } 255bb898558SAl Viro 2567fb983b4SAndy Lutomirski /* 2577fb983b4SAndy Lutomirski * Note that while the legacy 'TSS' name comes from 'Task State Segment', 2587fb983b4SAndy Lutomirski * on modern x86 CPUs the TSS also holds information important to 64-bit mode, 2597fb983b4SAndy Lutomirski * unrelated to the task-switch mechanism: 2607fb983b4SAndy Lutomirski */ 261bb898558SAl Viro #ifdef CONFIG_X86_32 262bb898558SAl Viro /* This is the TSS defined by the hardware. */ 263bb898558SAl Viro struct x86_hw_tss { 264bb898558SAl Viro unsigned short back_link, __blh; 265bb898558SAl Viro unsigned long sp0; 266bb898558SAl Viro unsigned short ss0, __ss0h; 267cf9328ccSAndy Lutomirski unsigned long sp1; 26876e4c490SAndy Lutomirski 26976e4c490SAndy Lutomirski /* 270cf9328ccSAndy Lutomirski * We don't use ring 1, so ss1 is a convenient scratch space in 271cf9328ccSAndy Lutomirski * the same cacheline as sp0. We use ss1 to cache the value in 272cf9328ccSAndy Lutomirski * MSR_IA32_SYSENTER_CS. When we context switch 273cf9328ccSAndy Lutomirski * MSR_IA32_SYSENTER_CS, we first check if the new value being 274cf9328ccSAndy Lutomirski * written matches ss1, and, if it's not, then we wrmsr the new 275cf9328ccSAndy Lutomirski * value and update ss1. 27676e4c490SAndy Lutomirski * 277cf9328ccSAndy Lutomirski * The only reason we context switch MSR_IA32_SYSENTER_CS is 278cf9328ccSAndy Lutomirski * that we set it to zero in vm86 tasks to avoid corrupting the 279cf9328ccSAndy Lutomirski * stack if we were to go through the sysenter path from vm86 280cf9328ccSAndy Lutomirski * mode. 28176e4c490SAndy Lutomirski */ 28276e4c490SAndy Lutomirski unsigned short ss1; /* MSR_IA32_SYSENTER_CS */ 28376e4c490SAndy Lutomirski 28476e4c490SAndy Lutomirski unsigned short __ss1h; 285bb898558SAl Viro unsigned long sp2; 286bb898558SAl Viro unsigned short ss2, __ss2h; 287bb898558SAl Viro unsigned long __cr3; 288bb898558SAl Viro unsigned long ip; 289bb898558SAl Viro unsigned long flags; 290bb898558SAl Viro unsigned long ax; 291bb898558SAl Viro unsigned long cx; 292bb898558SAl Viro unsigned long dx; 293bb898558SAl Viro unsigned long bx; 294bb898558SAl Viro unsigned long sp; 295bb898558SAl Viro unsigned long bp; 296bb898558SAl Viro unsigned long si; 297bb898558SAl Viro unsigned long di; 298bb898558SAl Viro unsigned short es, __esh; 299bb898558SAl Viro unsigned short cs, __csh; 300bb898558SAl Viro unsigned short ss, __ssh; 301bb898558SAl Viro unsigned short ds, __dsh; 302bb898558SAl Viro unsigned short fs, __fsh; 303bb898558SAl Viro unsigned short gs, __gsh; 304bb898558SAl Viro unsigned short ldt, __ldth; 305bb898558SAl Viro unsigned short trace; 306bb898558SAl Viro unsigned short io_bitmap_base; 307bb898558SAl Viro 308bb898558SAl Viro } __attribute__((packed)); 309bb898558SAl Viro #else 310bb898558SAl Viro struct x86_hw_tss { 311bb898558SAl Viro u32 reserved1; 312bb898558SAl Viro u64 sp0; 3139aaefe7bSAndy Lutomirski 3149aaefe7bSAndy Lutomirski /* 3159aaefe7bSAndy Lutomirski * We store cpu_current_top_of_stack in sp1 so it's always accessible. 3169aaefe7bSAndy Lutomirski * Linux does not use ring 1, so sp1 is not otherwise needed. 3179aaefe7bSAndy Lutomirski */ 318bb898558SAl Viro u64 sp1; 3199aaefe7bSAndy Lutomirski 320bb898558SAl Viro u64 sp2; 321bb898558SAl Viro u64 reserved2; 322bb898558SAl Viro u64 ist[7]; 323bb898558SAl Viro u32 reserved3; 324bb898558SAl Viro u32 reserved4; 325bb898558SAl Viro u16 reserved5; 326bb898558SAl Viro u16 io_bitmap_base; 327bb898558SAl Viro 328d3273deaSAndy Lutomirski } __attribute__((packed)); 329bb898558SAl Viro #endif 330bb898558SAl Viro 331bb898558SAl Viro /* 332bb898558SAl Viro * IO-bitmap sizes: 333bb898558SAl Viro */ 334bb898558SAl Viro #define IO_BITMAP_BITS 65536 335bb898558SAl Viro #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8) 336bb898558SAl Viro #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long)) 3377fb983b4SAndy Lutomirski #define IO_BITMAP_OFFSET (offsetof(struct tss_struct, io_bitmap) - offsetof(struct tss_struct, x86_tss)) 338bb898558SAl Viro #define INVALID_IO_BITMAP_OFFSET 0x8000 339bb898558SAl Viro 3404fe2d8b1SDave Hansen struct entry_stack { 3410f9a4810SAndy Lutomirski unsigned long words[64]; 3420f9a4810SAndy Lutomirski }; 3430f9a4810SAndy Lutomirski 3444fe2d8b1SDave Hansen struct entry_stack_page { 3454fe2d8b1SDave Hansen struct entry_stack stack; 346c482feefSAndy Lutomirski } __aligned(PAGE_SIZE); 3471a935bc3SAndy Lutomirski 348bb898558SAl Viro struct tss_struct { 349bb898558SAl Viro /* 3501a935bc3SAndy Lutomirski * The fixed hardware portion. This must not cross a page boundary 3511a935bc3SAndy Lutomirski * at risk of violating the SDM's advice and potentially triggering 3521a935bc3SAndy Lutomirski * errata. 353bb898558SAl Viro */ 354bb898558SAl Viro struct x86_hw_tss x86_tss; 355bb898558SAl Viro 356bb898558SAl Viro /* 357bb898558SAl Viro * The extra 1 is there because the CPU will access an 358bb898558SAl Viro * additional byte beyond the end of the IO permission 359bb898558SAl Viro * bitmap. The extra byte must be all 1 bits, and must 360bb898558SAl Viro * be within the limit. 361bb898558SAl Viro */ 362bb898558SAl Viro unsigned long io_bitmap[IO_BITMAP_LONGS + 1]; 3631a935bc3SAndy Lutomirski } __aligned(PAGE_SIZE); 364bb898558SAl Viro 365c482feefSAndy Lutomirski DECLARE_PER_CPU_PAGE_ALIGNED(struct tss_struct, cpu_tss_rw); 366bb898558SAl Viro 3674f53ab14SAndy Lutomirski /* 3684f53ab14SAndy Lutomirski * sizeof(unsigned long) coming from an extra "long" at the end 3694f53ab14SAndy Lutomirski * of the iobitmap. 3704f53ab14SAndy Lutomirski * 3714f53ab14SAndy Lutomirski * -1? seg base+limit should be pointing to the address of the 3724f53ab14SAndy Lutomirski * last valid byte 3734f53ab14SAndy Lutomirski */ 3744f53ab14SAndy Lutomirski #define __KERNEL_TSS_LIMIT \ 3754f53ab14SAndy Lutomirski (IO_BITMAP_OFFSET + IO_BITMAP_BYTES + sizeof(unsigned long) - 1) 3764f53ab14SAndy Lutomirski 377a7fcf28dSAndy Lutomirski #ifdef CONFIG_X86_32 378a7fcf28dSAndy Lutomirski DECLARE_PER_CPU(unsigned long, cpu_current_top_of_stack); 3799aaefe7bSAndy Lutomirski #else 380c482feefSAndy Lutomirski /* The RO copy can't be accessed with this_cpu_xyz(), so use the RW copy. */ 381c482feefSAndy Lutomirski #define cpu_current_top_of_stack cpu_tss_rw.x86_tss.sp1 382a7fcf28dSAndy Lutomirski #endif 383a7fcf28dSAndy Lutomirski 384bb898558SAl Viro /* 385bb898558SAl Viro * Save the original ist values for checking stack pointers during debugging 386bb898558SAl Viro */ 387bb898558SAl Viro struct orig_ist { 388bb898558SAl Viro unsigned long ist[7]; 389bb898558SAl Viro }; 390bb898558SAl Viro 391bb898558SAl Viro #ifdef CONFIG_X86_64 392bb898558SAl Viro DECLARE_PER_CPU(struct orig_ist, orig_ist); 39326f80bd6SBrian Gerst 394947e76cdSBrian Gerst union irq_stack_union { 395947e76cdSBrian Gerst char irq_stack[IRQ_STACK_SIZE]; 396947e76cdSBrian Gerst /* 397947e76cdSBrian Gerst * GCC hardcodes the stack canary as %gs:40. Since the 398947e76cdSBrian Gerst * irq_stack is the object at %gs:0, we reserve the bottom 399947e76cdSBrian Gerst * 48 bytes of the irq stack for the canary. 400947e76cdSBrian Gerst */ 401947e76cdSBrian Gerst struct { 402947e76cdSBrian Gerst char gs_base[40]; 403947e76cdSBrian Gerst unsigned long stack_canary; 404947e76cdSBrian Gerst }; 405947e76cdSBrian Gerst }; 406947e76cdSBrian Gerst 407277d5b40SAndi Kleen DECLARE_PER_CPU_FIRST(union irq_stack_union, irq_stack_union) __visible; 4082add8e23SBrian Gerst DECLARE_INIT_PER_CPU(irq_stack_union); 4092add8e23SBrian Gerst 41026f80bd6SBrian Gerst DECLARE_PER_CPU(char *, irq_stack_ptr); 4119766cdbcSJaswinder Singh Rajput DECLARE_PER_CPU(unsigned int, irq_count); 4129766cdbcSJaswinder Singh Rajput extern asmlinkage void ignore_sysret(void); 41360a5317fSTejun Heo #else /* X86_64 */ 41460a5317fSTejun Heo #ifdef CONFIG_CC_STACKPROTECTOR 4151ea0d14eSJeremy Fitzhardinge /* 4161ea0d14eSJeremy Fitzhardinge * Make sure stack canary segment base is cached-aligned: 4171ea0d14eSJeremy Fitzhardinge * "For Intel Atom processors, avoid non zero segment base address 4181ea0d14eSJeremy Fitzhardinge * that is not aligned to cache line boundary at all cost." 4191ea0d14eSJeremy Fitzhardinge * (Optim Ref Manual Assembly/Compiler Coding Rule 15.) 4201ea0d14eSJeremy Fitzhardinge */ 4211ea0d14eSJeremy Fitzhardinge struct stack_canary { 4221ea0d14eSJeremy Fitzhardinge char __pad[20]; /* canary at %gs:20 */ 4231ea0d14eSJeremy Fitzhardinge unsigned long canary; 4241ea0d14eSJeremy Fitzhardinge }; 42553f82452SJeremy Fitzhardinge DECLARE_PER_CPU_ALIGNED(struct stack_canary, stack_canary); 426bb898558SAl Viro #endif 427198d208dSSteven Rostedt /* 428198d208dSSteven Rostedt * per-CPU IRQ handling stacks 429198d208dSSteven Rostedt */ 430198d208dSSteven Rostedt struct irq_stack { 431198d208dSSteven Rostedt u32 stack[THREAD_SIZE/sizeof(u32)]; 432198d208dSSteven Rostedt } __aligned(THREAD_SIZE); 433198d208dSSteven Rostedt 434198d208dSSteven Rostedt DECLARE_PER_CPU(struct irq_stack *, hardirq_stack); 435198d208dSSteven Rostedt DECLARE_PER_CPU(struct irq_stack *, softirq_stack); 43660a5317fSTejun Heo #endif /* X86_64 */ 437bb898558SAl Viro 438bf15a8cfSFenghua Yu extern unsigned int fpu_kernel_xstate_size; 439a1141e0bSFenghua Yu extern unsigned int fpu_user_xstate_size; 440bb898558SAl Viro 44124f1e32cSFrederic Weisbecker struct perf_event; 44224f1e32cSFrederic Weisbecker 44313d4ea09SAndy Lutomirski typedef struct { 44413d4ea09SAndy Lutomirski unsigned long seg; 44513d4ea09SAndy Lutomirski } mm_segment_t; 44613d4ea09SAndy Lutomirski 447bb898558SAl Viro struct thread_struct { 448bb898558SAl Viro /* Cached TLS descriptors: */ 449bb898558SAl Viro struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES]; 450d375cf15SAndy Lutomirski #ifdef CONFIG_X86_32 451bb898558SAl Viro unsigned long sp0; 452d375cf15SAndy Lutomirski #endif 453bb898558SAl Viro unsigned long sp; 454bb898558SAl Viro #ifdef CONFIG_X86_32 455bb898558SAl Viro unsigned long sysenter_cs; 456bb898558SAl Viro #else 457bb898558SAl Viro unsigned short es; 458bb898558SAl Viro unsigned short ds; 459bb898558SAl Viro unsigned short fsindex; 460bb898558SAl Viro unsigned short gsindex; 461bb898558SAl Viro #endif 462b9d989c7SAndy Lutomirski 463d756f4adSAlexey Dobriyan #ifdef CONFIG_X86_64 464296f781aSAndy Lutomirski unsigned long fsbase; 465296f781aSAndy Lutomirski unsigned long gsbase; 466296f781aSAndy Lutomirski #else 467296f781aSAndy Lutomirski /* 468296f781aSAndy Lutomirski * XXX: this could presumably be unsigned short. Alternatively, 469296f781aSAndy Lutomirski * 32-bit kernels could be taught to use fsindex instead. 470296f781aSAndy Lutomirski */ 471bb898558SAl Viro unsigned long fs; 472bb898558SAl Viro unsigned long gs; 473296f781aSAndy Lutomirski #endif 474c5bedc68SIngo Molnar 47524f1e32cSFrederic Weisbecker /* Save middle states of ptrace breakpoints */ 47624f1e32cSFrederic Weisbecker struct perf_event *ptrace_bps[HBP_NUM]; 47724f1e32cSFrederic Weisbecker /* Debug status used for traps, single steps, etc... */ 478bb898558SAl Viro unsigned long debugreg6; 479326264a0SFrederic Weisbecker /* Keep track of the exact dr7 value set by the user */ 480326264a0SFrederic Weisbecker unsigned long ptrace_dr7; 481bb898558SAl Viro /* Fault info: */ 482bb898558SAl Viro unsigned long cr2; 48351e7dc70SSrikar Dronamraju unsigned long trap_nr; 484bb898558SAl Viro unsigned long error_code; 4859fda6a06SBrian Gerst #ifdef CONFIG_VM86 486bb898558SAl Viro /* Virtual 86 mode info */ 4879fda6a06SBrian Gerst struct vm86 *vm86; 488bb898558SAl Viro #endif 489bb898558SAl Viro /* IO permissions: */ 490bb898558SAl Viro unsigned long *io_bitmap_ptr; 491bb898558SAl Viro unsigned long iopl; 492bb898558SAl Viro /* Max allowed port in the bitmap, in bytes: */ 493bb898558SAl Viro unsigned io_bitmap_max; 4940c8c0f03SDave Hansen 49513d4ea09SAndy Lutomirski mm_segment_t addr_limit; 49613d4ea09SAndy Lutomirski 4972a53ccbcSIngo Molnar unsigned int sig_on_uaccess_err:1; 498dfa9a942SAndy Lutomirski unsigned int uaccess_err:1; /* uaccess failed */ 499dfa9a942SAndy Lutomirski 5000c8c0f03SDave Hansen /* Floating point and extended processor state */ 5010c8c0f03SDave Hansen struct fpu fpu; 5020c8c0f03SDave Hansen /* 5030c8c0f03SDave Hansen * WARNING: 'fpu' is dynamically-sized. It *MUST* be at 5040c8c0f03SDave Hansen * the end. 5050c8c0f03SDave Hansen */ 506bb898558SAl Viro }; 507bb898558SAl Viro 508f7d83c1cSKees Cook /* Whitelist the FPU state from the task_struct for hardened usercopy. */ 509f7d83c1cSKees Cook static inline void arch_thread_struct_whitelist(unsigned long *offset, 510f7d83c1cSKees Cook unsigned long *size) 511f7d83c1cSKees Cook { 512f7d83c1cSKees Cook *offset = offsetof(struct thread_struct, fpu.state); 513f7d83c1cSKees Cook *size = fpu_kernel_xstate_size; 514f7d83c1cSKees Cook } 515f7d83c1cSKees Cook 516bb898558SAl Viro /* 517b9d989c7SAndy Lutomirski * Thread-synchronous status. 518b9d989c7SAndy Lutomirski * 519b9d989c7SAndy Lutomirski * This is different from the flags in that nobody else 520b9d989c7SAndy Lutomirski * ever touches our thread-synchronous status, so we don't 521b9d989c7SAndy Lutomirski * have to worry about atomic accesses. 522b9d989c7SAndy Lutomirski */ 523b9d989c7SAndy Lutomirski #define TS_COMPAT 0x0002 /* 32bit syscall active (64BIT)*/ 524b9d989c7SAndy Lutomirski 525b9d989c7SAndy Lutomirski /* 526bb898558SAl Viro * Set IOPL bits in EFLAGS from given mask 527bb898558SAl Viro */ 528bb898558SAl Viro static inline void native_set_iopl_mask(unsigned mask) 529bb898558SAl Viro { 530bb898558SAl Viro #ifdef CONFIG_X86_32 531bb898558SAl Viro unsigned int reg; 532bb898558SAl Viro 533bb898558SAl Viro asm volatile ("pushfl;" 534bb898558SAl Viro "popl %0;" 535bb898558SAl Viro "andl %1, %0;" 536bb898558SAl Viro "orl %2, %0;" 537bb898558SAl Viro "pushl %0;" 538bb898558SAl Viro "popfl" 539bb898558SAl Viro : "=&r" (reg) 540bb898558SAl Viro : "i" (~X86_EFLAGS_IOPL), "r" (mask)); 541bb898558SAl Viro #endif 542bb898558SAl Viro } 543bb898558SAl Viro 544bb898558SAl Viro static inline void 545da51da18SAndy Lutomirski native_load_sp0(unsigned long sp0) 546bb898558SAl Viro { 547c482feefSAndy Lutomirski this_cpu_write(cpu_tss_rw.x86_tss.sp0, sp0); 548bb898558SAl Viro } 549bb898558SAl Viro 550bb898558SAl Viro static inline void native_swapgs(void) 551bb898558SAl Viro { 552bb898558SAl Viro #ifdef CONFIG_X86_64 553bb898558SAl Viro asm volatile("swapgs" ::: "memory"); 554bb898558SAl Viro #endif 555bb898558SAl Viro } 556bb898558SAl Viro 557a7fcf28dSAndy Lutomirski static inline unsigned long current_top_of_stack(void) 5588ef46a67SAndy Lutomirski { 5599aaefe7bSAndy Lutomirski /* 5609aaefe7bSAndy Lutomirski * We can't read directly from tss.sp0: sp0 on x86_32 is special in 5619aaefe7bSAndy Lutomirski * and around vm86 mode and sp0 on x86_64 is special because of the 5629aaefe7bSAndy Lutomirski * entry trampoline. 5639aaefe7bSAndy Lutomirski */ 564a7fcf28dSAndy Lutomirski return this_cpu_read_stable(cpu_current_top_of_stack); 5658ef46a67SAndy Lutomirski } 5668ef46a67SAndy Lutomirski 5673383642cSAndy Lutomirski static inline bool on_thread_stack(void) 5683383642cSAndy Lutomirski { 5693383642cSAndy Lutomirski return (unsigned long)(current_top_of_stack() - 5703383642cSAndy Lutomirski current_stack_pointer) < THREAD_SIZE; 5713383642cSAndy Lutomirski } 5723383642cSAndy Lutomirski 573bb898558SAl Viro #ifdef CONFIG_PARAVIRT 574bb898558SAl Viro #include <asm/paravirt.h> 575bb898558SAl Viro #else 576bb898558SAl Viro #define __cpuid native_cpuid 577bb898558SAl Viro 578da51da18SAndy Lutomirski static inline void load_sp0(unsigned long sp0) 579bb898558SAl Viro { 580da51da18SAndy Lutomirski native_load_sp0(sp0); 581bb898558SAl Viro } 582bb898558SAl Viro 583bb898558SAl Viro #define set_iopl_mask native_set_iopl_mask 584bb898558SAl Viro #endif /* CONFIG_PARAVIRT */ 585bb898558SAl Viro 586bb898558SAl Viro /* Free all resources held by a thread. */ 587bb898558SAl Viro extern void release_thread(struct task_struct *); 588bb898558SAl Viro 589bb898558SAl Viro unsigned long get_wchan(struct task_struct *p); 590bb898558SAl Viro 591bb898558SAl Viro /* 592bb898558SAl Viro * Generic CPUID function 593bb898558SAl Viro * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx 594bb898558SAl Viro * resulting in stale register contents being returned. 595bb898558SAl Viro */ 596bb898558SAl Viro static inline void cpuid(unsigned int op, 597bb898558SAl Viro unsigned int *eax, unsigned int *ebx, 598bb898558SAl Viro unsigned int *ecx, unsigned int *edx) 599bb898558SAl Viro { 600bb898558SAl Viro *eax = op; 601bb898558SAl Viro *ecx = 0; 602bb898558SAl Viro __cpuid(eax, ebx, ecx, edx); 603bb898558SAl Viro } 604bb898558SAl Viro 605bb898558SAl Viro /* Some CPUID calls want 'count' to be placed in ecx */ 606bb898558SAl Viro static inline void cpuid_count(unsigned int op, int count, 607bb898558SAl Viro unsigned int *eax, unsigned int *ebx, 608bb898558SAl Viro unsigned int *ecx, unsigned int *edx) 609bb898558SAl Viro { 610bb898558SAl Viro *eax = op; 611bb898558SAl Viro *ecx = count; 612bb898558SAl Viro __cpuid(eax, ebx, ecx, edx); 613bb898558SAl Viro } 614bb898558SAl Viro 615bb898558SAl Viro /* 616bb898558SAl Viro * CPUID functions returning a single datum 617bb898558SAl Viro */ 618bb898558SAl Viro static inline unsigned int cpuid_eax(unsigned int op) 619bb898558SAl Viro { 620bb898558SAl Viro unsigned int eax, ebx, ecx, edx; 621bb898558SAl Viro 622bb898558SAl Viro cpuid(op, &eax, &ebx, &ecx, &edx); 623bb898558SAl Viro 624bb898558SAl Viro return eax; 625bb898558SAl Viro } 626bb898558SAl Viro 627bb898558SAl Viro static inline unsigned int cpuid_ebx(unsigned int op) 628bb898558SAl Viro { 629bb898558SAl Viro unsigned int eax, ebx, ecx, edx; 630bb898558SAl Viro 631bb898558SAl Viro cpuid(op, &eax, &ebx, &ecx, &edx); 632bb898558SAl Viro 633bb898558SAl Viro return ebx; 634bb898558SAl Viro } 635bb898558SAl Viro 636bb898558SAl Viro static inline unsigned int cpuid_ecx(unsigned int op) 637bb898558SAl Viro { 638bb898558SAl Viro unsigned int eax, ebx, ecx, edx; 639bb898558SAl Viro 640bb898558SAl Viro cpuid(op, &eax, &ebx, &ecx, &edx); 641bb898558SAl Viro 642bb898558SAl Viro return ecx; 643bb898558SAl Viro } 644bb898558SAl Viro 645bb898558SAl Viro static inline unsigned int cpuid_edx(unsigned int op) 646bb898558SAl Viro { 647bb898558SAl Viro unsigned int eax, ebx, ecx, edx; 648bb898558SAl Viro 649bb898558SAl Viro cpuid(op, &eax, &ebx, &ecx, &edx); 650bb898558SAl Viro 651bb898558SAl Viro return edx; 652bb898558SAl Viro } 653bb898558SAl Viro 654bb898558SAl Viro /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */ 6550b101e62SDenys Vlasenko static __always_inline void rep_nop(void) 656bb898558SAl Viro { 657bb898558SAl Viro asm volatile("rep; nop" ::: "memory"); 658bb898558SAl Viro } 659bb898558SAl Viro 6600b101e62SDenys Vlasenko static __always_inline void cpu_relax(void) 661bb898558SAl Viro { 662bb898558SAl Viro rep_nop(); 663bb898558SAl Viro } 664bb898558SAl Viro 665c198b121SAndy Lutomirski /* 666c198b121SAndy Lutomirski * This function forces the icache and prefetched instruction stream to 667c198b121SAndy Lutomirski * catch up with reality in two very specific cases: 668c198b121SAndy Lutomirski * 669c198b121SAndy Lutomirski * a) Text was modified using one virtual address and is about to be executed 670c198b121SAndy Lutomirski * from the same physical page at a different virtual address. 671c198b121SAndy Lutomirski * 672c198b121SAndy Lutomirski * b) Text was modified on a different CPU, may subsequently be 673c198b121SAndy Lutomirski * executed on this CPU, and you want to make sure the new version 674c198b121SAndy Lutomirski * gets executed. This generally means you're calling this in a IPI. 675c198b121SAndy Lutomirski * 676c198b121SAndy Lutomirski * If you're calling this for a different reason, you're probably doing 677c198b121SAndy Lutomirski * it wrong. 678c198b121SAndy Lutomirski */ 679bb898558SAl Viro static inline void sync_core(void) 680bb898558SAl Viro { 681c198b121SAndy Lutomirski /* 682c198b121SAndy Lutomirski * There are quite a few ways to do this. IRET-to-self is nice 683c198b121SAndy Lutomirski * because it works on every CPU, at any CPL (so it's compatible 684c198b121SAndy Lutomirski * with paravirtualization), and it never exits to a hypervisor. 685c198b121SAndy Lutomirski * The only down sides are that it's a bit slow (it seems to be 686c198b121SAndy Lutomirski * a bit more than 2x slower than the fastest options) and that 687c198b121SAndy Lutomirski * it unmasks NMIs. The "push %cs" is needed because, in 688c198b121SAndy Lutomirski * paravirtual environments, __KERNEL_CS may not be a valid CS 689c198b121SAndy Lutomirski * value when we do IRET directly. 690c198b121SAndy Lutomirski * 691c198b121SAndy Lutomirski * In case NMI unmasking or performance ever becomes a problem, 692c198b121SAndy Lutomirski * the next best option appears to be MOV-to-CR2 and an 693c198b121SAndy Lutomirski * unconditional jump. That sequence also works on all CPUs, 694ecda85e7SJuergen Gross * but it will fault at CPL3 (i.e. Xen PV). 695c198b121SAndy Lutomirski * 696c198b121SAndy Lutomirski * CPUID is the conventional way, but it's nasty: it doesn't 697c198b121SAndy Lutomirski * exist on some 486-like CPUs, and it usually exits to a 698c198b121SAndy Lutomirski * hypervisor. 699c198b121SAndy Lutomirski * 700c198b121SAndy Lutomirski * Like all of Linux's memory ordering operations, this is a 701c198b121SAndy Lutomirski * compiler barrier as well. 702c198b121SAndy Lutomirski */ 7031c52d859SAndy Lutomirski #ifdef CONFIG_X86_32 704c198b121SAndy Lutomirski asm volatile ( 705c198b121SAndy Lutomirski "pushfl\n\t" 706c198b121SAndy Lutomirski "pushl %%cs\n\t" 707c198b121SAndy Lutomirski "pushl $1f\n\t" 708c198b121SAndy Lutomirski "iret\n\t" 70945c39fb0SH. Peter Anvin "1:" 710f5caf621SJosh Poimboeuf : ASM_CALL_CONSTRAINT : : "memory"); 71145c39fb0SH. Peter Anvin #else 712c198b121SAndy Lutomirski unsigned int tmp; 713c198b121SAndy Lutomirski 714c198b121SAndy Lutomirski asm volatile ( 71576846bf3SJosh Poimboeuf UNWIND_HINT_SAVE 716c198b121SAndy Lutomirski "mov %%ss, %0\n\t" 717c198b121SAndy Lutomirski "pushq %q0\n\t" 718c198b121SAndy Lutomirski "pushq %%rsp\n\t" 719c198b121SAndy Lutomirski "addq $8, (%%rsp)\n\t" 720c198b121SAndy Lutomirski "pushfq\n\t" 721c198b121SAndy Lutomirski "mov %%cs, %0\n\t" 722c198b121SAndy Lutomirski "pushq %q0\n\t" 723c198b121SAndy Lutomirski "pushq $1f\n\t" 724c198b121SAndy Lutomirski "iretq\n\t" 72576846bf3SJosh Poimboeuf UNWIND_HINT_RESTORE 726c198b121SAndy Lutomirski "1:" 727f5caf621SJosh Poimboeuf : "=&r" (tmp), ASM_CALL_CONSTRAINT : : "cc", "memory"); 72845c39fb0SH. Peter Anvin #endif 729bb898558SAl Viro } 730bb898558SAl Viro 731bb898558SAl Viro extern void select_idle_routine(const struct cpuinfo_x86 *c); 73207c94a38SBorislav Petkov extern void amd_e400_c1e_apic_setup(void); 733bb898558SAl Viro 734bb898558SAl Viro extern unsigned long boot_option_idle_override; 735bb898558SAl Viro 736d1896049SThomas Renninger enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_NOMWAIT, 73769fb3676SLen Brown IDLE_POLL}; 738d1896049SThomas Renninger 739bb898558SAl Viro extern void enable_sep_cpu(void); 740bb898558SAl Viro extern int sysenter_setup(void); 741bb898558SAl Viro 74229c84391SJan Kiszka extern void early_trap_init(void); 7438170e6beSH. Peter Anvin void early_trap_pf_init(void); 74429c84391SJan Kiszka 745bb898558SAl Viro /* Defined in head.S */ 746bb898558SAl Viro extern struct desc_ptr early_gdt_descr; 747bb898558SAl Viro 748bb898558SAl Viro extern void cpu_set_gdt(int); 749552be871SBrian Gerst extern void switch_to_new_gdt(int); 75045fc8757SThomas Garnier extern void load_direct_gdt(int); 75169218e47SThomas Garnier extern void load_fixmap_gdt(int); 75211e3a840SJeremy Fitzhardinge extern void load_percpu_segment(int); 753bb898558SAl Viro extern void cpu_init(void); 754bb898558SAl Viro 755c2724775SMarkus Metzger static inline unsigned long get_debugctlmsr(void) 756c2724775SMarkus Metzger { 757c2724775SMarkus Metzger unsigned long debugctlmsr = 0; 758c2724775SMarkus Metzger 759c2724775SMarkus Metzger #ifndef CONFIG_X86_DEBUGCTLMSR 760c2724775SMarkus Metzger if (boot_cpu_data.x86 < 6) 761c2724775SMarkus Metzger return 0; 762c2724775SMarkus Metzger #endif 763c2724775SMarkus Metzger rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr); 764c2724775SMarkus Metzger 765c2724775SMarkus Metzger return debugctlmsr; 766c2724775SMarkus Metzger } 767c2724775SMarkus Metzger 768bb898558SAl Viro static inline void update_debugctlmsr(unsigned long debugctlmsr) 769bb898558SAl Viro { 770bb898558SAl Viro #ifndef CONFIG_X86_DEBUGCTLMSR 771bb898558SAl Viro if (boot_cpu_data.x86 < 6) 772bb898558SAl Viro return; 773bb898558SAl Viro #endif 774bb898558SAl Viro wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr); 775bb898558SAl Viro } 776bb898558SAl Viro 7779bd1190aSOleg Nesterov extern void set_task_blockstep(struct task_struct *task, bool on); 7789bd1190aSOleg Nesterov 779bb898558SAl Viro /* Boot loader type from the setup header: */ 780bb898558SAl Viro extern int bootloader_type; 7815031296cSH. Peter Anvin extern int bootloader_version; 782bb898558SAl Viro 783bb898558SAl Viro extern char ignore_fpu_irq; 784bb898558SAl Viro 785bb898558SAl Viro #define HAVE_ARCH_PICK_MMAP_LAYOUT 1 786bb898558SAl Viro #define ARCH_HAS_PREFETCHW 787bb898558SAl Viro #define ARCH_HAS_SPINLOCK_PREFETCH 788bb898558SAl Viro 789bb898558SAl Viro #ifdef CONFIG_X86_32 790a930dc45SBorislav Petkov # define BASE_PREFETCH "" 791bb898558SAl Viro # define ARCH_HAS_PREFETCH 792bb898558SAl Viro #else 793a930dc45SBorislav Petkov # define BASE_PREFETCH "prefetcht0 %P1" 794bb898558SAl Viro #endif 795bb898558SAl Viro 796bb898558SAl Viro /* 797bb898558SAl Viro * Prefetch instructions for Pentium III (+) and AMD Athlon (+) 798bb898558SAl Viro * 799bb898558SAl Viro * It's not worth to care about 3dnow prefetches for the K6 800bb898558SAl Viro * because they are microcoded there and very slow. 801bb898558SAl Viro */ 802bb898558SAl Viro static inline void prefetch(const void *x) 803bb898558SAl Viro { 804a930dc45SBorislav Petkov alternative_input(BASE_PREFETCH, "prefetchnta %P1", 805bb898558SAl Viro X86_FEATURE_XMM, 806a930dc45SBorislav Petkov "m" (*(const char *)x)); 807bb898558SAl Viro } 808bb898558SAl Viro 809bb898558SAl Viro /* 810bb898558SAl Viro * 3dnow prefetch to get an exclusive cache line. 811bb898558SAl Viro * Useful for spinlocks to avoid one state transition in the 812bb898558SAl Viro * cache coherency protocol: 813bb898558SAl Viro */ 814bb898558SAl Viro static inline void prefetchw(const void *x) 815bb898558SAl Viro { 816a930dc45SBorislav Petkov alternative_input(BASE_PREFETCH, "prefetchw %P1", 817a930dc45SBorislav Petkov X86_FEATURE_3DNOWPREFETCH, 818a930dc45SBorislav Petkov "m" (*(const char *)x)); 819bb898558SAl Viro } 820bb898558SAl Viro 821bb898558SAl Viro static inline void spin_lock_prefetch(const void *x) 822bb898558SAl Viro { 823bb898558SAl Viro prefetchw(x); 824bb898558SAl Viro } 825bb898558SAl Viro 826d9e05cc5SAndy Lutomirski #define TOP_OF_INIT_STACK ((unsigned long)&init_stack + sizeof(init_stack) - \ 827d9e05cc5SAndy Lutomirski TOP_OF_KERNEL_STACK_PADDING) 828d9e05cc5SAndy Lutomirski 8293500130bSAndy Lutomirski #define task_top_of_stack(task) ((unsigned long)(task_pt_regs(task) + 1)) 8303500130bSAndy Lutomirski 831d375cf15SAndy Lutomirski #define task_pt_regs(task) \ 832d375cf15SAndy Lutomirski ({ \ 833d375cf15SAndy Lutomirski unsigned long __ptr = (unsigned long)task_stack_page(task); \ 834d375cf15SAndy Lutomirski __ptr += THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING; \ 835d375cf15SAndy Lutomirski ((struct pt_regs *)__ptr) - 1; \ 836d375cf15SAndy Lutomirski }) 837d375cf15SAndy Lutomirski 838bb898558SAl Viro #ifdef CONFIG_X86_32 839bb898558SAl Viro /* 840bb898558SAl Viro * User space process size: 3GB (default). 841bb898558SAl Viro */ 8428f3e474fSDmitry Safonov #define IA32_PAGE_OFFSET PAGE_OFFSET 843bb898558SAl Viro #define TASK_SIZE PAGE_OFFSET 844b569bab7SKirill A. Shutemov #define TASK_SIZE_LOW TASK_SIZE 845d9517346SIngo Molnar #define TASK_SIZE_MAX TASK_SIZE 84644b04912SKirill A. Shutemov #define DEFAULT_MAP_WINDOW TASK_SIZE 847bb898558SAl Viro #define STACK_TOP TASK_SIZE 848bb898558SAl Viro #define STACK_TOP_MAX STACK_TOP 849bb898558SAl Viro 850bb898558SAl Viro #define INIT_THREAD { \ 851d9e05cc5SAndy Lutomirski .sp0 = TOP_OF_INIT_STACK, \ 852bb898558SAl Viro .sysenter_cs = __KERNEL_CS, \ 853bb898558SAl Viro .io_bitmap_ptr = NULL, \ 85413d4ea09SAndy Lutomirski .addr_limit = KERNEL_DS, \ 855bb898558SAl Viro } 856bb898558SAl Viro 857bb898558SAl Viro #define KSTK_ESP(task) (task_pt_regs(task)->sp) 858bb898558SAl Viro 859bb898558SAl Viro #else 860bb898558SAl Viro /* 861f55f0501SAndy Lutomirski * User space process size. This is the first address outside the user range. 862f55f0501SAndy Lutomirski * There are a few constraints that determine this: 863f55f0501SAndy Lutomirski * 864f55f0501SAndy Lutomirski * On Intel CPUs, if a SYSCALL instruction is at the highest canonical 865f55f0501SAndy Lutomirski * address, then that syscall will enter the kernel with a 866f55f0501SAndy Lutomirski * non-canonical return address, and SYSRET will explode dangerously. 867f55f0501SAndy Lutomirski * We avoid this particular problem by preventing anything executable 868f55f0501SAndy Lutomirski * from being mapped at the maximum canonical address. 869f55f0501SAndy Lutomirski * 870f55f0501SAndy Lutomirski * On AMD CPUs in the Ryzen family, there's a nasty bug in which the 871f55f0501SAndy Lutomirski * CPUs malfunction if they execute code from the highest canonical page. 872f55f0501SAndy Lutomirski * They'll speculate right off the end of the canonical space, and 873f55f0501SAndy Lutomirski * bad things happen. This is worked around in the same way as the 874f55f0501SAndy Lutomirski * Intel problem. 875f55f0501SAndy Lutomirski * 876f55f0501SAndy Lutomirski * With page table isolation enabled, we map the LDT in ... [stay tuned] 877bb898558SAl Viro */ 878ee00f4a3SKirill A. Shutemov #define TASK_SIZE_MAX ((1UL << __VIRTUAL_MASK_SHIFT) - PAGE_SIZE) 879bb898558SAl Viro 880ee00f4a3SKirill A. Shutemov #define DEFAULT_MAP_WINDOW ((1UL << 47) - PAGE_SIZE) 881bb898558SAl Viro 882bb898558SAl Viro /* This decides where the kernel will search for a free chunk of vm 883bb898558SAl Viro * space during mmap's. 884bb898558SAl Viro */ 885bb898558SAl Viro #define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? \ 886bb898558SAl Viro 0xc0000000 : 0xFFFFe000) 887bb898558SAl Viro 888b569bab7SKirill A. Shutemov #define TASK_SIZE_LOW (test_thread_flag(TIF_ADDR32) ? \ 889b569bab7SKirill A. Shutemov IA32_PAGE_OFFSET : DEFAULT_MAP_WINDOW) 8906bd33008SH. Peter Anvin #define TASK_SIZE (test_thread_flag(TIF_ADDR32) ? \ 891d9517346SIngo Molnar IA32_PAGE_OFFSET : TASK_SIZE_MAX) 8926bd33008SH. Peter Anvin #define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_ADDR32)) ? \ 893d9517346SIngo Molnar IA32_PAGE_OFFSET : TASK_SIZE_MAX) 894bb898558SAl Viro 895b569bab7SKirill A. Shutemov #define STACK_TOP TASK_SIZE_LOW 896d9517346SIngo Molnar #define STACK_TOP_MAX TASK_SIZE_MAX 897bb898558SAl Viro 898bb898558SAl Viro #define INIT_THREAD { \ 89913d4ea09SAndy Lutomirski .addr_limit = KERNEL_DS, \ 900bb898558SAl Viro } 901bb898558SAl Viro 90289240ba0SStefani Seibold extern unsigned long KSTK_ESP(struct task_struct *task); 903d046ff8bSH. J. Lu 904bb898558SAl Viro #endif /* CONFIG_X86_64 */ 905bb898558SAl Viro 906bb898558SAl Viro extern void start_thread(struct pt_regs *regs, unsigned long new_ip, 907bb898558SAl Viro unsigned long new_sp); 908bb898558SAl Viro 909bb898558SAl Viro /* 910bb898558SAl Viro * This decides where the kernel will search for a free chunk of vm 911bb898558SAl Viro * space during mmap's. 912bb898558SAl Viro */ 9138f3e474fSDmitry Safonov #define __TASK_UNMAPPED_BASE(task_size) (PAGE_ALIGN(task_size / 3)) 914b569bab7SKirill A. Shutemov #define TASK_UNMAPPED_BASE __TASK_UNMAPPED_BASE(TASK_SIZE_LOW) 915bb898558SAl Viro 916bb898558SAl Viro #define KSTK_EIP(task) (task_pt_regs(task)->ip) 917bb898558SAl Viro 918bb898558SAl Viro /* Get/set a process' ability to use the timestamp counter instruction */ 919bb898558SAl Viro #define GET_TSC_CTL(adr) get_tsc_mode((adr)) 920bb898558SAl Viro #define SET_TSC_CTL(val) set_tsc_mode((val)) 921bb898558SAl Viro 922bb898558SAl Viro extern int get_tsc_mode(unsigned long adr); 923bb898558SAl Viro extern int set_tsc_mode(unsigned int val); 924bb898558SAl Viro 925e9ea1e7fSKyle Huey DECLARE_PER_CPU(u64, msr_misc_features_shadow); 926e9ea1e7fSKyle Huey 927fe3d197fSDave Hansen /* Register/unregister a process' MPX related resource */ 92846a6e0cfSDave Hansen #define MPX_ENABLE_MANAGEMENT() mpx_enable_management() 92946a6e0cfSDave Hansen #define MPX_DISABLE_MANAGEMENT() mpx_disable_management() 930fe3d197fSDave Hansen 931fe3d197fSDave Hansen #ifdef CONFIG_X86_INTEL_MPX 93246a6e0cfSDave Hansen extern int mpx_enable_management(void); 93346a6e0cfSDave Hansen extern int mpx_disable_management(void); 934fe3d197fSDave Hansen #else 93546a6e0cfSDave Hansen static inline int mpx_enable_management(void) 936fe3d197fSDave Hansen { 937fe3d197fSDave Hansen return -EINVAL; 938fe3d197fSDave Hansen } 93946a6e0cfSDave Hansen static inline int mpx_disable_management(void) 940fe3d197fSDave Hansen { 941fe3d197fSDave Hansen return -EINVAL; 942fe3d197fSDave Hansen } 943fe3d197fSDave Hansen #endif /* CONFIG_X86_INTEL_MPX */ 944fe3d197fSDave Hansen 945bc8e80d5SBorislav Petkov #ifdef CONFIG_CPU_SUP_AMD 9468b84c8dfSDaniel J Blueman extern u16 amd_get_nb_id(int cpu); 947cc2749e4SAravind Gopalakrishnan extern u32 amd_get_nodes_per_socket(void); 948bc8e80d5SBorislav Petkov #else 949bc8e80d5SBorislav Petkov static inline u16 amd_get_nb_id(int cpu) { return 0; } 950bc8e80d5SBorislav Petkov static inline u32 amd_get_nodes_per_socket(void) { return 0; } 951bc8e80d5SBorislav Petkov #endif 9526a812691SAndreas Herrmann 95396e39ac0SJason Wang static inline uint32_t hypervisor_cpuid_base(const char *sig, uint32_t leaves) 95496e39ac0SJason Wang { 95596e39ac0SJason Wang uint32_t base, eax, signature[3]; 95696e39ac0SJason Wang 95796e39ac0SJason Wang for (base = 0x40000000; base < 0x40010000; base += 0x100) { 95896e39ac0SJason Wang cpuid(base, &eax, &signature[0], &signature[1], &signature[2]); 95996e39ac0SJason Wang 96096e39ac0SJason Wang if (!memcmp(sig, signature, 12) && 96196e39ac0SJason Wang (leaves == 0 || ((eax - base) >= leaves))) 96296e39ac0SJason Wang return base; 96396e39ac0SJason Wang } 96496e39ac0SJason Wang 96596e39ac0SJason Wang return 0; 96696e39ac0SJason Wang } 96796e39ac0SJason Wang 968f05e798aSDavid Howells extern unsigned long arch_align_stack(unsigned long sp); 969f05e798aSDavid Howells extern void free_init_pages(char *what, unsigned long begin, unsigned long end); 970f05e798aSDavid Howells 971f05e798aSDavid Howells void default_idle(void); 9726a377ddcSLen Brown #ifdef CONFIG_XEN 9736a377ddcSLen Brown bool xen_set_default_idle(void); 9746a377ddcSLen Brown #else 9756a377ddcSLen Brown #define xen_set_default_idle 0 9766a377ddcSLen Brown #endif 977f05e798aSDavid Howells 978f05e798aSDavid Howells void stop_this_cpu(void *dummy); 9794d067d8eSBorislav Petkov void df_debug(struct pt_regs *regs, long error_code); 980*1008c52cSBorislav Petkov void microcode_check(void); 9811965aae3SH. Peter Anvin #endif /* _ASM_X86_PROCESSOR_H */ 982