1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 21965aae3SH. Peter Anvin #ifndef _ASM_X86_PROCESSOR_H 31965aae3SH. Peter Anvin #define _ASM_X86_PROCESSOR_H 4bb898558SAl Viro 5bb898558SAl Viro #include <asm/processor-flags.h> 6bb898558SAl Viro 7bb898558SAl Viro /* Forward declaration, a strange C thing */ 8bb898558SAl Viro struct task_struct; 9bb898558SAl Viro struct mm_struct; 10577d5cd7SThomas Gleixner struct io_bitmap; 119fda6a06SBrian Gerst struct vm86; 12bb898558SAl Viro 13bb898558SAl Viro #include <asm/math_emu.h> 14bb898558SAl Viro #include <asm/segment.h> 15bb898558SAl Viro #include <asm/types.h> 16decb4c41SIngo Molnar #include <uapi/asm/sigcontext.h> 17bb898558SAl Viro #include <asm/current.h> 18cd4d09ecSBorislav Petkov #include <asm/cpufeatures.h> 19d8001690SBorislav Petkov #include <asm/cpuid.h> 20bb898558SAl Viro #include <asm/page.h> 2154321d94SJeremy Fitzhardinge #include <asm/pgtable_types.h> 22bb898558SAl Viro #include <asm/percpu.h> 23bb898558SAl Viro #include <asm/desc_defs.h> 24bb898558SAl Viro #include <asm/nops.h> 25f05e798aSDavid Howells #include <asm/special_insns.h> 2614b9675aSIngo Molnar #include <asm/fpu/types.h> 2776846bf3SJosh Poimboeuf #include <asm/unwind_hints.h> 2815934878SSean Christopherson #include <asm/vmxfeatures.h> 29abc22418SVincenzo Frascino #include <asm/vdso/processor.h> 3098cfa463SRick Edgecombe #include <asm/shstk.h> 31bb898558SAl Viro 32bb898558SAl Viro #include <linux/personality.h> 33bb898558SAl Viro #include <linux/cache.h> 34bb898558SAl Viro #include <linux/threads.h> 355cbc19a9SPeter Zijlstra #include <linux/math64.h> 36faa4602eSPeter Zijlstra #include <linux/err.h> 37f05e798aSDavid Howells #include <linux/irqflags.h> 3821729f81STom Lendacky #include <linux/mem_encrypt.h> 39f05e798aSDavid Howells 40f05e798aSDavid Howells /* 41f05e798aSDavid Howells * We handle most unaligned accesses in hardware. On the other hand 42f05e798aSDavid Howells * unaligned DMA can be quite expensive on some Nehalem processors. 43f05e798aSDavid Howells * 44f05e798aSDavid Howells * Based on this we disable the IP header alignment in network drivers. 45f05e798aSDavid Howells */ 46f05e798aSDavid Howells #define NET_IP_ALIGN 0 47bb898558SAl Viro 48b332828cSK.Prasad #define HBP_NUM 4 49bb898558SAl Viro 50b8c1b8eaSIngo Molnar /* 51b8c1b8eaSIngo Molnar * These alignment constraints are for performance in the vSMP case, 52b8c1b8eaSIngo Molnar * but in the task_struct case we must also meet hardware imposed 53b8c1b8eaSIngo Molnar * alignment requirements of the FPU state: 54b8c1b8eaSIngo Molnar */ 55bb898558SAl Viro #ifdef CONFIG_X86_VSMP 56bb898558SAl Viro # define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT) 57bb898558SAl Viro # define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT) 58bb898558SAl Viro #else 59b8c1b8eaSIngo Molnar # define ARCH_MIN_TASKALIGN __alignof__(union fpregs_state) 60bb898558SAl Viro # define ARCH_MIN_MMSTRUCT_ALIGN 0 61bb898558SAl Viro #endif 62bb898558SAl Viro 63e0ba94f1SAlex Shi enum tlb_infos { 64e0ba94f1SAlex Shi ENTRIES, 65e0ba94f1SAlex Shi NR_INFO 66e0ba94f1SAlex Shi }; 67e0ba94f1SAlex Shi 68e0ba94f1SAlex Shi extern u16 __read_mostly tlb_lli_4k[NR_INFO]; 69e0ba94f1SAlex Shi extern u16 __read_mostly tlb_lli_2m[NR_INFO]; 70e0ba94f1SAlex Shi extern u16 __read_mostly tlb_lli_4m[NR_INFO]; 71e0ba94f1SAlex Shi extern u16 __read_mostly tlb_lld_4k[NR_INFO]; 72e0ba94f1SAlex Shi extern u16 __read_mostly tlb_lld_2m[NR_INFO]; 73e0ba94f1SAlex Shi extern u16 __read_mostly tlb_lld_4m[NR_INFO]; 74dd360393SKirill A. Shutemov extern u16 __read_mostly tlb_lld_1g[NR_INFO]; 75c4211f42SAlex Shi 76bb898558SAl Viro /* 77bb898558SAl Viro * CPU type and hardware bug flags. Kept separately for each CPU. 78bb898558SAl Viro */ 79bb898558SAl Viro 80b9655e70SThomas Gleixner struct cpuinfo_topology { 81b9655e70SThomas Gleixner // Real APIC ID read from the local APIC 82b9655e70SThomas Gleixner u32 apicid; 83b9655e70SThomas Gleixner // The initial APIC ID provided by CPUID 84b9655e70SThomas Gleixner u32 initial_apicid; 8502fb601dSThomas Gleixner 8602fb601dSThomas Gleixner // Physical package ID 8702fb601dSThomas Gleixner u32 pkg_id; 888a169ed4SThomas Gleixner 898a169ed4SThomas Gleixner // Physical die ID on AMD, Relative on Intel 908a169ed4SThomas Gleixner u32 die_id; 91e9525633SThomas Gleixner 92e3c0c5d5SThomas Gleixner // Compute unit ID - AMD specific 93e3c0c5d5SThomas Gleixner u32 cu_id; 94e3c0c5d5SThomas Gleixner 95e9525633SThomas Gleixner // Core ID relative to the package 96e9525633SThomas Gleixner u32 core_id; 9722dc9631SThomas Gleixner 9822dc9631SThomas Gleixner // Logical ID mappings 9922dc9631SThomas Gleixner u32 logical_pkg_id; 10022dc9631SThomas Gleixner u32 logical_die_id; 1016e290323SThomas Gleixner 1027e3ec628SThomas Gleixner // AMD Node ID and Nodes per Package info 1037e3ec628SThomas Gleixner u32 amd_node_id; 1047e3ec628SThomas Gleixner 1056e290323SThomas Gleixner // Cache level topology IDs 1066e290323SThomas Gleixner u32 llc_id; 1076e290323SThomas Gleixner u32 l2c_id; 108b9655e70SThomas Gleixner }; 109b9655e70SThomas Gleixner 110bb898558SAl Viro struct cpuinfo_x86 { 111a9d0adceSTony Luck union { 112a9d0adceSTony Luck /* 113a9d0adceSTony Luck * The particular ordering (low-to-high) of (vendor, 114a9d0adceSTony Luck * family, model) is done in case range of models, like 115a9d0adceSTony Luck * it is usually done on AMD, need to be compared. 116a9d0adceSTony Luck */ 117a9d0adceSTony Luck struct { 118bb898558SAl Viro __u8 x86_model; 119a9d0adceSTony Luck /* CPU family */ 120a9d0adceSTony Luck __u8 x86; 121a9d0adceSTony Luck /* CPU vendor */ 122a9d0adceSTony Luck __u8 x86_vendor; 123a9d0adceSTony Luck __u8 x86_reserved; 124a9d0adceSTony Luck }; 125a9d0adceSTony Luck /* combined vendor, family, model */ 126a9d0adceSTony Luck __u32 x86_vfm; 127a9d0adceSTony Luck }; 128b399151cSJia Zhang __u8 x86_stepping; 1296415813bSMathias Krause #ifdef CONFIG_X86_64 130bb898558SAl Viro /* Number of 4K pages in DTLB/ITLB combined(in pages): */ 131bb898558SAl Viro int x86_tlbsize; 13213c6c532SJan Beulich #endif 133b47ce1feSSean Christopherson #ifdef CONFIG_X86_VMX_FEATURE_NAMES 134b47ce1feSSean Christopherson __u32 vmx_capability[NVMXINTS]; 135b47ce1feSSean Christopherson #endif 136bb898558SAl Viro __u8 x86_virt_bits; 137bb898558SAl Viro __u8 x86_phys_bits; 138bb898558SAl Viro /* Max extended CPUID function supported: */ 139bb898558SAl Viro __u32 extended_cpuid_level; 140bb898558SAl Viro /* Maximum supported CPUID level, -1=no CPUID: */ 141bb898558SAl Viro int cpuid_level; 142db8c33f8SFenghua Yu /* 143db8c33f8SFenghua Yu * Align to size of unsigned long because the x86_capability array 144db8c33f8SFenghua Yu * is passed to bitops which require the alignment. Use unnamed 145db8c33f8SFenghua Yu * union to enforce the array is aligned to size of unsigned long. 146db8c33f8SFenghua Yu */ 147db8c33f8SFenghua Yu union { 14865fc985bSBorislav Petkov __u32 x86_capability[NCAPINTS + NBUGINTS]; 149db8c33f8SFenghua Yu unsigned long x86_capability_alignment; 150db8c33f8SFenghua Yu }; 151bb898558SAl Viro char x86_vendor_id[16]; 152bb898558SAl Viro char x86_model_id[64]; 153b9655e70SThomas Gleixner struct cpuinfo_topology topo; 154bb898558SAl Viro /* in KB - valid for CPUS which support this call: */ 15524dbc600SGustavo A. R. Silva unsigned int x86_cache_size; 156bb898558SAl Viro int x86_cache_alignment; /* In bytes */ 157f3d44f18SReinette Chatre /* Cache QoS architectural values, valid only on the BSP: */ 158cbc82b17SPeter P Waskiewicz Jr int x86_cache_max_rmid; /* max index */ 159cbc82b17SPeter P Waskiewicz Jr int x86_cache_occ_scale; /* scale to bytes */ 160f3d44f18SReinette Chatre int x86_cache_mbm_width_offset; 161bb898558SAl Viro int x86_power; 162bb898558SAl Viro unsigned long loops_per_jiffy; 163822ccfadSTony Luck /* protected processor identification number */ 164822ccfadSTony Luck u64 ppin; 165bb898558SAl Viro u16 x86_clflush_size; 166bb898558SAl Viro /* number of cores as seen by the OS: */ 167bb898558SAl Viro u16 booted_cores; 168bb898558SAl Viro /* Index into per_cpu list: */ 169bb898558SAl Viro u16 cpu_index; 170c52787b5SBalbir Singh /* Is SMT active on this core? */ 171c52787b5SBalbir Singh bool smt_active; 172506ed6b5SAndi Kleen u32 microcode; 173cc51e542SAndi Kleen /* Address space bits used by the cache internally */ 174cc51e542SAndi Kleen u8 x86_cache_bits; 17530bb9811SAndi Kleen unsigned initialized : 1; 1763859a271SKees Cook } __randomize_layout; 177bb898558SAl Viro 178bb898558SAl Viro #define X86_VENDOR_INTEL 0 179bb898558SAl Viro #define X86_VENDOR_CYRIX 1 180bb898558SAl Viro #define X86_VENDOR_AMD 2 181bb898558SAl Viro #define X86_VENDOR_UMC 3 182bb898558SAl Viro #define X86_VENDOR_CENTAUR 5 183bb898558SAl Viro #define X86_VENDOR_TRANSMETA 7 184bb898558SAl Viro #define X86_VENDOR_NSC 8 185c9661c1eSPu Wen #define X86_VENDOR_HYGON 9 186761fdd5eSTony W Wang-oc #define X86_VENDOR_ZHAOXIN 10 187639475d4SMarcos Del Sol Vives #define X86_VENDOR_VORTEX 11 188639475d4SMarcos Del Sol Vives #define X86_VENDOR_NUM 12 189bb898558SAl Viro 190bb898558SAl Viro #define X86_VENDOR_UNKNOWN 0xff 191bb898558SAl Viro 192bb898558SAl Viro /* 193bb898558SAl Viro * capabilities of CPUs 194bb898558SAl Viro */ 195bb898558SAl Viro extern struct cpuinfo_x86 boot_cpu_data; 196bb898558SAl Viro extern struct cpuinfo_x86 new_cpu_data; 197bb898558SAl Viro 1986cbd2171SThomas Gleixner extern __u32 cpu_caps_cleared[NCAPINTS + NBUGINTS]; 1996cbd2171SThomas Gleixner extern __u32 cpu_caps_set[NCAPINTS + NBUGINTS]; 200bb898558SAl Viro 2012c773dd3SJan Beulich DECLARE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info); 202bb898558SAl Viro #define cpu_data(cpu) per_cpu(cpu_info, cpu) 203bb898558SAl Viro 204bb898558SAl Viro extern const struct seq_operations cpuinfo_op; 205bb898558SAl Viro 206bb898558SAl Viro #define cache_line_size() (boot_cpu_data.x86_cache_alignment) 207bb898558SAl Viro 208bb898558SAl Viro extern void cpu_detect(struct cpuinfo_x86 *c); 209bb898558SAl Viro 2109df95169SVlastimil Babka static inline unsigned long long l1tf_pfn_limit(void) 21117dbca11SAndi Kleen { 212cc51e542SAndi Kleen return BIT_ULL(boot_cpu_data.x86_cache_bits - 1 - PAGE_SHIFT); 21317dbca11SAndi Kleen } 21417dbca11SAndi Kleen 215bb898558SAl Viro extern void early_cpu_init(void); 216bb898558SAl Viro extern void identify_secondary_cpu(struct cpuinfo_x86 *); 217bb898558SAl Viro extern void print_cpu_info(struct cpuinfo_x86 *); 21821c3fcf3SYinghai Lu void print_cpu_msr(struct cpuinfo_x86 *); 219bb898558SAl Viro 2206c690ee1SAndy Lutomirski /* 2216c690ee1SAndy Lutomirski * Friendlier CR3 helpers. 2226c690ee1SAndy Lutomirski */ 2236c690ee1SAndy Lutomirski static inline unsigned long read_cr3_pa(void) 2246c690ee1SAndy Lutomirski { 2256c690ee1SAndy Lutomirski return __read_cr3() & CR3_ADDR_MASK; 2266c690ee1SAndy Lutomirski } 2276c690ee1SAndy Lutomirski 228eef9c4abSTom Lendacky static inline unsigned long native_read_cr3_pa(void) 229eef9c4abSTom Lendacky { 230eef9c4abSTom Lendacky return __native_read_cr3() & CR3_ADDR_MASK; 231eef9c4abSTom Lendacky } 232eef9c4abSTom Lendacky 233bb898558SAl Viro static inline void load_cr3(pgd_t *pgdir) 234bb898558SAl Viro { 23521729f81STom Lendacky write_cr3(__sme_pa(pgdir)); 236bb898558SAl Viro } 237bb898558SAl Viro 2387fb983b4SAndy Lutomirski /* 2397fb983b4SAndy Lutomirski * Note that while the legacy 'TSS' name comes from 'Task State Segment', 2407fb983b4SAndy Lutomirski * on modern x86 CPUs the TSS also holds information important to 64-bit mode, 2417fb983b4SAndy Lutomirski * unrelated to the task-switch mechanism: 2427fb983b4SAndy Lutomirski */ 243bb898558SAl Viro #ifdef CONFIG_X86_32 244bb898558SAl Viro /* This is the TSS defined by the hardware. */ 245bb898558SAl Viro struct x86_hw_tss { 246bb898558SAl Viro unsigned short back_link, __blh; 247bb898558SAl Viro unsigned long sp0; 248bb898558SAl Viro unsigned short ss0, __ss0h; 249cf9328ccSAndy Lutomirski unsigned long sp1; 25076e4c490SAndy Lutomirski 25176e4c490SAndy Lutomirski /* 252cf9328ccSAndy Lutomirski * We don't use ring 1, so ss1 is a convenient scratch space in 253cf9328ccSAndy Lutomirski * the same cacheline as sp0. We use ss1 to cache the value in 254cf9328ccSAndy Lutomirski * MSR_IA32_SYSENTER_CS. When we context switch 255cf9328ccSAndy Lutomirski * MSR_IA32_SYSENTER_CS, we first check if the new value being 256cf9328ccSAndy Lutomirski * written matches ss1, and, if it's not, then we wrmsr the new 257cf9328ccSAndy Lutomirski * value and update ss1. 25876e4c490SAndy Lutomirski * 259cf9328ccSAndy Lutomirski * The only reason we context switch MSR_IA32_SYSENTER_CS is 260cf9328ccSAndy Lutomirski * that we set it to zero in vm86 tasks to avoid corrupting the 261cf9328ccSAndy Lutomirski * stack if we were to go through the sysenter path from vm86 262cf9328ccSAndy Lutomirski * mode. 26376e4c490SAndy Lutomirski */ 26476e4c490SAndy Lutomirski unsigned short ss1; /* MSR_IA32_SYSENTER_CS */ 26576e4c490SAndy Lutomirski 26676e4c490SAndy Lutomirski unsigned short __ss1h; 267bb898558SAl Viro unsigned long sp2; 268bb898558SAl Viro unsigned short ss2, __ss2h; 269bb898558SAl Viro unsigned long __cr3; 270bb898558SAl Viro unsigned long ip; 271bb898558SAl Viro unsigned long flags; 272bb898558SAl Viro unsigned long ax; 273bb898558SAl Viro unsigned long cx; 274bb898558SAl Viro unsigned long dx; 275bb898558SAl Viro unsigned long bx; 276bb898558SAl Viro unsigned long sp; 277bb898558SAl Viro unsigned long bp; 278bb898558SAl Viro unsigned long si; 279bb898558SAl Viro unsigned long di; 280bb898558SAl Viro unsigned short es, __esh; 281bb898558SAl Viro unsigned short cs, __csh; 282bb898558SAl Viro unsigned short ss, __ssh; 283bb898558SAl Viro unsigned short ds, __dsh; 284bb898558SAl Viro unsigned short fs, __fsh; 285bb898558SAl Viro unsigned short gs, __gsh; 286bb898558SAl Viro unsigned short ldt, __ldth; 287bb898558SAl Viro unsigned short trace; 288bb898558SAl Viro unsigned short io_bitmap_base; 289bb898558SAl Viro 290bb898558SAl Viro } __attribute__((packed)); 291bb898558SAl Viro #else 292bb898558SAl Viro struct x86_hw_tss { 293bb898558SAl Viro u32 reserved1; 294bb898558SAl Viro u64 sp0; 295bb898558SAl Viro u64 sp1; 2969aaefe7bSAndy Lutomirski 29798f05b51SAndy Lutomirski /* 29898f05b51SAndy Lutomirski * Since Linux does not use ring 2, the 'sp2' slot is unused by 29998f05b51SAndy Lutomirski * hardware. entry_SYSCALL_64 uses it as scratch space to stash 30098f05b51SAndy Lutomirski * the user RSP value. 30198f05b51SAndy Lutomirski */ 302bb898558SAl Viro u64 sp2; 30398f05b51SAndy Lutomirski 304bb898558SAl Viro u64 reserved2; 305bb898558SAl Viro u64 ist[7]; 306bb898558SAl Viro u32 reserved3; 307bb898558SAl Viro u32 reserved4; 308bb898558SAl Viro u16 reserved5; 309bb898558SAl Viro u16 io_bitmap_base; 310bb898558SAl Viro 311d3273deaSAndy Lutomirski } __attribute__((packed)); 312bb898558SAl Viro #endif 313bb898558SAl Viro 314bb898558SAl Viro /* 315bb898558SAl Viro * IO-bitmap sizes: 316bb898558SAl Viro */ 317bb898558SAl Viro #define IO_BITMAP_BITS 65536 318f5848e5fSThomas Gleixner #define IO_BITMAP_BYTES (IO_BITMAP_BITS / BITS_PER_BYTE) 319bb898558SAl Viro #define IO_BITMAP_LONGS (IO_BITMAP_BYTES / sizeof(long)) 320ecc7e37dSThomas Gleixner 321c8137aceSThomas Gleixner #define IO_BITMAP_OFFSET_VALID_MAP \ 322f5848e5fSThomas Gleixner (offsetof(struct tss_struct, io_bitmap.bitmap) - \ 323ecc7e37dSThomas Gleixner offsetof(struct tss_struct, x86_tss)) 324ecc7e37dSThomas Gleixner 325c8137aceSThomas Gleixner #define IO_BITMAP_OFFSET_VALID_ALL \ 326c8137aceSThomas Gleixner (offsetof(struct tss_struct, io_bitmap.mapall) - \ 327c8137aceSThomas Gleixner offsetof(struct tss_struct, x86_tss)) 328c8137aceSThomas Gleixner 329111e7b15SThomas Gleixner #ifdef CONFIG_X86_IOPL_IOPERM 330ecc7e37dSThomas Gleixner /* 331c8137aceSThomas Gleixner * sizeof(unsigned long) coming from an extra "long" at the end of the 332c8137aceSThomas Gleixner * iobitmap. The limit is inclusive, i.e. the last valid byte. 333ecc7e37dSThomas Gleixner */ 334ecc7e37dSThomas Gleixner # define __KERNEL_TSS_LIMIT \ 335c8137aceSThomas Gleixner (IO_BITMAP_OFFSET_VALID_ALL + IO_BITMAP_BYTES + \ 336c8137aceSThomas Gleixner sizeof(unsigned long) - 1) 337111e7b15SThomas Gleixner #else 338111e7b15SThomas Gleixner # define __KERNEL_TSS_LIMIT \ 339111e7b15SThomas Gleixner (offsetof(struct tss_struct, x86_tss) + sizeof(struct x86_hw_tss) - 1) 340111e7b15SThomas Gleixner #endif 341ecc7e37dSThomas Gleixner 342ecc7e37dSThomas Gleixner /* Base offset outside of TSS_LIMIT so unpriviledged IO causes #GP */ 343ecc7e37dSThomas Gleixner #define IO_BITMAP_OFFSET_INVALID (__KERNEL_TSS_LIMIT + 1) 344bb898558SAl Viro 3454fe2d8b1SDave Hansen struct entry_stack { 346c7aadc09SPeter Zijlstra char stack[PAGE_SIZE]; 3470f9a4810SAndy Lutomirski }; 3480f9a4810SAndy Lutomirski 3494fe2d8b1SDave Hansen struct entry_stack_page { 3504fe2d8b1SDave Hansen struct entry_stack stack; 351c482feefSAndy Lutomirski } __aligned(PAGE_SIZE); 3521a935bc3SAndy Lutomirski 353f5848e5fSThomas Gleixner /* 354f5848e5fSThomas Gleixner * All IO bitmap related data stored in the TSS: 355f5848e5fSThomas Gleixner */ 356f5848e5fSThomas Gleixner struct x86_io_bitmap { 357060aa16fSThomas Gleixner /* The sequence number of the last active bitmap. */ 358060aa16fSThomas Gleixner u64 prev_sequence; 359060aa16fSThomas Gleixner 360f5848e5fSThomas Gleixner /* 361f5848e5fSThomas Gleixner * Store the dirty size of the last io bitmap offender. The next 362f5848e5fSThomas Gleixner * one will have to do the cleanup as the switch out to a non io 363f5848e5fSThomas Gleixner * bitmap user will just set x86_tss.io_bitmap_base to a value 364f5848e5fSThomas Gleixner * outside of the TSS limit. So for sane tasks there is no need to 365f5848e5fSThomas Gleixner * actually touch the io_bitmap at all. 366f5848e5fSThomas Gleixner */ 367f5848e5fSThomas Gleixner unsigned int prev_max; 368f5848e5fSThomas Gleixner 369f5848e5fSThomas Gleixner /* 370f5848e5fSThomas Gleixner * The extra 1 is there because the CPU will access an 371f5848e5fSThomas Gleixner * additional byte beyond the end of the IO permission 372f5848e5fSThomas Gleixner * bitmap. The extra byte must be all 1 bits, and must 373f5848e5fSThomas Gleixner * be within the limit. 374f5848e5fSThomas Gleixner */ 375f5848e5fSThomas Gleixner unsigned long bitmap[IO_BITMAP_LONGS + 1]; 376c8137aceSThomas Gleixner 377c8137aceSThomas Gleixner /* 378c8137aceSThomas Gleixner * Special I/O bitmap to emulate IOPL(3). All bytes zero, 379c8137aceSThomas Gleixner * except the additional byte at the end. 380c8137aceSThomas Gleixner */ 381c8137aceSThomas Gleixner unsigned long mapall[IO_BITMAP_LONGS + 1]; 382f5848e5fSThomas Gleixner }; 383f5848e5fSThomas Gleixner 384bb898558SAl Viro struct tss_struct { 385bb898558SAl Viro /* 3861a935bc3SAndy Lutomirski * The fixed hardware portion. This must not cross a page boundary 3871a935bc3SAndy Lutomirski * at risk of violating the SDM's advice and potentially triggering 3881a935bc3SAndy Lutomirski * errata. 389bb898558SAl Viro */ 390bb898558SAl Viro struct x86_hw_tss x86_tss; 391bb898558SAl Viro 392f5848e5fSThomas Gleixner struct x86_io_bitmap io_bitmap; 3931a935bc3SAndy Lutomirski } __aligned(PAGE_SIZE); 394bb898558SAl Viro 395c482feefSAndy Lutomirski DECLARE_PER_CPU_PAGE_ALIGNED(struct tss_struct, cpu_tss_rw); 396bb898558SAl Viro 397e6401c13SAndy Lutomirski /* Per CPU interrupt stacks */ 398e6401c13SAndy Lutomirski struct irq_stack { 399e6401c13SAndy Lutomirski char stack[IRQ_STACK_SIZE]; 400e6401c13SAndy Lutomirski } __aligned(IRQ_STACK_SIZE); 401e6401c13SAndy Lutomirski 402bb898558SAl Viro #ifdef CONFIG_X86_64 403e6401c13SAndy Lutomirski struct fixed_percpu_data { 404947e76cdSBrian Gerst /* 405947e76cdSBrian Gerst * GCC hardcodes the stack canary as %gs:40. Since the 406947e76cdSBrian Gerst * irq_stack is the object at %gs:0, we reserve the bottom 407947e76cdSBrian Gerst * 48 bytes of the irq stack for the canary. 4083fb0fdb3SAndy Lutomirski * 4093fb0fdb3SAndy Lutomirski * Once we are willing to require -mstack-protector-guard-symbol= 4103fb0fdb3SAndy Lutomirski * support for x86_64 stackprotector, we can get rid of this. 411947e76cdSBrian Gerst */ 412947e76cdSBrian Gerst char gs_base[40]; 413947e76cdSBrian Gerst unsigned long stack_canary; 414947e76cdSBrian Gerst }; 415947e76cdSBrian Gerst 416e6401c13SAndy Lutomirski DECLARE_PER_CPU_FIRST(struct fixed_percpu_data, fixed_percpu_data) __visible; 417e6401c13SAndy Lutomirski DECLARE_INIT_PER_CPU(fixed_percpu_data); 4182add8e23SBrian Gerst 41935060ed6SVitaly Kuznetsov static inline unsigned long cpu_kernelmode_gs_base(int cpu) 42035060ed6SVitaly Kuznetsov { 421e6401c13SAndy Lutomirski return (unsigned long)per_cpu(fixed_percpu_data.gs_base, cpu); 42235060ed6SVitaly Kuznetsov } 42335060ed6SVitaly Kuznetsov 424f71e1d2fSNikolay Borisov extern asmlinkage void entry_SYSCALL32_ignore(void); 42542b933b5SVitaly Kuznetsov 42642b933b5SVitaly Kuznetsov /* Save actual FS/GS selectors and bases to current->thread */ 4276758034eSThomas Gleixner void current_save_fsgs(void); 42860a5317fSTejun Heo #else /* X86_64 */ 429050e9baaSLinus Torvalds #ifdef CONFIG_STACKPROTECTOR 4303fb0fdb3SAndy Lutomirski DECLARE_PER_CPU(unsigned long, __stack_chk_guard); 431bb898558SAl Viro #endif 432951c2a51SThomas Gleixner #endif /* !X86_64 */ 433bb898558SAl Viro 43424f1e32cSFrederic Weisbecker struct perf_event; 43524f1e32cSFrederic Weisbecker 436bb898558SAl Viro struct thread_struct { 437bb898558SAl Viro /* Cached TLS descriptors: */ 438bb898558SAl Viro struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES]; 439d375cf15SAndy Lutomirski #ifdef CONFIG_X86_32 440bb898558SAl Viro unsigned long sp0; 441d375cf15SAndy Lutomirski #endif 442bb898558SAl Viro unsigned long sp; 443bb898558SAl Viro #ifdef CONFIG_X86_32 444bb898558SAl Viro unsigned long sysenter_cs; 445bb898558SAl Viro #else 446bb898558SAl Viro unsigned short es; 447bb898558SAl Viro unsigned short ds; 448bb898558SAl Viro unsigned short fsindex; 449bb898558SAl Viro unsigned short gsindex; 450bb898558SAl Viro #endif 451b9d989c7SAndy Lutomirski 452d756f4adSAlexey Dobriyan #ifdef CONFIG_X86_64 453296f781aSAndy Lutomirski unsigned long fsbase; 454296f781aSAndy Lutomirski unsigned long gsbase; 455296f781aSAndy Lutomirski #else 456296f781aSAndy Lutomirski /* 457296f781aSAndy Lutomirski * XXX: this could presumably be unsigned short. Alternatively, 458296f781aSAndy Lutomirski * 32-bit kernels could be taught to use fsindex instead. 459296f781aSAndy Lutomirski */ 460bb898558SAl Viro unsigned long fs; 461bb898558SAl Viro unsigned long gs; 462296f781aSAndy Lutomirski #endif 463c5bedc68SIngo Molnar 46424f1e32cSFrederic Weisbecker /* Save middle states of ptrace breakpoints */ 46524f1e32cSFrederic Weisbecker struct perf_event *ptrace_bps[HBP_NUM]; 46624f1e32cSFrederic Weisbecker /* Debug status used for traps, single steps, etc... */ 467d53d9bc0SPeter Zijlstra unsigned long virtual_dr6; 468326264a0SFrederic Weisbecker /* Keep track of the exact dr7 value set by the user */ 469326264a0SFrederic Weisbecker unsigned long ptrace_dr7; 470bb898558SAl Viro /* Fault info: */ 471bb898558SAl Viro unsigned long cr2; 47251e7dc70SSrikar Dronamraju unsigned long trap_nr; 473bb898558SAl Viro unsigned long error_code; 4749fda6a06SBrian Gerst #ifdef CONFIG_VM86 475bb898558SAl Viro /* Virtual 86 mode info */ 4769fda6a06SBrian Gerst struct vm86 *vm86; 477bb898558SAl Viro #endif 478bb898558SAl Viro /* IO permissions: */ 479577d5cd7SThomas Gleixner struct io_bitmap *io_bitmap; 480c8137aceSThomas Gleixner 481c8137aceSThomas Gleixner /* 482d9f6e12fSIngo Molnar * IOPL. Privilege level dependent I/O permission which is 483a24ca997SThomas Gleixner * emulated via the I/O bitmap to prevent user space from disabling 484a24ca997SThomas Gleixner * interrupts. 485c8137aceSThomas Gleixner */ 486c8137aceSThomas Gleixner unsigned long iopl_emul; 4870c8c0f03SDave Hansen 488b968e84bSPeter Zijlstra unsigned int iopl_warn:1; 489dfa9a942SAndy Lutomirski 4909782a712SDave Hansen /* 4919782a712SDave Hansen * Protection Keys Register for Userspace. Loaded immediately on 4929782a712SDave Hansen * context switch. Store it in thread_struct to avoid a lookup in 4939782a712SDave Hansen * the tasks's FPU xstate buffer. This value is only valid when a 4949782a712SDave Hansen * task is scheduled out. For 'current' the authoritative source of 4959782a712SDave Hansen * PKRU is the hardware itself. 4969782a712SDave Hansen */ 4979782a712SDave Hansen u32 pkru; 4989782a712SDave Hansen 49998cfa463SRick Edgecombe #ifdef CONFIG_X86_USER_SHADOW_STACK 50098cfa463SRick Edgecombe unsigned long features; 50198cfa463SRick Edgecombe unsigned long features_locked; 5022d39a6adSRick Edgecombe 5032d39a6adSRick Edgecombe struct thread_shstk shstk; 50498cfa463SRick Edgecombe #endif 50598cfa463SRick Edgecombe 5060c8c0f03SDave Hansen /* Floating point and extended processor state */ 5070c8c0f03SDave Hansen struct fpu fpu; 5080c8c0f03SDave Hansen /* 5090c8c0f03SDave Hansen * WARNING: 'fpu' is dynamically-sized. It *MUST* be at 5100c8c0f03SDave Hansen * the end. 5110c8c0f03SDave Hansen */ 512bb898558SAl Viro }; 513bb898558SAl Viro 5142dd8eedcSThomas Gleixner extern void fpu_thread_struct_whitelist(unsigned long *offset, unsigned long *size); 5152dd8eedcSThomas Gleixner 516f7d83c1cSKees Cook static inline void arch_thread_struct_whitelist(unsigned long *offset, 517f7d83c1cSKees Cook unsigned long *size) 518f7d83c1cSKees Cook { 5192dd8eedcSThomas Gleixner fpu_thread_struct_whitelist(offset, size); 520f7d83c1cSKees Cook } 521f7d83c1cSKees Cook 522bb898558SAl Viro static inline void 523da51da18SAndy Lutomirski native_load_sp0(unsigned long sp0) 524bb898558SAl Viro { 525c482feefSAndy Lutomirski this_cpu_write(cpu_tss_rw.x86_tss.sp0, sp0); 526bb898558SAl Viro } 527bb898558SAl Viro 52858edfd2eSChang S. Bae static __always_inline void native_swapgs(void) 529bb898558SAl Viro { 530bb898558SAl Viro #ifdef CONFIG_X86_64 531bb898558SAl Viro asm volatile("swapgs" ::: "memory"); 532bb898558SAl Viro #endif 533bb898558SAl Viro } 534bb898558SAl Viro 5351894a403SPeter Zijlstra static __always_inline unsigned long current_top_of_stack(void) 5368ef46a67SAndy Lutomirski { 5379aaefe7bSAndy Lutomirski /* 5389aaefe7bSAndy Lutomirski * We can't read directly from tss.sp0: sp0 on x86_32 is special in 5399aaefe7bSAndy Lutomirski * and around vm86 mode and sp0 on x86_64 is special because of the 5409aaefe7bSAndy Lutomirski * entry trampoline. 5419aaefe7bSAndy Lutomirski */ 542ed2f752eSUros Bizjak if (IS_ENABLED(CONFIG_USE_X86_SEG_SUPPORT)) 5430e370363SUros Bizjak return this_cpu_read_const(const_pcpu_hot.top_of_stack); 544ed2f752eSUros Bizjak 545c063a217SThomas Gleixner return this_cpu_read_stable(pcpu_hot.top_of_stack); 5468ef46a67SAndy Lutomirski } 5478ef46a67SAndy Lutomirski 5481894a403SPeter Zijlstra static __always_inline bool on_thread_stack(void) 5493383642cSAndy Lutomirski { 5503383642cSAndy Lutomirski return (unsigned long)(current_top_of_stack() - 5513383642cSAndy Lutomirski current_stack_pointer) < THREAD_SIZE; 5523383642cSAndy Lutomirski } 5533383642cSAndy Lutomirski 5549bad5658SJuergen Gross #ifdef CONFIG_PARAVIRT_XXL 555bb898558SAl Viro #include <asm/paravirt.h> 556bb898558SAl Viro #else 557bb898558SAl Viro 558da51da18SAndy Lutomirski static inline void load_sp0(unsigned long sp0) 559bb898558SAl Viro { 560da51da18SAndy Lutomirski native_load_sp0(sp0); 561bb898558SAl Viro } 562bb898558SAl Viro 5639bad5658SJuergen Gross #endif /* CONFIG_PARAVIRT_XXL */ 564bb898558SAl Viro 56542a20f86SKees Cook unsigned long __get_wchan(struct task_struct *p); 566bb898558SAl Viro 56735ce6492SThomas Gleixner extern void select_idle_routine(void); 56807c94a38SBorislav Petkov extern void amd_e400_c1e_apic_setup(void); 569bb898558SAl Viro 570bb898558SAl Viro extern unsigned long boot_option_idle_override; 571bb898558SAl Viro 572d1896049SThomas Renninger enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_NOMWAIT, 57369fb3676SLen Brown IDLE_POLL}; 574d1896049SThomas Renninger 575bb898558SAl Viro extern void enable_sep_cpu(void); 576bb898558SAl Viro 57729c84391SJan Kiszka 578bb898558SAl Viro /* Defined in head.S */ 579bb898558SAl Viro extern struct desc_ptr early_gdt_descr; 580bb898558SAl Viro 5811f19e2d5SThomas Gleixner extern void switch_gdt_and_percpu_base(int); 58245fc8757SThomas Garnier extern void load_direct_gdt(int); 58369218e47SThomas Garnier extern void load_fixmap_gdt(int); 584bb898558SAl Viro extern void cpu_init(void); 585520d0308SJoerg Roedel extern void cpu_init_exception_handling(void); 5867652ac92SThomas Gleixner extern void cr4_init(void); 587bb898558SAl Viro 5889bd1190aSOleg Nesterov extern void set_task_blockstep(struct task_struct *task, bool on); 5899bd1190aSOleg Nesterov 590bb898558SAl Viro /* Boot loader type from the setup header: */ 591bb898558SAl Viro extern int bootloader_type; 5925031296cSH. Peter Anvin extern int bootloader_version; 593bb898558SAl Viro 594bb898558SAl Viro extern char ignore_fpu_irq; 595bb898558SAl Viro 596bb898558SAl Viro #define HAVE_ARCH_PICK_MMAP_LAYOUT 1 597bb898558SAl Viro #define ARCH_HAS_PREFETCHW 598bb898558SAl Viro 599bb898558SAl Viro #ifdef CONFIG_X86_32 600a930dc45SBorislav Petkov # define BASE_PREFETCH "" 601bb898558SAl Viro # define ARCH_HAS_PREFETCH 602bb898558SAl Viro #else 603a3ff5316SUros Bizjak # define BASE_PREFETCH "prefetcht0 %1" 604bb898558SAl Viro #endif 605bb898558SAl Viro 606bb898558SAl Viro /* 607bb898558SAl Viro * Prefetch instructions for Pentium III (+) and AMD Athlon (+) 608bb898558SAl Viro * 609bb898558SAl Viro * It's not worth to care about 3dnow prefetches for the K6 610bb898558SAl Viro * because they are microcoded there and very slow. 611bb898558SAl Viro */ 612bb898558SAl Viro static inline void prefetch(const void *x) 613bb898558SAl Viro { 614a3ff5316SUros Bizjak alternative_input(BASE_PREFETCH, "prefetchnta %1", 615bb898558SAl Viro X86_FEATURE_XMM, 616a930dc45SBorislav Petkov "m" (*(const char *)x)); 617bb898558SAl Viro } 618bb898558SAl Viro 619bb898558SAl Viro /* 620bb898558SAl Viro * 3dnow prefetch to get an exclusive cache line. 621bb898558SAl Viro * Useful for spinlocks to avoid one state transition in the 622bb898558SAl Viro * cache coherency protocol: 623bb898558SAl Viro */ 6242823e83aSPeter Zijlstra static __always_inline void prefetchw(const void *x) 625bb898558SAl Viro { 626a3ff5316SUros Bizjak alternative_input(BASE_PREFETCH, "prefetchw %1", 627a930dc45SBorislav Petkov X86_FEATURE_3DNOWPREFETCH, 628a930dc45SBorislav Petkov "m" (*(const char *)x)); 629bb898558SAl Viro } 630bb898558SAl Viro 631d9e05cc5SAndy Lutomirski #define TOP_OF_INIT_STACK ((unsigned long)&init_stack + sizeof(init_stack) - \ 632d9e05cc5SAndy Lutomirski TOP_OF_KERNEL_STACK_PADDING) 633d9e05cc5SAndy Lutomirski 6343500130bSAndy Lutomirski #define task_top_of_stack(task) ((unsigned long)(task_pt_regs(task) + 1)) 6353500130bSAndy Lutomirski 636d375cf15SAndy Lutomirski #define task_pt_regs(task) \ 637d375cf15SAndy Lutomirski ({ \ 638d375cf15SAndy Lutomirski unsigned long __ptr = (unsigned long)task_stack_page(task); \ 639d375cf15SAndy Lutomirski __ptr += THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING; \ 640d375cf15SAndy Lutomirski ((struct pt_regs *)__ptr) - 1; \ 641d375cf15SAndy Lutomirski }) 642d375cf15SAndy Lutomirski 643bb898558SAl Viro #ifdef CONFIG_X86_32 644bb898558SAl Viro #define INIT_THREAD { \ 645d9e05cc5SAndy Lutomirski .sp0 = TOP_OF_INIT_STACK, \ 646bb898558SAl Viro .sysenter_cs = __KERNEL_CS, \ 647bb898558SAl Viro } 648bb898558SAl Viro 649bb898558SAl Viro #define KSTK_ESP(task) (task_pt_regs(task)->sp) 650bb898558SAl Viro 651bb898558SAl Viro #else 6522cb16181SBrian Gerst extern unsigned long __top_init_kernel_stack[]; 6533adee777SBrian Gerst 6543adee777SBrian Gerst #define INIT_THREAD { \ 6552cb16181SBrian Gerst .sp = (unsigned long)&__top_init_kernel_stack, \ 6563adee777SBrian Gerst } 657bb898558SAl Viro 65889240ba0SStefani Seibold extern unsigned long KSTK_ESP(struct task_struct *task); 659d046ff8bSH. J. Lu 660bb898558SAl Viro #endif /* CONFIG_X86_64 */ 661bb898558SAl Viro 662bb898558SAl Viro extern void start_thread(struct pt_regs *regs, unsigned long new_ip, 663bb898558SAl Viro unsigned long new_sp); 664bb898558SAl Viro 665bb898558SAl Viro /* 666bb898558SAl Viro * This decides where the kernel will search for a free chunk of vm 667bb898558SAl Viro * space during mmap's. 668bb898558SAl Viro */ 6698f3e474fSDmitry Safonov #define __TASK_UNMAPPED_BASE(task_size) (PAGE_ALIGN(task_size / 3)) 670b569bab7SKirill A. Shutemov #define TASK_UNMAPPED_BASE __TASK_UNMAPPED_BASE(TASK_SIZE_LOW) 671bb898558SAl Viro 672bb898558SAl Viro #define KSTK_EIP(task) (task_pt_regs(task)->ip) 673bb898558SAl Viro 674bb898558SAl Viro /* Get/set a process' ability to use the timestamp counter instruction */ 675bb898558SAl Viro #define GET_TSC_CTL(adr) get_tsc_mode((adr)) 676bb898558SAl Viro #define SET_TSC_CTL(val) set_tsc_mode((val)) 677bb898558SAl Viro 678bb898558SAl Viro extern int get_tsc_mode(unsigned long adr); 679bb898558SAl Viro extern int set_tsc_mode(unsigned int val); 680bb898558SAl Viro 681e9ea1e7fSKyle Huey DECLARE_PER_CPU(u64, msr_misc_features_shadow); 682e9ea1e7fSKyle Huey 6834705243dSThomas Gleixner static inline u32 per_cpu_llc_id(unsigned int cpu) 6846e290323SThomas Gleixner { 6856e290323SThomas Gleixner return per_cpu(cpu_info.topo.llc_id, cpu); 6866e290323SThomas Gleixner } 6876e290323SThomas Gleixner 6884705243dSThomas Gleixner static inline u32 per_cpu_l2c_id(unsigned int cpu) 6896e290323SThomas Gleixner { 6906e290323SThomas Gleixner return per_cpu(cpu_info.topo.l2c_id, cpu); 6916e290323SThomas Gleixner } 6929164d949SKim Phillips 693bc8e80d5SBorislav Petkov #ifdef CONFIG_CPU_SUP_AMD 6943743d55bSHuang Rui extern u32 amd_get_highest_perf(void); 695*501bd734SMateusz Guzik 696*501bd734SMateusz Guzik /* 697*501bd734SMateusz Guzik * Issue a DIV 0/1 insn to clear any division data from previous DIV 698*501bd734SMateusz Guzik * operations. 699*501bd734SMateusz Guzik */ 700*501bd734SMateusz Guzik static __always_inline void amd_clear_divider(void) 701*501bd734SMateusz Guzik { 702*501bd734SMateusz Guzik asm volatile(ALTERNATIVE("", "div %2\n\t", X86_BUG_DIV0) 703*501bd734SMateusz Guzik :: "a" (0), "d" (0), "r" (1)); 704*501bd734SMateusz Guzik } 705*501bd734SMateusz Guzik 706566ffa3aSArnd Bergmann extern void amd_check_microcode(void); 707bc8e80d5SBorislav Petkov #else 7083743d55bSHuang Rui static inline u32 amd_get_highest_perf(void) { return 0; } 70977245f1cSBorislav Petkov (AMD) static inline void amd_clear_divider(void) { } 710566ffa3aSArnd Bergmann static inline void amd_check_microcode(void) { } 711bc8e80d5SBorislav Petkov #endif 7126a812691SAndreas Herrmann 713f05e798aSDavid Howells extern unsigned long arch_align_stack(unsigned long sp); 714e5cb113fSAlexey Dobriyan void free_init_pages(const char *what, unsigned long begin, unsigned long end); 7155494c3a6SKees Cook extern void free_kernel_image_pages(const char *what, void *begin, void *end); 716f05e798aSDavid Howells 717f05e798aSDavid Howells void default_idle(void); 7186a377ddcSLen Brown #ifdef CONFIG_XEN 7196a377ddcSLen Brown bool xen_set_default_idle(void); 7206a377ddcSLen Brown #else 7216a377ddcSLen Brown #define xen_set_default_idle 0 7226a377ddcSLen Brown #endif 723f05e798aSDavid Howells 724f9cdf7caSPeter Zijlstra void __noreturn stop_this_cpu(void *dummy); 725ab31c744SAshok Raj void microcode_check(struct cpuinfo_x86 *prev_info); 726c0dd9245SAshok Raj void store_cpu_caps(struct cpuinfo_x86 *info); 727d90a7a0eSJiri Kosina 728d90a7a0eSJiri Kosina enum l1tf_mitigations { 729d90a7a0eSJiri Kosina L1TF_MITIGATION_OFF, 730d90a7a0eSJiri Kosina L1TF_MITIGATION_FLUSH_NOWARN, 731d90a7a0eSJiri Kosina L1TF_MITIGATION_FLUSH, 732d90a7a0eSJiri Kosina L1TF_MITIGATION_FLUSH_NOSMT, 733d90a7a0eSJiri Kosina L1TF_MITIGATION_FULL, 734d90a7a0eSJiri Kosina L1TF_MITIGATION_FULL_FORCE 735d90a7a0eSJiri Kosina }; 736d90a7a0eSJiri Kosina 737d90a7a0eSJiri Kosina extern enum l1tf_mitigations l1tf_mitigation; 738d90a7a0eSJiri Kosina 739bc124170SThomas Gleixner enum mds_mitigations { 740bc124170SThomas Gleixner MDS_MITIGATION_OFF, 741bc124170SThomas Gleixner MDS_MITIGATION_FULL, 74222dd8365SThomas Gleixner MDS_MITIGATION_VMWERV, 743bc124170SThomas Gleixner }; 744bc124170SThomas Gleixner 745eb3515dcSArnd Bergmann extern bool gds_ucode_mitigated(void); 746eb3515dcSArnd Bergmann 74704c30245SBorislav Petkov (AMD) /* 74804c30245SBorislav Petkov (AMD) * Make previous memory operations globally visible before 74904c30245SBorislav Petkov (AMD) * a WRMSR. 75004c30245SBorislav Petkov (AMD) * 75104c30245SBorislav Petkov (AMD) * MFENCE makes writes visible, but only affects load/store 75204c30245SBorislav Petkov (AMD) * instructions. WRMSR is unfortunately not a load/store 75304c30245SBorislav Petkov (AMD) * instruction and is unaffected by MFENCE. The LFENCE ensures 75404c30245SBorislav Petkov (AMD) * that the WRMSR is not reordered. 75504c30245SBorislav Petkov (AMD) * 75604c30245SBorislav Petkov (AMD) * Most WRMSRs are full serializing instructions themselves and 75704c30245SBorislav Petkov (AMD) * do not require this barrier. This is only required for the 75804c30245SBorislav Petkov (AMD) * IA32_TSC_DEADLINE and X2APIC MSRs. 75904c30245SBorislav Petkov (AMD) */ 76004c30245SBorislav Petkov (AMD) static inline void weak_wrmsr_fence(void) 76104c30245SBorislav Petkov (AMD) { 76204c30245SBorislav Petkov (AMD) alternative("mfence; lfence", "", ALT_NOT(X86_FEATURE_APIC_MSRS_FENCE)); 76304c30245SBorislav Petkov (AMD) } 76404c30245SBorislav Petkov (AMD) 7651965aae3SH. Peter Anvin #endif /* _ASM_X86_PROCESSOR_H */ 766