1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _ASM_X86_PGTABLE_H 3 #define _ASM_X86_PGTABLE_H 4 5 #include <linux/mem_encrypt.h> 6 #include <asm/page.h> 7 #include <asm/pgtable_types.h> 8 9 /* 10 * Macro to mark a page protection value as UC- 11 */ 12 #define pgprot_noncached(prot) \ 13 ((boot_cpu_data.x86 > 3) \ 14 ? (__pgprot(pgprot_val(prot) | \ 15 cachemode2protval(_PAGE_CACHE_MODE_UC_MINUS))) \ 16 : (prot)) 17 18 #ifndef __ASSEMBLER__ 19 #include <linux/spinlock.h> 20 #include <asm/x86_init.h> 21 #include <asm/pkru.h> 22 #include <asm/fpu/api.h> 23 #include <asm/coco.h> 24 #include <asm-generic/pgtable_uffd.h> 25 #include <linux/page_table_check.h> 26 27 extern pgd_t early_top_pgt[PTRS_PER_PGD]; 28 bool __init __early_make_pgtable(unsigned long address, pmdval_t pmd); 29 30 struct seq_file; 31 void ptdump_walk_pgd_level(struct seq_file *m, struct mm_struct *mm); 32 void ptdump_walk_pgd_level_debugfs(struct seq_file *m, struct mm_struct *mm, 33 bool user); 34 bool ptdump_walk_pgd_level_checkwx(void); 35 #define ptdump_check_wx ptdump_walk_pgd_level_checkwx 36 void ptdump_walk_user_pgd_level_checkwx(void); 37 38 /* 39 * Macros to add or remove encryption attribute 40 */ 41 #define pgprot_encrypted(prot) __pgprot(cc_mkenc(pgprot_val(prot))) 42 #define pgprot_decrypted(prot) __pgprot(cc_mkdec(pgprot_val(prot))) 43 44 #ifdef CONFIG_DEBUG_WX 45 #define debug_checkwx_user() ptdump_walk_user_pgd_level_checkwx() 46 #else 47 #define debug_checkwx_user() do { } while (0) 48 #endif 49 50 extern spinlock_t pgd_lock; 51 extern struct list_head pgd_list; 52 53 extern struct mm_struct *pgd_page_get_mm(struct page *page); 54 55 extern pmdval_t early_pmd_flags; 56 57 #ifdef CONFIG_PARAVIRT_XXL 58 #include <asm/paravirt.h> 59 #else /* !CONFIG_PARAVIRT_XXL */ 60 #define set_pte(ptep, pte) native_set_pte(ptep, pte) 61 62 #define set_pte_atomic(ptep, pte) \ 63 native_set_pte_atomic(ptep, pte) 64 65 #define set_pmd(pmdp, pmd) native_set_pmd(pmdp, pmd) 66 67 #ifndef __PAGETABLE_P4D_FOLDED 68 #define set_pgd(pgdp, pgd) native_set_pgd(pgdp, pgd) 69 #define pgd_clear(pgd) (pgtable_l5_enabled() ? native_pgd_clear(pgd) : 0) 70 #endif 71 72 #ifndef set_p4d 73 # define set_p4d(p4dp, p4d) native_set_p4d(p4dp, p4d) 74 #endif 75 76 #ifndef __PAGETABLE_PUD_FOLDED 77 #define p4d_clear(p4d) native_p4d_clear(p4d) 78 #endif 79 80 #ifndef set_pud 81 # define set_pud(pudp, pud) native_set_pud(pudp, pud) 82 #endif 83 84 #ifndef __PAGETABLE_PUD_FOLDED 85 #define pud_clear(pud) native_pud_clear(pud) 86 #endif 87 88 #define pte_clear(mm, addr, ptep) native_pte_clear(mm, addr, ptep) 89 #define pmd_clear(pmd) native_pmd_clear(pmd) 90 91 #define pgd_val(x) native_pgd_val(x) 92 #define __pgd(x) native_make_pgd(x) 93 94 #ifndef __PAGETABLE_P4D_FOLDED 95 #define p4d_val(x) native_p4d_val(x) 96 #define __p4d(x) native_make_p4d(x) 97 #endif 98 99 #ifndef __PAGETABLE_PUD_FOLDED 100 #define pud_val(x) native_pud_val(x) 101 #define __pud(x) native_make_pud(x) 102 #endif 103 104 #ifndef __PAGETABLE_PMD_FOLDED 105 #define pmd_val(x) native_pmd_val(x) 106 #define __pmd(x) native_make_pmd(x) 107 #endif 108 109 #define pte_val(x) native_pte_val(x) 110 #define __pte(x) native_make_pte(x) 111 112 #define arch_end_context_switch(prev) do {} while(0) 113 static inline void arch_flush_lazy_mmu_mode(void) {} 114 #endif /* CONFIG_PARAVIRT_XXL */ 115 116 static inline pmd_t pmd_set_flags(pmd_t pmd, pmdval_t set) 117 { 118 pmdval_t v = native_pmd_val(pmd); 119 120 return native_make_pmd(v | set); 121 } 122 123 static inline pmd_t pmd_clear_flags(pmd_t pmd, pmdval_t clear) 124 { 125 pmdval_t v = native_pmd_val(pmd); 126 127 return native_make_pmd(v & ~clear); 128 } 129 130 static inline pud_t pud_set_flags(pud_t pud, pudval_t set) 131 { 132 pudval_t v = native_pud_val(pud); 133 134 return native_make_pud(v | set); 135 } 136 137 static inline pud_t pud_clear_flags(pud_t pud, pudval_t clear) 138 { 139 pudval_t v = native_pud_val(pud); 140 141 return native_make_pud(v & ~clear); 142 } 143 144 /* 145 * The following only work if pte_present() is true. 146 * Undefined behaviour if not.. 147 */ 148 static inline bool pte_dirty(pte_t pte) 149 { 150 return pte_flags(pte) & _PAGE_DIRTY_BITS; 151 } 152 153 static inline bool pte_shstk(pte_t pte) 154 { 155 return cpu_feature_enabled(X86_FEATURE_SHSTK) && 156 (pte_flags(pte) & (_PAGE_RW | _PAGE_DIRTY)) == _PAGE_DIRTY; 157 } 158 159 static inline int pte_young(pte_t pte) 160 { 161 return pte_flags(pte) & _PAGE_ACCESSED; 162 } 163 164 static inline bool pte_decrypted(pte_t pte) 165 { 166 return cc_mkdec(pte_val(pte)) == pte_val(pte); 167 } 168 169 #define pmd_dirty pmd_dirty 170 static inline bool pmd_dirty(pmd_t pmd) 171 { 172 return pmd_flags(pmd) & _PAGE_DIRTY_BITS; 173 } 174 175 static inline bool pmd_shstk(pmd_t pmd) 176 { 177 return cpu_feature_enabled(X86_FEATURE_SHSTK) && 178 (pmd_flags(pmd) & (_PAGE_RW | _PAGE_DIRTY | _PAGE_PSE)) == 179 (_PAGE_DIRTY | _PAGE_PSE); 180 } 181 182 #define pmd_young pmd_young 183 static inline int pmd_young(pmd_t pmd) 184 { 185 return pmd_flags(pmd) & _PAGE_ACCESSED; 186 } 187 188 static inline bool pud_dirty(pud_t pud) 189 { 190 return pud_flags(pud) & _PAGE_DIRTY_BITS; 191 } 192 193 static inline int pud_young(pud_t pud) 194 { 195 return pud_flags(pud) & _PAGE_ACCESSED; 196 } 197 198 static inline bool pud_shstk(pud_t pud) 199 { 200 return cpu_feature_enabled(X86_FEATURE_SHSTK) && 201 (pud_flags(pud) & (_PAGE_RW | _PAGE_DIRTY | _PAGE_PSE)) == 202 (_PAGE_DIRTY | _PAGE_PSE); 203 } 204 205 static inline int pte_write(pte_t pte) 206 { 207 /* 208 * Shadow stack pages are logically writable, but do not have 209 * _PAGE_RW. Check for them separately from _PAGE_RW itself. 210 */ 211 return (pte_flags(pte) & _PAGE_RW) || pte_shstk(pte); 212 } 213 214 #define pmd_write pmd_write 215 static inline int pmd_write(pmd_t pmd) 216 { 217 /* 218 * Shadow stack pages are logically writable, but do not have 219 * _PAGE_RW. Check for them separately from _PAGE_RW itself. 220 */ 221 return (pmd_flags(pmd) & _PAGE_RW) || pmd_shstk(pmd); 222 } 223 224 #define pud_write pud_write 225 static inline int pud_write(pud_t pud) 226 { 227 return pud_flags(pud) & _PAGE_RW; 228 } 229 230 static inline int pte_huge(pte_t pte) 231 { 232 return pte_flags(pte) & _PAGE_PSE; 233 } 234 235 static inline int pte_global(pte_t pte) 236 { 237 return pte_flags(pte) & _PAGE_GLOBAL; 238 } 239 240 static inline int pte_exec(pte_t pte) 241 { 242 return !(pte_flags(pte) & _PAGE_NX); 243 } 244 245 static inline int pte_special(pte_t pte) 246 { 247 return pte_flags(pte) & _PAGE_SPECIAL; 248 } 249 250 /* Entries that were set to PROT_NONE are inverted */ 251 252 static inline u64 protnone_mask(u64 val); 253 254 #define PFN_PTE_SHIFT PAGE_SHIFT 255 256 static inline unsigned long pte_pfn(pte_t pte) 257 { 258 phys_addr_t pfn = pte_val(pte); 259 pfn ^= protnone_mask(pfn); 260 return (pfn & PTE_PFN_MASK) >> PAGE_SHIFT; 261 } 262 263 static inline unsigned long pmd_pfn(pmd_t pmd) 264 { 265 phys_addr_t pfn = pmd_val(pmd); 266 pfn ^= protnone_mask(pfn); 267 return (pfn & pmd_pfn_mask(pmd)) >> PAGE_SHIFT; 268 } 269 270 #define pud_pfn pud_pfn 271 static inline unsigned long pud_pfn(pud_t pud) 272 { 273 phys_addr_t pfn = pud_val(pud); 274 pfn ^= protnone_mask(pfn); 275 return (pfn & pud_pfn_mask(pud)) >> PAGE_SHIFT; 276 } 277 278 static inline unsigned long p4d_pfn(p4d_t p4d) 279 { 280 return (p4d_val(p4d) & p4d_pfn_mask(p4d)) >> PAGE_SHIFT; 281 } 282 283 static inline unsigned long pgd_pfn(pgd_t pgd) 284 { 285 return (pgd_val(pgd) & PTE_PFN_MASK) >> PAGE_SHIFT; 286 } 287 288 #define pte_page(pte) pfn_to_page(pte_pfn(pte)) 289 290 #define pmd_leaf pmd_leaf 291 static inline bool pmd_leaf(pmd_t pte) 292 { 293 return pmd_flags(pte) & _PAGE_PSE; 294 } 295 296 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 297 static inline int pmd_trans_huge(pmd_t pmd) 298 { 299 return (pmd_val(pmd) & _PAGE_PSE) == _PAGE_PSE; 300 } 301 302 #ifdef CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD 303 static inline int pud_trans_huge(pud_t pud) 304 { 305 return (pud_val(pud) & _PAGE_PSE) == _PAGE_PSE; 306 } 307 #endif 308 309 #define has_transparent_hugepage has_transparent_hugepage 310 static inline int has_transparent_hugepage(void) 311 { 312 return boot_cpu_has(X86_FEATURE_PSE); 313 } 314 315 #ifdef CONFIG_ARCH_SUPPORTS_PMD_PFNMAP 316 static inline bool pmd_special(pmd_t pmd) 317 { 318 return pmd_flags(pmd) & _PAGE_SPECIAL; 319 } 320 321 static inline pmd_t pmd_mkspecial(pmd_t pmd) 322 { 323 return pmd_set_flags(pmd, _PAGE_SPECIAL); 324 } 325 #endif /* CONFIG_ARCH_SUPPORTS_PMD_PFNMAP */ 326 327 #ifdef CONFIG_ARCH_SUPPORTS_PUD_PFNMAP 328 static inline bool pud_special(pud_t pud) 329 { 330 return pud_flags(pud) & _PAGE_SPECIAL; 331 } 332 333 static inline pud_t pud_mkspecial(pud_t pud) 334 { 335 return pud_set_flags(pud, _PAGE_SPECIAL); 336 } 337 #endif /* CONFIG_ARCH_SUPPORTS_PUD_PFNMAP */ 338 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 339 340 static inline pte_t pte_set_flags(pte_t pte, pteval_t set) 341 { 342 pteval_t v = native_pte_val(pte); 343 344 return native_make_pte(v | set); 345 } 346 347 static inline pte_t pte_clear_flags(pte_t pte, pteval_t clear) 348 { 349 pteval_t v = native_pte_val(pte); 350 351 return native_make_pte(v & ~clear); 352 } 353 354 /* 355 * Write protection operations can result in Dirty=1,Write=0 PTEs. But in the 356 * case of X86_FEATURE_USER_SHSTK, these PTEs denote shadow stack memory. So 357 * when creating dirty, write-protected memory, a software bit is used: 358 * _PAGE_BIT_SAVED_DIRTY. The following functions take a PTE and transition the 359 * Dirty bit to SavedDirty, and vice-vesra. 360 * 361 * This shifting is only done if needed. In the case of shifting 362 * Dirty->SavedDirty, the condition is if the PTE is Write=0. In the case of 363 * shifting SavedDirty->Dirty, the condition is Write=1. 364 */ 365 static inline pgprotval_t mksaveddirty_shift(pgprotval_t v) 366 { 367 pgprotval_t cond = (~v >> _PAGE_BIT_RW) & 1; 368 369 v |= ((v >> _PAGE_BIT_DIRTY) & cond) << _PAGE_BIT_SAVED_DIRTY; 370 v &= ~(cond << _PAGE_BIT_DIRTY); 371 372 return v; 373 } 374 375 static inline pgprotval_t clear_saveddirty_shift(pgprotval_t v) 376 { 377 pgprotval_t cond = (v >> _PAGE_BIT_RW) & 1; 378 379 v |= ((v >> _PAGE_BIT_SAVED_DIRTY) & cond) << _PAGE_BIT_DIRTY; 380 v &= ~(cond << _PAGE_BIT_SAVED_DIRTY); 381 382 return v; 383 } 384 385 static inline pte_t pte_mksaveddirty(pte_t pte) 386 { 387 pteval_t v = native_pte_val(pte); 388 389 v = mksaveddirty_shift(v); 390 return native_make_pte(v); 391 } 392 393 static inline pte_t pte_clear_saveddirty(pte_t pte) 394 { 395 pteval_t v = native_pte_val(pte); 396 397 v = clear_saveddirty_shift(v); 398 return native_make_pte(v); 399 } 400 401 static inline pte_t pte_wrprotect(pte_t pte) 402 { 403 pte = pte_clear_flags(pte, _PAGE_RW); 404 405 /* 406 * Blindly clearing _PAGE_RW might accidentally create 407 * a shadow stack PTE (Write=0,Dirty=1). Move the hardware 408 * dirty value to the software bit, if present. 409 */ 410 return pte_mksaveddirty(pte); 411 } 412 413 #ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP 414 static inline int pte_uffd_wp(pte_t pte) 415 { 416 return pte_flags(pte) & _PAGE_UFFD_WP; 417 } 418 419 static inline pte_t pte_mkuffd_wp(pte_t pte) 420 { 421 return pte_wrprotect(pte_set_flags(pte, _PAGE_UFFD_WP)); 422 } 423 424 static inline pte_t pte_clear_uffd_wp(pte_t pte) 425 { 426 return pte_clear_flags(pte, _PAGE_UFFD_WP); 427 } 428 #endif /* CONFIG_HAVE_ARCH_USERFAULTFD_WP */ 429 430 static inline pte_t pte_mkclean(pte_t pte) 431 { 432 return pte_clear_flags(pte, _PAGE_DIRTY_BITS); 433 } 434 435 static inline pte_t pte_mkold(pte_t pte) 436 { 437 return pte_clear_flags(pte, _PAGE_ACCESSED); 438 } 439 440 static inline pte_t pte_mkexec(pte_t pte) 441 { 442 return pte_clear_flags(pte, _PAGE_NX); 443 } 444 445 static inline pte_t pte_mkdirty(pte_t pte) 446 { 447 pte = pte_set_flags(pte, _PAGE_DIRTY | _PAGE_SOFT_DIRTY); 448 449 return pte_mksaveddirty(pte); 450 } 451 452 static inline pte_t pte_mkwrite_shstk(pte_t pte) 453 { 454 pte = pte_clear_flags(pte, _PAGE_RW); 455 456 return pte_set_flags(pte, _PAGE_DIRTY); 457 } 458 459 static inline pte_t pte_mkyoung(pte_t pte) 460 { 461 return pte_set_flags(pte, _PAGE_ACCESSED); 462 } 463 464 static inline pte_t pte_mkwrite_novma(pte_t pte) 465 { 466 return pte_set_flags(pte, _PAGE_RW); 467 } 468 469 struct vm_area_struct; 470 pte_t pte_mkwrite(pte_t pte, struct vm_area_struct *vma); 471 #define pte_mkwrite pte_mkwrite 472 473 static inline pte_t pte_mkhuge(pte_t pte) 474 { 475 return pte_set_flags(pte, _PAGE_PSE); 476 } 477 478 static inline pte_t pte_clrhuge(pte_t pte) 479 { 480 return pte_clear_flags(pte, _PAGE_PSE); 481 } 482 483 static inline pte_t pte_mkglobal(pte_t pte) 484 { 485 return pte_set_flags(pte, _PAGE_GLOBAL); 486 } 487 488 static inline pte_t pte_clrglobal(pte_t pte) 489 { 490 return pte_clear_flags(pte, _PAGE_GLOBAL); 491 } 492 493 static inline pte_t pte_mkspecial(pte_t pte) 494 { 495 return pte_set_flags(pte, _PAGE_SPECIAL); 496 } 497 498 /* See comments above mksaveddirty_shift() */ 499 static inline pmd_t pmd_mksaveddirty(pmd_t pmd) 500 { 501 pmdval_t v = native_pmd_val(pmd); 502 503 v = mksaveddirty_shift(v); 504 return native_make_pmd(v); 505 } 506 507 /* See comments above mksaveddirty_shift() */ 508 static inline pmd_t pmd_clear_saveddirty(pmd_t pmd) 509 { 510 pmdval_t v = native_pmd_val(pmd); 511 512 v = clear_saveddirty_shift(v); 513 return native_make_pmd(v); 514 } 515 516 static inline pmd_t pmd_wrprotect(pmd_t pmd) 517 { 518 pmd = pmd_clear_flags(pmd, _PAGE_RW); 519 520 /* 521 * Blindly clearing _PAGE_RW might accidentally create 522 * a shadow stack PMD (RW=0, Dirty=1). Move the hardware 523 * dirty value to the software bit. 524 */ 525 return pmd_mksaveddirty(pmd); 526 } 527 528 #ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP 529 static inline int pmd_uffd_wp(pmd_t pmd) 530 { 531 return pmd_flags(pmd) & _PAGE_UFFD_WP; 532 } 533 534 static inline pmd_t pmd_mkuffd_wp(pmd_t pmd) 535 { 536 return pmd_wrprotect(pmd_set_flags(pmd, _PAGE_UFFD_WP)); 537 } 538 539 static inline pmd_t pmd_clear_uffd_wp(pmd_t pmd) 540 { 541 return pmd_clear_flags(pmd, _PAGE_UFFD_WP); 542 } 543 #endif /* CONFIG_HAVE_ARCH_USERFAULTFD_WP */ 544 545 static inline pmd_t pmd_mkold(pmd_t pmd) 546 { 547 return pmd_clear_flags(pmd, _PAGE_ACCESSED); 548 } 549 550 static inline pmd_t pmd_mkclean(pmd_t pmd) 551 { 552 return pmd_clear_flags(pmd, _PAGE_DIRTY_BITS); 553 } 554 555 static inline pmd_t pmd_mkdirty(pmd_t pmd) 556 { 557 pmd = pmd_set_flags(pmd, _PAGE_DIRTY | _PAGE_SOFT_DIRTY); 558 559 return pmd_mksaveddirty(pmd); 560 } 561 562 static inline pmd_t pmd_mkwrite_shstk(pmd_t pmd) 563 { 564 pmd = pmd_clear_flags(pmd, _PAGE_RW); 565 566 return pmd_set_flags(pmd, _PAGE_DIRTY); 567 } 568 569 static inline pmd_t pmd_mkhuge(pmd_t pmd) 570 { 571 return pmd_set_flags(pmd, _PAGE_PSE); 572 } 573 574 static inline pmd_t pmd_mkyoung(pmd_t pmd) 575 { 576 return pmd_set_flags(pmd, _PAGE_ACCESSED); 577 } 578 579 static inline pmd_t pmd_mkwrite_novma(pmd_t pmd) 580 { 581 return pmd_set_flags(pmd, _PAGE_RW); 582 } 583 584 pmd_t pmd_mkwrite(pmd_t pmd, struct vm_area_struct *vma); 585 #define pmd_mkwrite pmd_mkwrite 586 587 /* See comments above mksaveddirty_shift() */ 588 static inline pud_t pud_mksaveddirty(pud_t pud) 589 { 590 pudval_t v = native_pud_val(pud); 591 592 v = mksaveddirty_shift(v); 593 return native_make_pud(v); 594 } 595 596 /* See comments above mksaveddirty_shift() */ 597 static inline pud_t pud_clear_saveddirty(pud_t pud) 598 { 599 pudval_t v = native_pud_val(pud); 600 601 v = clear_saveddirty_shift(v); 602 return native_make_pud(v); 603 } 604 605 static inline pud_t pud_mkold(pud_t pud) 606 { 607 return pud_clear_flags(pud, _PAGE_ACCESSED); 608 } 609 610 static inline pud_t pud_mkclean(pud_t pud) 611 { 612 return pud_clear_flags(pud, _PAGE_DIRTY_BITS); 613 } 614 615 static inline pud_t pud_wrprotect(pud_t pud) 616 { 617 pud = pud_clear_flags(pud, _PAGE_RW); 618 619 /* 620 * Blindly clearing _PAGE_RW might accidentally create 621 * a shadow stack PUD (RW=0, Dirty=1). Move the hardware 622 * dirty value to the software bit. 623 */ 624 return pud_mksaveddirty(pud); 625 } 626 627 static inline pud_t pud_mkdirty(pud_t pud) 628 { 629 pud = pud_set_flags(pud, _PAGE_DIRTY | _PAGE_SOFT_DIRTY); 630 631 return pud_mksaveddirty(pud); 632 } 633 634 static inline pud_t pud_mkhuge(pud_t pud) 635 { 636 return pud_set_flags(pud, _PAGE_PSE); 637 } 638 639 static inline pud_t pud_mkyoung(pud_t pud) 640 { 641 return pud_set_flags(pud, _PAGE_ACCESSED); 642 } 643 644 static inline pud_t pud_mkwrite(pud_t pud) 645 { 646 pud = pud_set_flags(pud, _PAGE_RW); 647 648 return pud_clear_saveddirty(pud); 649 } 650 651 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 652 static inline int pte_soft_dirty(pte_t pte) 653 { 654 return pte_flags(pte) & _PAGE_SOFT_DIRTY; 655 } 656 657 static inline int pmd_soft_dirty(pmd_t pmd) 658 { 659 return pmd_flags(pmd) & _PAGE_SOFT_DIRTY; 660 } 661 662 static inline int pud_soft_dirty(pud_t pud) 663 { 664 return pud_flags(pud) & _PAGE_SOFT_DIRTY; 665 } 666 667 static inline pte_t pte_mksoft_dirty(pte_t pte) 668 { 669 return pte_set_flags(pte, _PAGE_SOFT_DIRTY); 670 } 671 672 static inline pmd_t pmd_mksoft_dirty(pmd_t pmd) 673 { 674 return pmd_set_flags(pmd, _PAGE_SOFT_DIRTY); 675 } 676 677 static inline pud_t pud_mksoft_dirty(pud_t pud) 678 { 679 return pud_set_flags(pud, _PAGE_SOFT_DIRTY); 680 } 681 682 static inline pte_t pte_clear_soft_dirty(pte_t pte) 683 { 684 return pte_clear_flags(pte, _PAGE_SOFT_DIRTY); 685 } 686 687 static inline pmd_t pmd_clear_soft_dirty(pmd_t pmd) 688 { 689 return pmd_clear_flags(pmd, _PAGE_SOFT_DIRTY); 690 } 691 692 static inline pud_t pud_clear_soft_dirty(pud_t pud) 693 { 694 return pud_clear_flags(pud, _PAGE_SOFT_DIRTY); 695 } 696 697 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ 698 699 /* 700 * Mask out unsupported bits in a present pgprot. Non-present pgprots 701 * can use those bits for other purposes, so leave them be. 702 */ 703 static inline pgprotval_t massage_pgprot(pgprot_t pgprot) 704 { 705 pgprotval_t protval = pgprot_val(pgprot); 706 707 if (protval & _PAGE_PRESENT) 708 protval &= __supported_pte_mask; 709 710 return protval; 711 } 712 713 static inline pgprotval_t check_pgprot(pgprot_t pgprot) 714 { 715 pgprotval_t massaged_val = massage_pgprot(pgprot); 716 717 /* mmdebug.h can not be included here because of dependencies */ 718 #ifdef CONFIG_DEBUG_VM 719 WARN_ONCE(pgprot_val(pgprot) != massaged_val, 720 "attempted to set unsupported pgprot: %016llx " 721 "bits: %016llx supported: %016llx\n", 722 (u64)pgprot_val(pgprot), 723 (u64)pgprot_val(pgprot) ^ massaged_val, 724 (u64)__supported_pte_mask); 725 #endif 726 727 return massaged_val; 728 } 729 730 static inline pte_t pfn_pte(unsigned long page_nr, pgprot_t pgprot) 731 { 732 phys_addr_t pfn = (phys_addr_t)page_nr << PAGE_SHIFT; 733 /* This bit combination is used to mark shadow stacks */ 734 WARN_ON_ONCE((pgprot_val(pgprot) & (_PAGE_DIRTY | _PAGE_RW)) == 735 _PAGE_DIRTY); 736 pfn ^= protnone_mask(pgprot_val(pgprot)); 737 pfn &= PTE_PFN_MASK; 738 return __pte(pfn | check_pgprot(pgprot)); 739 } 740 741 static inline pmd_t pfn_pmd(unsigned long page_nr, pgprot_t pgprot) 742 { 743 phys_addr_t pfn = (phys_addr_t)page_nr << PAGE_SHIFT; 744 pfn ^= protnone_mask(pgprot_val(pgprot)); 745 pfn &= PHYSICAL_PMD_PAGE_MASK; 746 return __pmd(pfn | check_pgprot(pgprot)); 747 } 748 749 static inline pud_t pfn_pud(unsigned long page_nr, pgprot_t pgprot) 750 { 751 phys_addr_t pfn = (phys_addr_t)page_nr << PAGE_SHIFT; 752 pfn ^= protnone_mask(pgprot_val(pgprot)); 753 pfn &= PHYSICAL_PUD_PAGE_MASK; 754 return __pud(pfn | check_pgprot(pgprot)); 755 } 756 757 static inline pmd_t pmd_mkinvalid(pmd_t pmd) 758 { 759 return pfn_pmd(pmd_pfn(pmd), 760 __pgprot(pmd_flags(pmd) & ~(_PAGE_PRESENT|_PAGE_PROTNONE))); 761 } 762 763 static inline pud_t pud_mkinvalid(pud_t pud) 764 { 765 return pfn_pud(pud_pfn(pud), 766 __pgprot(pud_flags(pud) & ~(_PAGE_PRESENT|_PAGE_PROTNONE))); 767 } 768 769 static inline u64 flip_protnone_guard(u64 oldval, u64 val, u64 mask); 770 771 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 772 { 773 pteval_t val = pte_val(pte), oldval = val; 774 pte_t pte_result; 775 776 /* 777 * Chop off the NX bit (if present), and add the NX portion of 778 * the newprot (if present): 779 */ 780 val &= _PAGE_CHG_MASK; 781 val |= check_pgprot(newprot) & ~_PAGE_CHG_MASK; 782 val = flip_protnone_guard(oldval, val, PTE_PFN_MASK); 783 784 pte_result = __pte(val); 785 786 /* 787 * To avoid creating Write=0,Dirty=1 PTEs, pte_modify() needs to avoid: 788 * 1. Marking Write=0 PTEs Dirty=1 789 * 2. Marking Dirty=1 PTEs Write=0 790 * 791 * The first case cannot happen because the _PAGE_CHG_MASK will filter 792 * out any Dirty bit passed in newprot. Handle the second case by 793 * going through the mksaveddirty exercise. Only do this if the old 794 * value was Write=1 to avoid doing this on Shadow Stack PTEs. 795 */ 796 if (oldval & _PAGE_RW) 797 pte_result = pte_mksaveddirty(pte_result); 798 else 799 pte_result = pte_clear_saveddirty(pte_result); 800 801 return pte_result; 802 } 803 804 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) 805 { 806 pmdval_t val = pmd_val(pmd), oldval = val; 807 pmd_t pmd_result; 808 809 val &= (_HPAGE_CHG_MASK & ~_PAGE_DIRTY); 810 val |= check_pgprot(newprot) & ~_HPAGE_CHG_MASK; 811 val = flip_protnone_guard(oldval, val, PHYSICAL_PMD_PAGE_MASK); 812 813 pmd_result = __pmd(val); 814 815 /* 816 * Avoid creating shadow stack PMD by accident. See comment in 817 * pte_modify(). 818 */ 819 if (oldval & _PAGE_RW) 820 pmd_result = pmd_mksaveddirty(pmd_result); 821 else 822 pmd_result = pmd_clear_saveddirty(pmd_result); 823 824 return pmd_result; 825 } 826 827 static inline pud_t pud_modify(pud_t pud, pgprot_t newprot) 828 { 829 pudval_t val = pud_val(pud), oldval = val; 830 pud_t pud_result; 831 832 val &= _HPAGE_CHG_MASK; 833 val |= check_pgprot(newprot) & ~_HPAGE_CHG_MASK; 834 val = flip_protnone_guard(oldval, val, PHYSICAL_PUD_PAGE_MASK); 835 836 pud_result = __pud(val); 837 838 /* 839 * Avoid creating shadow stack PUD by accident. See comment in 840 * pte_modify(). 841 */ 842 if (oldval & _PAGE_RW) 843 pud_result = pud_mksaveddirty(pud_result); 844 else 845 pud_result = pud_clear_saveddirty(pud_result); 846 847 return pud_result; 848 } 849 850 /* 851 * mprotect needs to preserve PAT and encryption bits when updating 852 * vm_page_prot 853 */ 854 #define pgprot_modify pgprot_modify 855 static inline pgprot_t pgprot_modify(pgprot_t oldprot, pgprot_t newprot) 856 { 857 pgprotval_t preservebits = pgprot_val(oldprot) & _PAGE_CHG_MASK; 858 pgprotval_t addbits = pgprot_val(newprot) & ~_PAGE_CHG_MASK; 859 return __pgprot(preservebits | addbits); 860 } 861 862 #define pte_pgprot(x) __pgprot(pte_flags(x)) 863 #define pmd_pgprot(x) __pgprot(pmd_flags(x)) 864 #define pud_pgprot(x) __pgprot(pud_flags(x)) 865 #define p4d_pgprot(x) __pgprot(p4d_flags(x)) 866 867 #define canon_pgprot(p) __pgprot(massage_pgprot(p)) 868 869 static inline int is_new_memtype_allowed(u64 paddr, unsigned long size, 870 enum page_cache_mode pcm, 871 enum page_cache_mode new_pcm) 872 { 873 /* 874 * PAT type is always WB for untracked ranges, so no need to check. 875 */ 876 if (x86_platform.is_untracked_pat_range(paddr, paddr + size)) 877 return 1; 878 879 /* 880 * Certain new memtypes are not allowed with certain 881 * requested memtype: 882 * - request is uncached, return cannot be write-back 883 * - request is write-combine, return cannot be write-back 884 * - request is write-through, return cannot be write-back 885 * - request is write-through, return cannot be write-combine 886 */ 887 if ((pcm == _PAGE_CACHE_MODE_UC_MINUS && 888 new_pcm == _PAGE_CACHE_MODE_WB) || 889 (pcm == _PAGE_CACHE_MODE_WC && 890 new_pcm == _PAGE_CACHE_MODE_WB) || 891 (pcm == _PAGE_CACHE_MODE_WT && 892 new_pcm == _PAGE_CACHE_MODE_WB) || 893 (pcm == _PAGE_CACHE_MODE_WT && 894 new_pcm == _PAGE_CACHE_MODE_WC)) { 895 return 0; 896 } 897 898 return 1; 899 } 900 901 pmd_t *populate_extra_pmd(unsigned long vaddr); 902 pte_t *populate_extra_pte(unsigned long vaddr); 903 904 #ifdef CONFIG_MITIGATION_PAGE_TABLE_ISOLATION 905 pgd_t __pti_set_user_pgtbl(pgd_t *pgdp, pgd_t pgd); 906 907 /* 908 * Take a PGD location (pgdp) and a pgd value that needs to be set there. 909 * Populates the user and returns the resulting PGD that must be set in 910 * the kernel copy of the page tables. 911 */ 912 static inline pgd_t pti_set_user_pgtbl(pgd_t *pgdp, pgd_t pgd) 913 { 914 if (!static_cpu_has(X86_FEATURE_PTI)) 915 return pgd; 916 return __pti_set_user_pgtbl(pgdp, pgd); 917 } 918 #else /* CONFIG_MITIGATION_PAGE_TABLE_ISOLATION */ 919 static inline pgd_t pti_set_user_pgtbl(pgd_t *pgdp, pgd_t pgd) 920 { 921 return pgd; 922 } 923 #endif /* CONFIG_MITIGATION_PAGE_TABLE_ISOLATION */ 924 925 #endif /* __ASSEMBLER__ */ 926 927 928 #ifdef CONFIG_X86_32 929 # include <asm/pgtable_32.h> 930 #else 931 # include <asm/pgtable_64.h> 932 #endif 933 934 #ifndef __ASSEMBLER__ 935 #include <linux/mm_types.h> 936 #include <linux/mmdebug.h> 937 #include <linux/log2.h> 938 #include <asm/fixmap.h> 939 940 static inline int pte_none(pte_t pte) 941 { 942 return !(pte.pte & ~(_PAGE_KNL_ERRATUM_MASK)); 943 } 944 945 #define __HAVE_ARCH_PTE_SAME 946 static inline int pte_same(pte_t a, pte_t b) 947 { 948 return a.pte == b.pte; 949 } 950 951 static inline pte_t pte_advance_pfn(pte_t pte, unsigned long nr) 952 { 953 if (__pte_needs_invert(pte_val(pte))) 954 return __pte(pte_val(pte) - (nr << PFN_PTE_SHIFT)); 955 return __pte(pte_val(pte) + (nr << PFN_PTE_SHIFT)); 956 } 957 #define pte_advance_pfn pte_advance_pfn 958 959 static inline int pte_present(pte_t a) 960 { 961 return pte_flags(a) & (_PAGE_PRESENT | _PAGE_PROTNONE); 962 } 963 964 #define pte_accessible pte_accessible 965 static inline bool pte_accessible(struct mm_struct *mm, pte_t a) 966 { 967 if (pte_flags(a) & _PAGE_PRESENT) 968 return true; 969 970 if ((pte_flags(a) & _PAGE_PROTNONE) && 971 atomic_read(&mm->tlb_flush_pending)) 972 return true; 973 974 return false; 975 } 976 977 static inline int pmd_present(pmd_t pmd) 978 { 979 /* 980 * Checking for _PAGE_PSE is needed too because 981 * split_huge_page will temporarily clear the present bit (but 982 * the _PAGE_PSE flag will remain set at all times while the 983 * _PAGE_PRESENT bit is clear). 984 */ 985 return pmd_flags(pmd) & (_PAGE_PRESENT | _PAGE_PROTNONE | _PAGE_PSE); 986 } 987 988 #ifdef CONFIG_NUMA_BALANCING 989 /* 990 * These work without NUMA balancing but the kernel does not care. See the 991 * comment in include/linux/pgtable.h 992 */ 993 static inline int pte_protnone(pte_t pte) 994 { 995 return (pte_flags(pte) & (_PAGE_PROTNONE | _PAGE_PRESENT)) 996 == _PAGE_PROTNONE; 997 } 998 999 static inline int pmd_protnone(pmd_t pmd) 1000 { 1001 return (pmd_flags(pmd) & (_PAGE_PROTNONE | _PAGE_PRESENT)) 1002 == _PAGE_PROTNONE; 1003 } 1004 #endif /* CONFIG_NUMA_BALANCING */ 1005 1006 static inline int pmd_none(pmd_t pmd) 1007 { 1008 /* Only check low word on 32-bit platforms, since it might be 1009 out of sync with upper half. */ 1010 unsigned long val = native_pmd_val(pmd); 1011 return (val & ~_PAGE_KNL_ERRATUM_MASK) == 0; 1012 } 1013 1014 static inline unsigned long pmd_page_vaddr(pmd_t pmd) 1015 { 1016 return (unsigned long)__va(pmd_val(pmd) & pmd_pfn_mask(pmd)); 1017 } 1018 1019 /* 1020 * Currently stuck as a macro due to indirect forward reference to 1021 * linux/mmzone.h's __section_mem_map_addr() definition: 1022 */ 1023 #define pmd_page(pmd) pfn_to_page(pmd_pfn(pmd)) 1024 1025 static inline int pmd_bad(pmd_t pmd) 1026 { 1027 return (pmd_flags(pmd) & ~(_PAGE_USER | _PAGE_ACCESSED)) != 1028 (_KERNPG_TABLE & ~_PAGE_ACCESSED); 1029 } 1030 1031 static inline unsigned long pages_to_mb(unsigned long npg) 1032 { 1033 return npg >> (20 - PAGE_SHIFT); 1034 } 1035 1036 #if CONFIG_PGTABLE_LEVELS > 2 1037 static inline int pud_none(pud_t pud) 1038 { 1039 return (native_pud_val(pud) & ~(_PAGE_KNL_ERRATUM_MASK)) == 0; 1040 } 1041 1042 static inline int pud_present(pud_t pud) 1043 { 1044 return pud_flags(pud) & _PAGE_PRESENT; 1045 } 1046 1047 static inline pmd_t *pud_pgtable(pud_t pud) 1048 { 1049 return (pmd_t *)__va(pud_val(pud) & pud_pfn_mask(pud)); 1050 } 1051 1052 /* 1053 * Currently stuck as a macro due to indirect forward reference to 1054 * linux/mmzone.h's __section_mem_map_addr() definition: 1055 */ 1056 #define pud_page(pud) pfn_to_page(pud_pfn(pud)) 1057 1058 #define pud_leaf pud_leaf 1059 static inline bool pud_leaf(pud_t pud) 1060 { 1061 return pud_val(pud) & _PAGE_PSE; 1062 } 1063 1064 static inline int pud_bad(pud_t pud) 1065 { 1066 return (pud_flags(pud) & ~(_KERNPG_TABLE | _PAGE_USER)) != 0; 1067 } 1068 #endif /* CONFIG_PGTABLE_LEVELS > 2 */ 1069 1070 #if CONFIG_PGTABLE_LEVELS > 3 1071 static inline int p4d_none(p4d_t p4d) 1072 { 1073 return (native_p4d_val(p4d) & ~(_PAGE_KNL_ERRATUM_MASK)) == 0; 1074 } 1075 1076 static inline int p4d_present(p4d_t p4d) 1077 { 1078 return p4d_flags(p4d) & _PAGE_PRESENT; 1079 } 1080 1081 static inline pud_t *p4d_pgtable(p4d_t p4d) 1082 { 1083 return (pud_t *)__va(p4d_val(p4d) & p4d_pfn_mask(p4d)); 1084 } 1085 1086 /* 1087 * Currently stuck as a macro due to indirect forward reference to 1088 * linux/mmzone.h's __section_mem_map_addr() definition: 1089 */ 1090 #define p4d_page(p4d) pfn_to_page(p4d_pfn(p4d)) 1091 1092 static inline int p4d_bad(p4d_t p4d) 1093 { 1094 unsigned long ignore_flags = _KERNPG_TABLE | _PAGE_USER; 1095 1096 if (IS_ENABLED(CONFIG_MITIGATION_PAGE_TABLE_ISOLATION)) 1097 ignore_flags |= _PAGE_NX; 1098 1099 return (p4d_flags(p4d) & ~ignore_flags) != 0; 1100 } 1101 #endif /* CONFIG_PGTABLE_LEVELS > 3 */ 1102 1103 static inline unsigned long p4d_index(unsigned long address) 1104 { 1105 return (address >> P4D_SHIFT) & (PTRS_PER_P4D - 1); 1106 } 1107 1108 #if CONFIG_PGTABLE_LEVELS > 4 1109 static inline int pgd_present(pgd_t pgd) 1110 { 1111 if (!pgtable_l5_enabled()) 1112 return 1; 1113 return pgd_flags(pgd) & _PAGE_PRESENT; 1114 } 1115 1116 static inline unsigned long pgd_page_vaddr(pgd_t pgd) 1117 { 1118 return (unsigned long)__va((unsigned long)pgd_val(pgd) & PTE_PFN_MASK); 1119 } 1120 1121 /* 1122 * Currently stuck as a macro due to indirect forward reference to 1123 * linux/mmzone.h's __section_mem_map_addr() definition: 1124 */ 1125 #define pgd_page(pgd) pfn_to_page(pgd_pfn(pgd)) 1126 1127 /* to find an entry in a page-table-directory. */ 1128 static inline p4d_t *p4d_offset(pgd_t *pgd, unsigned long address) 1129 { 1130 if (!pgtable_l5_enabled()) 1131 return (p4d_t *)pgd; 1132 return (p4d_t *)pgd_page_vaddr(*pgd) + p4d_index(address); 1133 } 1134 1135 static inline int pgd_bad(pgd_t pgd) 1136 { 1137 unsigned long ignore_flags = _PAGE_USER; 1138 1139 if (!pgtable_l5_enabled()) 1140 return 0; 1141 1142 if (IS_ENABLED(CONFIG_MITIGATION_PAGE_TABLE_ISOLATION)) 1143 ignore_flags |= _PAGE_NX; 1144 1145 return (pgd_flags(pgd) & ~ignore_flags) != _KERNPG_TABLE; 1146 } 1147 1148 static inline int pgd_none(pgd_t pgd) 1149 { 1150 if (!pgtable_l5_enabled()) 1151 return 0; 1152 /* 1153 * There is no need to do a workaround for the KNL stray 1154 * A/D bit erratum here. PGDs only point to page tables 1155 * except on 32-bit non-PAE which is not supported on 1156 * KNL. 1157 */ 1158 return !native_pgd_val(pgd); 1159 } 1160 #endif /* CONFIG_PGTABLE_LEVELS > 4 */ 1161 1162 #endif /* __ASSEMBLER__ */ 1163 1164 #define KERNEL_PGD_BOUNDARY pgd_index(PAGE_OFFSET) 1165 #define KERNEL_PGD_PTRS (PTRS_PER_PGD - KERNEL_PGD_BOUNDARY) 1166 1167 #ifndef __ASSEMBLER__ 1168 1169 extern int direct_gbpages; 1170 void init_mem_mapping(void); 1171 void early_alloc_pgt_buf(void); 1172 void __init poking_init(void); 1173 unsigned long init_memory_mapping(unsigned long start, 1174 unsigned long end, pgprot_t prot); 1175 1176 #ifdef CONFIG_X86_64 1177 extern pgd_t trampoline_pgd_entry; 1178 #endif 1179 1180 /* local pte updates need not use xchg for locking */ 1181 static inline pte_t native_local_ptep_get_and_clear(pte_t *ptep) 1182 { 1183 pte_t res = *ptep; 1184 1185 /* Pure native function needs no input for mm, addr */ 1186 native_pte_clear(NULL, 0, ptep); 1187 return res; 1188 } 1189 1190 static inline pmd_t native_local_pmdp_get_and_clear(pmd_t *pmdp) 1191 { 1192 pmd_t res = *pmdp; 1193 1194 native_pmd_clear(pmdp); 1195 return res; 1196 } 1197 1198 static inline pud_t native_local_pudp_get_and_clear(pud_t *pudp) 1199 { 1200 pud_t res = *pudp; 1201 1202 native_pud_clear(pudp); 1203 return res; 1204 } 1205 1206 static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr, 1207 pmd_t *pmdp, pmd_t pmd) 1208 { 1209 page_table_check_pmd_set(mm, addr, pmdp, pmd); 1210 set_pmd(pmdp, pmd); 1211 } 1212 1213 static inline void set_pud_at(struct mm_struct *mm, unsigned long addr, 1214 pud_t *pudp, pud_t pud) 1215 { 1216 page_table_check_pud_set(mm, addr, pudp, pud); 1217 native_set_pud(pudp, pud); 1218 } 1219 1220 /* 1221 * We only update the dirty/accessed state if we set 1222 * the dirty bit by hand in the kernel, since the hardware 1223 * will do the accessed bit for us, and we don't want to 1224 * race with other CPU's that might be updating the dirty 1225 * bit at the same time. 1226 */ 1227 struct vm_area_struct; 1228 1229 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 1230 extern int ptep_set_access_flags(struct vm_area_struct *vma, 1231 unsigned long address, pte_t *ptep, 1232 pte_t entry, int dirty); 1233 1234 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 1235 bool ptep_test_and_clear_young(struct vm_area_struct *vma, 1236 unsigned long addr, pte_t *ptep); 1237 1238 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 1239 bool ptep_clear_flush_young(struct vm_area_struct *vma, 1240 unsigned long address, pte_t *ptep); 1241 1242 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 1243 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, 1244 pte_t *ptep) 1245 { 1246 pte_t pte = native_ptep_get_and_clear(ptep); 1247 page_table_check_pte_clear(mm, addr, pte); 1248 return pte; 1249 } 1250 1251 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL 1252 static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm, 1253 unsigned long addr, pte_t *ptep, 1254 int full) 1255 { 1256 pte_t pte; 1257 if (full) { 1258 /* 1259 * Full address destruction in progress; paravirt does not 1260 * care about updates and native needs no locking 1261 */ 1262 pte = native_local_ptep_get_and_clear(ptep); 1263 page_table_check_pte_clear(mm, addr, pte); 1264 } else { 1265 pte = ptep_get_and_clear(mm, addr, ptep); 1266 } 1267 return pte; 1268 } 1269 1270 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 1271 static inline void ptep_set_wrprotect(struct mm_struct *mm, 1272 unsigned long addr, pte_t *ptep) 1273 { 1274 /* 1275 * Avoid accidentally creating shadow stack PTEs 1276 * (Write=0,Dirty=1). Use cmpxchg() to prevent races with 1277 * the hardware setting Dirty=1. 1278 */ 1279 pte_t old_pte, new_pte; 1280 1281 old_pte = READ_ONCE(*ptep); 1282 do { 1283 new_pte = pte_wrprotect(old_pte); 1284 } while (!try_cmpxchg((long *)&ptep->pte, (long *)&old_pte, *(long *)&new_pte)); 1285 } 1286 1287 /* 1288 * Note: strictly-zero compare is narrower than pte_none(), but the gap is 1289 * harmless: _PAGE_DIRTY and _PAGE_ACCESSED aren't set on untouched kernel PTEs. 1290 */ 1291 static inline bool ptep_try_set(pte_t *ptep, pte_t new_pte) 1292 { 1293 pte_t old_pte = __pte(0); 1294 1295 return try_cmpxchg((long *)&ptep->pte, (long *)&old_pte, *(long *)&new_pte); 1296 } 1297 #define ptep_try_set ptep_try_set 1298 1299 #define flush_tlb_fix_spurious_fault(vma, address, ptep) do { } while (0) 1300 1301 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 1302 extern int pmdp_set_access_flags(struct vm_area_struct *vma, 1303 unsigned long address, pmd_t *pmdp, 1304 pmd_t entry, int dirty); 1305 extern int pudp_set_access_flags(struct vm_area_struct *vma, 1306 unsigned long address, pud_t *pudp, 1307 pud_t entry, int dirty); 1308 1309 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 1310 bool pmdp_test_and_clear_young(struct vm_area_struct *vma, 1311 unsigned long addr, pmd_t *pmdp); 1312 bool pudp_test_and_clear_young(struct vm_area_struct *vma, 1313 unsigned long addr, pud_t *pudp); 1314 1315 #define __HAVE_ARCH_PMDP_CLEAR_YOUNG_FLUSH 1316 bool pmdp_clear_flush_young(struct vm_area_struct *vma, 1317 unsigned long address, pmd_t *pmdp); 1318 1319 1320 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 1321 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, unsigned long addr, 1322 pmd_t *pmdp) 1323 { 1324 pmd_t pmd = native_pmdp_get_and_clear(pmdp); 1325 1326 page_table_check_pmd_clear(mm, addr, pmd); 1327 1328 return pmd; 1329 } 1330 1331 #define __HAVE_ARCH_PUDP_HUGE_GET_AND_CLEAR 1332 static inline pud_t pudp_huge_get_and_clear(struct mm_struct *mm, 1333 unsigned long addr, pud_t *pudp) 1334 { 1335 pud_t pud = native_pudp_get_and_clear(pudp); 1336 1337 page_table_check_pud_clear(mm, addr, pud); 1338 1339 return pud; 1340 } 1341 1342 #define __HAVE_ARCH_PMDP_SET_WRPROTECT 1343 static inline void pmdp_set_wrprotect(struct mm_struct *mm, 1344 unsigned long addr, pmd_t *pmdp) 1345 { 1346 /* 1347 * Avoid accidentally creating shadow stack PTEs 1348 * (Write=0,Dirty=1). Use cmpxchg() to prevent races with 1349 * the hardware setting Dirty=1. 1350 */ 1351 pmd_t old_pmd, new_pmd; 1352 1353 old_pmd = READ_ONCE(*pmdp); 1354 do { 1355 new_pmd = pmd_wrprotect(old_pmd); 1356 } while (!try_cmpxchg((long *)pmdp, (long *)&old_pmd, *(long *)&new_pmd)); 1357 } 1358 1359 #ifndef pmdp_establish 1360 #define pmdp_establish pmdp_establish 1361 static inline pmd_t pmdp_establish(struct vm_area_struct *vma, 1362 unsigned long address, pmd_t *pmdp, pmd_t pmd) 1363 { 1364 page_table_check_pmd_set(vma->vm_mm, address, pmdp, pmd); 1365 if (IS_ENABLED(CONFIG_SMP)) { 1366 return xchg(pmdp, pmd); 1367 } else { 1368 pmd_t old = *pmdp; 1369 WRITE_ONCE(*pmdp, pmd); 1370 return old; 1371 } 1372 } 1373 #endif 1374 1375 #ifdef CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD 1376 static inline pud_t pudp_establish(struct vm_area_struct *vma, 1377 unsigned long address, pud_t *pudp, pud_t pud) 1378 { 1379 page_table_check_pud_set(vma->vm_mm, address, pudp, pud); 1380 if (IS_ENABLED(CONFIG_SMP)) { 1381 return xchg(pudp, pud); 1382 } else { 1383 pud_t old = *pudp; 1384 WRITE_ONCE(*pudp, pud); 1385 return old; 1386 } 1387 } 1388 #endif 1389 1390 #define __HAVE_ARCH_PMDP_INVALIDATE_AD 1391 extern pmd_t pmdp_invalidate_ad(struct vm_area_struct *vma, 1392 unsigned long address, pmd_t *pmdp); 1393 1394 pud_t pudp_invalidate(struct vm_area_struct *vma, unsigned long address, 1395 pud_t *pudp); 1396 1397 /* 1398 * Page table pages are page-aligned. The lower half of the top 1399 * level is used for userspace and the top half for the kernel. 1400 * 1401 * Returns true for parts of the PGD that map userspace and 1402 * false for the parts that map the kernel. 1403 */ 1404 static inline bool pgdp_maps_userspace(void *__ptr) 1405 { 1406 unsigned long ptr = (unsigned long)__ptr; 1407 1408 return (((ptr & ~PAGE_MASK) / sizeof(pgd_t)) < PGD_KERNEL_START); 1409 } 1410 1411 #ifdef CONFIG_MITIGATION_PAGE_TABLE_ISOLATION 1412 /* 1413 * All top-level MITIGATION_PAGE_TABLE_ISOLATION page tables are order-1 pages 1414 * (8k-aligned and 8k in size). The kernel one is at the beginning 4k and 1415 * the user one is in the last 4k. To switch between them, you 1416 * just need to flip the 12th bit in their addresses. 1417 */ 1418 #define PTI_PGTABLE_SWITCH_BIT PAGE_SHIFT 1419 1420 /* 1421 * This generates better code than the inline assembly in 1422 * __set_bit(). 1423 */ 1424 static inline void *ptr_set_bit(void *ptr, int bit) 1425 { 1426 unsigned long __ptr = (unsigned long)ptr; 1427 1428 __ptr |= BIT(bit); 1429 return (void *)__ptr; 1430 } 1431 static inline void *ptr_clear_bit(void *ptr, int bit) 1432 { 1433 unsigned long __ptr = (unsigned long)ptr; 1434 1435 __ptr &= ~BIT(bit); 1436 return (void *)__ptr; 1437 } 1438 1439 static inline pgd_t *kernel_to_user_pgdp(pgd_t *pgdp) 1440 { 1441 return ptr_set_bit(pgdp, PTI_PGTABLE_SWITCH_BIT); 1442 } 1443 1444 static inline pgd_t *user_to_kernel_pgdp(pgd_t *pgdp) 1445 { 1446 return ptr_clear_bit(pgdp, PTI_PGTABLE_SWITCH_BIT); 1447 } 1448 1449 static inline p4d_t *kernel_to_user_p4dp(p4d_t *p4dp) 1450 { 1451 return ptr_set_bit(p4dp, PTI_PGTABLE_SWITCH_BIT); 1452 } 1453 1454 static inline p4d_t *user_to_kernel_p4dp(p4d_t *p4dp) 1455 { 1456 return ptr_clear_bit(p4dp, PTI_PGTABLE_SWITCH_BIT); 1457 } 1458 #endif /* CONFIG_MITIGATION_PAGE_TABLE_ISOLATION */ 1459 1460 /* 1461 * clone_pgd_range(pgd_t *dst, pgd_t *src, int count); 1462 * 1463 * dst - pointer to pgd range anywhere on a pgd page 1464 * src - "" 1465 * count - the number of pgds to copy. 1466 * 1467 * dst and src can be on the same page, but the range must not overlap, 1468 * and must not cross a page boundary. 1469 */ 1470 static inline void clone_pgd_range(pgd_t *dst, pgd_t *src, int count) 1471 { 1472 memcpy(dst, src, count * sizeof(pgd_t)); 1473 #ifdef CONFIG_MITIGATION_PAGE_TABLE_ISOLATION 1474 if (!static_cpu_has(X86_FEATURE_PTI)) 1475 return; 1476 /* Clone the user space pgd as well */ 1477 memcpy(kernel_to_user_pgdp(dst), kernel_to_user_pgdp(src), 1478 count * sizeof(pgd_t)); 1479 #endif 1480 } 1481 1482 #define PTE_SHIFT ilog2(PTRS_PER_PTE) 1483 static inline int page_level_shift(enum pg_level level) 1484 { 1485 return (PAGE_SHIFT - PTE_SHIFT) + level * PTE_SHIFT; 1486 } 1487 static inline unsigned long page_level_size(enum pg_level level) 1488 { 1489 return 1UL << page_level_shift(level); 1490 } 1491 static inline unsigned long page_level_mask(enum pg_level level) 1492 { 1493 return ~(page_level_size(level) - 1); 1494 } 1495 1496 /* 1497 * The x86 doesn't have any external MMU info: the kernel page 1498 * tables contain all the necessary information. 1499 */ 1500 static inline void update_mmu_cache(struct vm_area_struct *vma, 1501 unsigned long addr, pte_t *ptep) 1502 { 1503 } 1504 static inline void update_mmu_cache_range(struct vm_fault *vmf, 1505 struct vm_area_struct *vma, unsigned long addr, 1506 pte_t *ptep, unsigned int nr) 1507 { 1508 } 1509 static inline void update_mmu_cache_pmd(struct vm_area_struct *vma, 1510 unsigned long addr, pmd_t *pmd) 1511 { 1512 } 1513 static inline void update_mmu_cache_pud(struct vm_area_struct *vma, 1514 unsigned long addr, pud_t *pud) 1515 { 1516 } 1517 static inline pte_t pte_swp_mkexclusive(pte_t pte) 1518 { 1519 return pte_set_flags(pte, _PAGE_SWP_EXCLUSIVE); 1520 } 1521 1522 static inline bool pte_swp_exclusive(pte_t pte) 1523 { 1524 return pte_flags(pte) & _PAGE_SWP_EXCLUSIVE; 1525 } 1526 1527 static inline pte_t pte_swp_clear_exclusive(pte_t pte) 1528 { 1529 return pte_clear_flags(pte, _PAGE_SWP_EXCLUSIVE); 1530 } 1531 1532 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 1533 static inline pte_t pte_swp_mksoft_dirty(pte_t pte) 1534 { 1535 return pte_set_flags(pte, _PAGE_SWP_SOFT_DIRTY); 1536 } 1537 1538 static inline int pte_swp_soft_dirty(pte_t pte) 1539 { 1540 return pte_flags(pte) & _PAGE_SWP_SOFT_DIRTY; 1541 } 1542 1543 static inline pte_t pte_swp_clear_soft_dirty(pte_t pte) 1544 { 1545 return pte_clear_flags(pte, _PAGE_SWP_SOFT_DIRTY); 1546 } 1547 1548 #ifdef CONFIG_ARCH_ENABLE_THP_MIGRATION 1549 static inline pmd_t pmd_swp_mksoft_dirty(pmd_t pmd) 1550 { 1551 return pmd_set_flags(pmd, _PAGE_SWP_SOFT_DIRTY); 1552 } 1553 1554 static inline int pmd_swp_soft_dirty(pmd_t pmd) 1555 { 1556 return pmd_flags(pmd) & _PAGE_SWP_SOFT_DIRTY; 1557 } 1558 1559 static inline pmd_t pmd_swp_clear_soft_dirty(pmd_t pmd) 1560 { 1561 return pmd_clear_flags(pmd, _PAGE_SWP_SOFT_DIRTY); 1562 } 1563 #endif 1564 #endif 1565 1566 #ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP 1567 static inline pte_t pte_swp_mkuffd_wp(pte_t pte) 1568 { 1569 return pte_set_flags(pte, _PAGE_SWP_UFFD_WP); 1570 } 1571 1572 static inline int pte_swp_uffd_wp(pte_t pte) 1573 { 1574 return pte_flags(pte) & _PAGE_SWP_UFFD_WP; 1575 } 1576 1577 static inline pte_t pte_swp_clear_uffd_wp(pte_t pte) 1578 { 1579 return pte_clear_flags(pte, _PAGE_SWP_UFFD_WP); 1580 } 1581 1582 static inline pmd_t pmd_swp_mkuffd_wp(pmd_t pmd) 1583 { 1584 return pmd_set_flags(pmd, _PAGE_SWP_UFFD_WP); 1585 } 1586 1587 static inline int pmd_swp_uffd_wp(pmd_t pmd) 1588 { 1589 return pmd_flags(pmd) & _PAGE_SWP_UFFD_WP; 1590 } 1591 1592 static inline pmd_t pmd_swp_clear_uffd_wp(pmd_t pmd) 1593 { 1594 return pmd_clear_flags(pmd, _PAGE_SWP_UFFD_WP); 1595 } 1596 #endif /* CONFIG_HAVE_ARCH_USERFAULTFD_WP */ 1597 1598 static inline u16 pte_flags_pkey(unsigned long pte_flags) 1599 { 1600 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS 1601 /* ifdef to avoid doing 59-bit shift on 32-bit values */ 1602 return (pte_flags & _PAGE_PKEY_MASK) >> _PAGE_BIT_PKEY_BIT0; 1603 #else 1604 return 0; 1605 #endif 1606 } 1607 1608 static inline bool __pkru_allows_pkey(u16 pkey, bool write) 1609 { 1610 u32 pkru = read_pkru(); 1611 1612 if (!__pkru_allows_read(pkru, pkey)) 1613 return false; 1614 if (write && !__pkru_allows_write(pkru, pkey)) 1615 return false; 1616 1617 return true; 1618 } 1619 1620 /* 1621 * 'pteval' can come from a PTE, PMD or PUD. We only check 1622 * _PAGE_PRESENT, _PAGE_USER, and _PAGE_RW in here which are the 1623 * same value on all 3 types. 1624 */ 1625 static inline bool __pte_access_permitted(unsigned long pteval, bool write) 1626 { 1627 unsigned long need_pte_bits = _PAGE_PRESENT|_PAGE_USER; 1628 1629 /* 1630 * Write=0,Dirty=1 PTEs are shadow stack, which the kernel 1631 * shouldn't generally allow access to, but since they 1632 * are already Write=0, the below logic covers both cases. 1633 */ 1634 if (write) 1635 need_pte_bits |= _PAGE_RW; 1636 1637 if ((pteval & need_pte_bits) != need_pte_bits) 1638 return 0; 1639 1640 return __pkru_allows_pkey(pte_flags_pkey(pteval), write); 1641 } 1642 1643 #define pte_access_permitted pte_access_permitted 1644 static inline bool pte_access_permitted(pte_t pte, bool write) 1645 { 1646 return __pte_access_permitted(pte_val(pte), write); 1647 } 1648 1649 #define pmd_access_permitted pmd_access_permitted 1650 static inline bool pmd_access_permitted(pmd_t pmd, bool write) 1651 { 1652 return __pte_access_permitted(pmd_val(pmd), write); 1653 } 1654 1655 #define pud_access_permitted pud_access_permitted 1656 static inline bool pud_access_permitted(pud_t pud, bool write) 1657 { 1658 return __pte_access_permitted(pud_val(pud), write); 1659 } 1660 1661 #define __HAVE_ARCH_PFN_MODIFY_ALLOWED 1 1662 extern bool pfn_modify_allowed(unsigned long pfn, pgprot_t prot); 1663 1664 static inline bool arch_has_pfn_modify_check(void) 1665 { 1666 return boot_cpu_has_bug(X86_BUG_L1TF); 1667 } 1668 1669 #define arch_check_zapped_pte arch_check_zapped_pte 1670 void arch_check_zapped_pte(struct vm_area_struct *vma, pte_t pte); 1671 1672 #define arch_check_zapped_pmd arch_check_zapped_pmd 1673 void arch_check_zapped_pmd(struct vm_area_struct *vma, pmd_t pmd); 1674 1675 #define arch_check_zapped_pud arch_check_zapped_pud 1676 void arch_check_zapped_pud(struct vm_area_struct *vma, pud_t pud); 1677 1678 #ifdef CONFIG_XEN_PV 1679 #define arch_has_hw_nonleaf_pmd_young arch_has_hw_nonleaf_pmd_young 1680 static inline bool arch_has_hw_nonleaf_pmd_young(void) 1681 { 1682 return !cpu_feature_enabled(X86_FEATURE_XENPV); 1683 } 1684 #endif 1685 1686 #ifdef CONFIG_PAGE_TABLE_CHECK 1687 static inline bool pte_user_accessible_page(struct mm_struct *mm, unsigned long addr, pte_t pte) 1688 { 1689 return (pte_val(pte) & _PAGE_PRESENT) && (pte_val(pte) & _PAGE_USER); 1690 } 1691 1692 static inline bool pmd_user_accessible_page(struct mm_struct *mm, unsigned long addr, pmd_t pmd) 1693 { 1694 return pmd_leaf(pmd) && (pmd_val(pmd) & _PAGE_PRESENT) && (pmd_val(pmd) & _PAGE_USER); 1695 } 1696 1697 static inline bool pud_user_accessible_page(struct mm_struct *mm, unsigned long addr, pud_t pud) 1698 { 1699 return pud_leaf(pud) && (pud_val(pud) & _PAGE_PRESENT) && (pud_val(pud) & _PAGE_USER); 1700 } 1701 #endif 1702 1703 #ifdef CONFIG_X86_SGX 1704 int arch_memory_failure(unsigned long pfn, int flags); 1705 #define arch_memory_failure arch_memory_failure 1706 1707 bool arch_is_platform_page(u64 paddr); 1708 #define arch_is_platform_page arch_is_platform_page 1709 #endif 1710 1711 /* 1712 * Use set_p*_safe(), and elide TLB flushing, when confident that *no* 1713 * TLB flush will be required as a result of the "set". For example, use 1714 * in scenarios where it is known ahead of time that the routine is 1715 * setting non-present entries, or re-setting an existing entry to the 1716 * same value. Otherwise, use the typical "set" helpers and flush the 1717 * TLB. 1718 */ 1719 #define set_pte_safe(ptep, pte) \ 1720 ({ \ 1721 WARN_ON_ONCE(pte_present(*ptep) && !pte_same(*ptep, pte)); \ 1722 set_pte(ptep, pte); \ 1723 }) 1724 1725 #define set_pmd_safe(pmdp, pmd) \ 1726 ({ \ 1727 WARN_ON_ONCE(pmd_present(*pmdp) && !pmd_same(*pmdp, pmd)); \ 1728 set_pmd(pmdp, pmd); \ 1729 }) 1730 1731 #define set_pud_safe(pudp, pud) \ 1732 ({ \ 1733 WARN_ON_ONCE(pud_present(*pudp) && !pud_same(*pudp, pud)); \ 1734 set_pud(pudp, pud); \ 1735 }) 1736 1737 #define set_p4d_safe(p4dp, p4d) \ 1738 ({ \ 1739 WARN_ON_ONCE(p4d_present(*p4dp) && !p4d_same(*p4dp, p4d)); \ 1740 set_p4d(p4dp, p4d); \ 1741 }) 1742 1743 #define set_pgd_safe(pgdp, pgd) \ 1744 ({ \ 1745 WARN_ON_ONCE(pgd_present(*pgdp) && !pgd_same(*pgdp, pgd)); \ 1746 set_pgd(pgdp, pgd); \ 1747 }) 1748 #endif /* __ASSEMBLER__ */ 1749 1750 #endif /* _ASM_X86_PGTABLE_H */ 1751