1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _ASM_X86_PGTABLE_H 3 #define _ASM_X86_PGTABLE_H 4 5 #include <linux/mem_encrypt.h> 6 #include <asm/page.h> 7 #include <asm/pgtable_types.h> 8 9 /* 10 * Macro to mark a page protection value as UC- 11 */ 12 #define pgprot_noncached(prot) \ 13 ((boot_cpu_data.x86 > 3) \ 14 ? (__pgprot(pgprot_val(prot) | \ 15 cachemode2protval(_PAGE_CACHE_MODE_UC_MINUS))) \ 16 : (prot)) 17 18 #ifndef __ASSEMBLER__ 19 #include <linux/spinlock.h> 20 #include <asm/x86_init.h> 21 #include <asm/pkru.h> 22 #include <asm/fpu/api.h> 23 #include <asm/coco.h> 24 #include <asm-generic/pgtable_uffd.h> 25 #include <linux/page_table_check.h> 26 27 extern pgd_t early_top_pgt[PTRS_PER_PGD]; 28 bool __init __early_make_pgtable(unsigned long address, pmdval_t pmd); 29 30 struct seq_file; 31 void ptdump_walk_pgd_level(struct seq_file *m, struct mm_struct *mm); 32 void ptdump_walk_pgd_level_debugfs(struct seq_file *m, struct mm_struct *mm, 33 bool user); 34 bool ptdump_walk_pgd_level_checkwx(void); 35 #define ptdump_check_wx ptdump_walk_pgd_level_checkwx 36 void ptdump_walk_user_pgd_level_checkwx(void); 37 38 /* 39 * Macros to add or remove encryption attribute 40 */ 41 #define pgprot_encrypted(prot) __pgprot(cc_mkenc(pgprot_val(prot))) 42 #define pgprot_decrypted(prot) __pgprot(cc_mkdec(pgprot_val(prot))) 43 44 #ifdef CONFIG_DEBUG_WX 45 #define debug_checkwx_user() ptdump_walk_user_pgd_level_checkwx() 46 #else 47 #define debug_checkwx_user() do { } while (0) 48 #endif 49 50 /* 51 * ZERO_PAGE is a global shared page that is always zero: used 52 * for zero-mapped memory areas etc.. 53 */ 54 extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)] 55 __visible; 56 #define ZERO_PAGE(vaddr) ((void)(vaddr),virt_to_page(empty_zero_page)) 57 58 extern spinlock_t pgd_lock; 59 extern struct list_head pgd_list; 60 61 extern struct mm_struct *pgd_page_get_mm(struct page *page); 62 63 extern pmdval_t early_pmd_flags; 64 65 #ifdef CONFIG_PARAVIRT_XXL 66 #include <asm/paravirt.h> 67 #else /* !CONFIG_PARAVIRT_XXL */ 68 #define set_pte(ptep, pte) native_set_pte(ptep, pte) 69 70 #define set_pte_atomic(ptep, pte) \ 71 native_set_pte_atomic(ptep, pte) 72 73 #define set_pmd(pmdp, pmd) native_set_pmd(pmdp, pmd) 74 75 #ifndef __PAGETABLE_P4D_FOLDED 76 #define set_pgd(pgdp, pgd) native_set_pgd(pgdp, pgd) 77 #define pgd_clear(pgd) (pgtable_l5_enabled() ? native_pgd_clear(pgd) : 0) 78 #endif 79 80 #ifndef set_p4d 81 # define set_p4d(p4dp, p4d) native_set_p4d(p4dp, p4d) 82 #endif 83 84 #ifndef __PAGETABLE_PUD_FOLDED 85 #define p4d_clear(p4d) native_p4d_clear(p4d) 86 #endif 87 88 #ifndef set_pud 89 # define set_pud(pudp, pud) native_set_pud(pudp, pud) 90 #endif 91 92 #ifndef __PAGETABLE_PUD_FOLDED 93 #define pud_clear(pud) native_pud_clear(pud) 94 #endif 95 96 #define pte_clear(mm, addr, ptep) native_pte_clear(mm, addr, ptep) 97 #define pmd_clear(pmd) native_pmd_clear(pmd) 98 99 #define pgd_val(x) native_pgd_val(x) 100 #define __pgd(x) native_make_pgd(x) 101 102 #ifndef __PAGETABLE_P4D_FOLDED 103 #define p4d_val(x) native_p4d_val(x) 104 #define __p4d(x) native_make_p4d(x) 105 #endif 106 107 #ifndef __PAGETABLE_PUD_FOLDED 108 #define pud_val(x) native_pud_val(x) 109 #define __pud(x) native_make_pud(x) 110 #endif 111 112 #ifndef __PAGETABLE_PMD_FOLDED 113 #define pmd_val(x) native_pmd_val(x) 114 #define __pmd(x) native_make_pmd(x) 115 #endif 116 117 #define pte_val(x) native_pte_val(x) 118 #define __pte(x) native_make_pte(x) 119 120 #define arch_end_context_switch(prev) do {} while(0) 121 #endif /* CONFIG_PARAVIRT_XXL */ 122 123 static inline pmd_t pmd_set_flags(pmd_t pmd, pmdval_t set) 124 { 125 pmdval_t v = native_pmd_val(pmd); 126 127 return native_make_pmd(v | set); 128 } 129 130 static inline pmd_t pmd_clear_flags(pmd_t pmd, pmdval_t clear) 131 { 132 pmdval_t v = native_pmd_val(pmd); 133 134 return native_make_pmd(v & ~clear); 135 } 136 137 static inline pud_t pud_set_flags(pud_t pud, pudval_t set) 138 { 139 pudval_t v = native_pud_val(pud); 140 141 return native_make_pud(v | set); 142 } 143 144 static inline pud_t pud_clear_flags(pud_t pud, pudval_t clear) 145 { 146 pudval_t v = native_pud_val(pud); 147 148 return native_make_pud(v & ~clear); 149 } 150 151 /* 152 * The following only work if pte_present() is true. 153 * Undefined behaviour if not.. 154 */ 155 static inline bool pte_dirty(pte_t pte) 156 { 157 return pte_flags(pte) & _PAGE_DIRTY_BITS; 158 } 159 160 static inline bool pte_shstk(pte_t pte) 161 { 162 return cpu_feature_enabled(X86_FEATURE_SHSTK) && 163 (pte_flags(pte) & (_PAGE_RW | _PAGE_DIRTY)) == _PAGE_DIRTY; 164 } 165 166 static inline int pte_young(pte_t pte) 167 { 168 return pte_flags(pte) & _PAGE_ACCESSED; 169 } 170 171 static inline bool pte_decrypted(pte_t pte) 172 { 173 return cc_mkdec(pte_val(pte)) == pte_val(pte); 174 } 175 176 #define pmd_dirty pmd_dirty 177 static inline bool pmd_dirty(pmd_t pmd) 178 { 179 return pmd_flags(pmd) & _PAGE_DIRTY_BITS; 180 } 181 182 static inline bool pmd_shstk(pmd_t pmd) 183 { 184 return cpu_feature_enabled(X86_FEATURE_SHSTK) && 185 (pmd_flags(pmd) & (_PAGE_RW | _PAGE_DIRTY | _PAGE_PSE)) == 186 (_PAGE_DIRTY | _PAGE_PSE); 187 } 188 189 #define pmd_young pmd_young 190 static inline int pmd_young(pmd_t pmd) 191 { 192 return pmd_flags(pmd) & _PAGE_ACCESSED; 193 } 194 195 static inline bool pud_dirty(pud_t pud) 196 { 197 return pud_flags(pud) & _PAGE_DIRTY_BITS; 198 } 199 200 static inline int pud_young(pud_t pud) 201 { 202 return pud_flags(pud) & _PAGE_ACCESSED; 203 } 204 205 static inline bool pud_shstk(pud_t pud) 206 { 207 return cpu_feature_enabled(X86_FEATURE_SHSTK) && 208 (pud_flags(pud) & (_PAGE_RW | _PAGE_DIRTY | _PAGE_PSE)) == 209 (_PAGE_DIRTY | _PAGE_PSE); 210 } 211 212 static inline int pte_write(pte_t pte) 213 { 214 /* 215 * Shadow stack pages are logically writable, but do not have 216 * _PAGE_RW. Check for them separately from _PAGE_RW itself. 217 */ 218 return (pte_flags(pte) & _PAGE_RW) || pte_shstk(pte); 219 } 220 221 #define pmd_write pmd_write 222 static inline int pmd_write(pmd_t pmd) 223 { 224 /* 225 * Shadow stack pages are logically writable, but do not have 226 * _PAGE_RW. Check for them separately from _PAGE_RW itself. 227 */ 228 return (pmd_flags(pmd) & _PAGE_RW) || pmd_shstk(pmd); 229 } 230 231 #define pud_write pud_write 232 static inline int pud_write(pud_t pud) 233 { 234 return pud_flags(pud) & _PAGE_RW; 235 } 236 237 static inline int pte_huge(pte_t pte) 238 { 239 return pte_flags(pte) & _PAGE_PSE; 240 } 241 242 static inline int pte_global(pte_t pte) 243 { 244 return pte_flags(pte) & _PAGE_GLOBAL; 245 } 246 247 static inline int pte_exec(pte_t pte) 248 { 249 return !(pte_flags(pte) & _PAGE_NX); 250 } 251 252 static inline int pte_special(pte_t pte) 253 { 254 return pte_flags(pte) & _PAGE_SPECIAL; 255 } 256 257 /* Entries that were set to PROT_NONE are inverted */ 258 259 static inline u64 protnone_mask(u64 val); 260 261 #define PFN_PTE_SHIFT PAGE_SHIFT 262 263 static inline unsigned long pte_pfn(pte_t pte) 264 { 265 phys_addr_t pfn = pte_val(pte); 266 pfn ^= protnone_mask(pfn); 267 return (pfn & PTE_PFN_MASK) >> PAGE_SHIFT; 268 } 269 270 static inline unsigned long pmd_pfn(pmd_t pmd) 271 { 272 phys_addr_t pfn = pmd_val(pmd); 273 pfn ^= protnone_mask(pfn); 274 return (pfn & pmd_pfn_mask(pmd)) >> PAGE_SHIFT; 275 } 276 277 #define pud_pfn pud_pfn 278 static inline unsigned long pud_pfn(pud_t pud) 279 { 280 phys_addr_t pfn = pud_val(pud); 281 pfn ^= protnone_mask(pfn); 282 return (pfn & pud_pfn_mask(pud)) >> PAGE_SHIFT; 283 } 284 285 static inline unsigned long p4d_pfn(p4d_t p4d) 286 { 287 return (p4d_val(p4d) & p4d_pfn_mask(p4d)) >> PAGE_SHIFT; 288 } 289 290 static inline unsigned long pgd_pfn(pgd_t pgd) 291 { 292 return (pgd_val(pgd) & PTE_PFN_MASK) >> PAGE_SHIFT; 293 } 294 295 #define pte_page(pte) pfn_to_page(pte_pfn(pte)) 296 297 #define pmd_leaf pmd_leaf 298 static inline bool pmd_leaf(pmd_t pte) 299 { 300 return pmd_flags(pte) & _PAGE_PSE; 301 } 302 303 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 304 /* NOTE: when predicate huge page, consider also pmd_devmap, or use pmd_leaf */ 305 static inline int pmd_trans_huge(pmd_t pmd) 306 { 307 return (pmd_val(pmd) & (_PAGE_PSE|_PAGE_DEVMAP)) == _PAGE_PSE; 308 } 309 310 #ifdef CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD 311 static inline int pud_trans_huge(pud_t pud) 312 { 313 return (pud_val(pud) & (_PAGE_PSE|_PAGE_DEVMAP)) == _PAGE_PSE; 314 } 315 #endif 316 317 #define has_transparent_hugepage has_transparent_hugepage 318 static inline int has_transparent_hugepage(void) 319 { 320 return boot_cpu_has(X86_FEATURE_PSE); 321 } 322 323 #ifdef CONFIG_ARCH_HAS_PTE_DEVMAP 324 static inline int pmd_devmap(pmd_t pmd) 325 { 326 return !!(pmd_val(pmd) & _PAGE_DEVMAP); 327 } 328 329 #ifdef CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD 330 static inline int pud_devmap(pud_t pud) 331 { 332 return !!(pud_val(pud) & _PAGE_DEVMAP); 333 } 334 #else 335 static inline int pud_devmap(pud_t pud) 336 { 337 return 0; 338 } 339 #endif 340 341 #ifdef CONFIG_ARCH_SUPPORTS_PMD_PFNMAP 342 static inline bool pmd_special(pmd_t pmd) 343 { 344 return pmd_flags(pmd) & _PAGE_SPECIAL; 345 } 346 347 static inline pmd_t pmd_mkspecial(pmd_t pmd) 348 { 349 return pmd_set_flags(pmd, _PAGE_SPECIAL); 350 } 351 #endif /* CONFIG_ARCH_SUPPORTS_PMD_PFNMAP */ 352 353 #ifdef CONFIG_ARCH_SUPPORTS_PUD_PFNMAP 354 static inline bool pud_special(pud_t pud) 355 { 356 return pud_flags(pud) & _PAGE_SPECIAL; 357 } 358 359 static inline pud_t pud_mkspecial(pud_t pud) 360 { 361 return pud_set_flags(pud, _PAGE_SPECIAL); 362 } 363 #endif /* CONFIG_ARCH_SUPPORTS_PUD_PFNMAP */ 364 365 static inline int pgd_devmap(pgd_t pgd) 366 { 367 return 0; 368 } 369 #endif 370 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 371 372 static inline pte_t pte_set_flags(pte_t pte, pteval_t set) 373 { 374 pteval_t v = native_pte_val(pte); 375 376 return native_make_pte(v | set); 377 } 378 379 static inline pte_t pte_clear_flags(pte_t pte, pteval_t clear) 380 { 381 pteval_t v = native_pte_val(pte); 382 383 return native_make_pte(v & ~clear); 384 } 385 386 /* 387 * Write protection operations can result in Dirty=1,Write=0 PTEs. But in the 388 * case of X86_FEATURE_USER_SHSTK, these PTEs denote shadow stack memory. So 389 * when creating dirty, write-protected memory, a software bit is used: 390 * _PAGE_BIT_SAVED_DIRTY. The following functions take a PTE and transition the 391 * Dirty bit to SavedDirty, and vice-vesra. 392 * 393 * This shifting is only done if needed. In the case of shifting 394 * Dirty->SavedDirty, the condition is if the PTE is Write=0. In the case of 395 * shifting SavedDirty->Dirty, the condition is Write=1. 396 */ 397 static inline pgprotval_t mksaveddirty_shift(pgprotval_t v) 398 { 399 pgprotval_t cond = (~v >> _PAGE_BIT_RW) & 1; 400 401 v |= ((v >> _PAGE_BIT_DIRTY) & cond) << _PAGE_BIT_SAVED_DIRTY; 402 v &= ~(cond << _PAGE_BIT_DIRTY); 403 404 return v; 405 } 406 407 static inline pgprotval_t clear_saveddirty_shift(pgprotval_t v) 408 { 409 pgprotval_t cond = (v >> _PAGE_BIT_RW) & 1; 410 411 v |= ((v >> _PAGE_BIT_SAVED_DIRTY) & cond) << _PAGE_BIT_DIRTY; 412 v &= ~(cond << _PAGE_BIT_SAVED_DIRTY); 413 414 return v; 415 } 416 417 static inline pte_t pte_mksaveddirty(pte_t pte) 418 { 419 pteval_t v = native_pte_val(pte); 420 421 v = mksaveddirty_shift(v); 422 return native_make_pte(v); 423 } 424 425 static inline pte_t pte_clear_saveddirty(pte_t pte) 426 { 427 pteval_t v = native_pte_val(pte); 428 429 v = clear_saveddirty_shift(v); 430 return native_make_pte(v); 431 } 432 433 static inline pte_t pte_wrprotect(pte_t pte) 434 { 435 pte = pte_clear_flags(pte, _PAGE_RW); 436 437 /* 438 * Blindly clearing _PAGE_RW might accidentally create 439 * a shadow stack PTE (Write=0,Dirty=1). Move the hardware 440 * dirty value to the software bit, if present. 441 */ 442 return pte_mksaveddirty(pte); 443 } 444 445 #ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP 446 static inline int pte_uffd_wp(pte_t pte) 447 { 448 return pte_flags(pte) & _PAGE_UFFD_WP; 449 } 450 451 static inline pte_t pte_mkuffd_wp(pte_t pte) 452 { 453 return pte_wrprotect(pte_set_flags(pte, _PAGE_UFFD_WP)); 454 } 455 456 static inline pte_t pte_clear_uffd_wp(pte_t pte) 457 { 458 return pte_clear_flags(pte, _PAGE_UFFD_WP); 459 } 460 #endif /* CONFIG_HAVE_ARCH_USERFAULTFD_WP */ 461 462 static inline pte_t pte_mkclean(pte_t pte) 463 { 464 return pte_clear_flags(pte, _PAGE_DIRTY_BITS); 465 } 466 467 static inline pte_t pte_mkold(pte_t pte) 468 { 469 return pte_clear_flags(pte, _PAGE_ACCESSED); 470 } 471 472 static inline pte_t pte_mkexec(pte_t pte) 473 { 474 return pte_clear_flags(pte, _PAGE_NX); 475 } 476 477 static inline pte_t pte_mkdirty(pte_t pte) 478 { 479 pte = pte_set_flags(pte, _PAGE_DIRTY | _PAGE_SOFT_DIRTY); 480 481 return pte_mksaveddirty(pte); 482 } 483 484 static inline pte_t pte_mkwrite_shstk(pte_t pte) 485 { 486 pte = pte_clear_flags(pte, _PAGE_RW); 487 488 return pte_set_flags(pte, _PAGE_DIRTY); 489 } 490 491 static inline pte_t pte_mkyoung(pte_t pte) 492 { 493 return pte_set_flags(pte, _PAGE_ACCESSED); 494 } 495 496 static inline pte_t pte_mkwrite_novma(pte_t pte) 497 { 498 return pte_set_flags(pte, _PAGE_RW); 499 } 500 501 struct vm_area_struct; 502 pte_t pte_mkwrite(pte_t pte, struct vm_area_struct *vma); 503 #define pte_mkwrite pte_mkwrite 504 505 static inline pte_t pte_mkhuge(pte_t pte) 506 { 507 return pte_set_flags(pte, _PAGE_PSE); 508 } 509 510 static inline pte_t pte_clrhuge(pte_t pte) 511 { 512 return pte_clear_flags(pte, _PAGE_PSE); 513 } 514 515 static inline pte_t pte_mkglobal(pte_t pte) 516 { 517 return pte_set_flags(pte, _PAGE_GLOBAL); 518 } 519 520 static inline pte_t pte_clrglobal(pte_t pte) 521 { 522 return pte_clear_flags(pte, _PAGE_GLOBAL); 523 } 524 525 static inline pte_t pte_mkspecial(pte_t pte) 526 { 527 return pte_set_flags(pte, _PAGE_SPECIAL); 528 } 529 530 static inline pte_t pte_mkdevmap(pte_t pte) 531 { 532 return pte_set_flags(pte, _PAGE_SPECIAL|_PAGE_DEVMAP); 533 } 534 535 /* See comments above mksaveddirty_shift() */ 536 static inline pmd_t pmd_mksaveddirty(pmd_t pmd) 537 { 538 pmdval_t v = native_pmd_val(pmd); 539 540 v = mksaveddirty_shift(v); 541 return native_make_pmd(v); 542 } 543 544 /* See comments above mksaveddirty_shift() */ 545 static inline pmd_t pmd_clear_saveddirty(pmd_t pmd) 546 { 547 pmdval_t v = native_pmd_val(pmd); 548 549 v = clear_saveddirty_shift(v); 550 return native_make_pmd(v); 551 } 552 553 static inline pmd_t pmd_wrprotect(pmd_t pmd) 554 { 555 pmd = pmd_clear_flags(pmd, _PAGE_RW); 556 557 /* 558 * Blindly clearing _PAGE_RW might accidentally create 559 * a shadow stack PMD (RW=0, Dirty=1). Move the hardware 560 * dirty value to the software bit. 561 */ 562 return pmd_mksaveddirty(pmd); 563 } 564 565 #ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP 566 static inline int pmd_uffd_wp(pmd_t pmd) 567 { 568 return pmd_flags(pmd) & _PAGE_UFFD_WP; 569 } 570 571 static inline pmd_t pmd_mkuffd_wp(pmd_t pmd) 572 { 573 return pmd_wrprotect(pmd_set_flags(pmd, _PAGE_UFFD_WP)); 574 } 575 576 static inline pmd_t pmd_clear_uffd_wp(pmd_t pmd) 577 { 578 return pmd_clear_flags(pmd, _PAGE_UFFD_WP); 579 } 580 #endif /* CONFIG_HAVE_ARCH_USERFAULTFD_WP */ 581 582 static inline pmd_t pmd_mkold(pmd_t pmd) 583 { 584 return pmd_clear_flags(pmd, _PAGE_ACCESSED); 585 } 586 587 static inline pmd_t pmd_mkclean(pmd_t pmd) 588 { 589 return pmd_clear_flags(pmd, _PAGE_DIRTY_BITS); 590 } 591 592 static inline pmd_t pmd_mkdirty(pmd_t pmd) 593 { 594 pmd = pmd_set_flags(pmd, _PAGE_DIRTY | _PAGE_SOFT_DIRTY); 595 596 return pmd_mksaveddirty(pmd); 597 } 598 599 static inline pmd_t pmd_mkwrite_shstk(pmd_t pmd) 600 { 601 pmd = pmd_clear_flags(pmd, _PAGE_RW); 602 603 return pmd_set_flags(pmd, _PAGE_DIRTY); 604 } 605 606 static inline pmd_t pmd_mkdevmap(pmd_t pmd) 607 { 608 return pmd_set_flags(pmd, _PAGE_DEVMAP); 609 } 610 611 static inline pmd_t pmd_mkhuge(pmd_t pmd) 612 { 613 return pmd_set_flags(pmd, _PAGE_PSE); 614 } 615 616 static inline pmd_t pmd_mkyoung(pmd_t pmd) 617 { 618 return pmd_set_flags(pmd, _PAGE_ACCESSED); 619 } 620 621 static inline pmd_t pmd_mkwrite_novma(pmd_t pmd) 622 { 623 return pmd_set_flags(pmd, _PAGE_RW); 624 } 625 626 pmd_t pmd_mkwrite(pmd_t pmd, struct vm_area_struct *vma); 627 #define pmd_mkwrite pmd_mkwrite 628 629 /* See comments above mksaveddirty_shift() */ 630 static inline pud_t pud_mksaveddirty(pud_t pud) 631 { 632 pudval_t v = native_pud_val(pud); 633 634 v = mksaveddirty_shift(v); 635 return native_make_pud(v); 636 } 637 638 /* See comments above mksaveddirty_shift() */ 639 static inline pud_t pud_clear_saveddirty(pud_t pud) 640 { 641 pudval_t v = native_pud_val(pud); 642 643 v = clear_saveddirty_shift(v); 644 return native_make_pud(v); 645 } 646 647 static inline pud_t pud_mkold(pud_t pud) 648 { 649 return pud_clear_flags(pud, _PAGE_ACCESSED); 650 } 651 652 static inline pud_t pud_mkclean(pud_t pud) 653 { 654 return pud_clear_flags(pud, _PAGE_DIRTY_BITS); 655 } 656 657 static inline pud_t pud_wrprotect(pud_t pud) 658 { 659 pud = pud_clear_flags(pud, _PAGE_RW); 660 661 /* 662 * Blindly clearing _PAGE_RW might accidentally create 663 * a shadow stack PUD (RW=0, Dirty=1). Move the hardware 664 * dirty value to the software bit. 665 */ 666 return pud_mksaveddirty(pud); 667 } 668 669 static inline pud_t pud_mkdirty(pud_t pud) 670 { 671 pud = pud_set_flags(pud, _PAGE_DIRTY | _PAGE_SOFT_DIRTY); 672 673 return pud_mksaveddirty(pud); 674 } 675 676 static inline pud_t pud_mkdevmap(pud_t pud) 677 { 678 return pud_set_flags(pud, _PAGE_DEVMAP); 679 } 680 681 static inline pud_t pud_mkhuge(pud_t pud) 682 { 683 return pud_set_flags(pud, _PAGE_PSE); 684 } 685 686 static inline pud_t pud_mkyoung(pud_t pud) 687 { 688 return pud_set_flags(pud, _PAGE_ACCESSED); 689 } 690 691 static inline pud_t pud_mkwrite(pud_t pud) 692 { 693 pud = pud_set_flags(pud, _PAGE_RW); 694 695 return pud_clear_saveddirty(pud); 696 } 697 698 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 699 static inline int pte_soft_dirty(pte_t pte) 700 { 701 return pte_flags(pte) & _PAGE_SOFT_DIRTY; 702 } 703 704 static inline int pmd_soft_dirty(pmd_t pmd) 705 { 706 return pmd_flags(pmd) & _PAGE_SOFT_DIRTY; 707 } 708 709 static inline int pud_soft_dirty(pud_t pud) 710 { 711 return pud_flags(pud) & _PAGE_SOFT_DIRTY; 712 } 713 714 static inline pte_t pte_mksoft_dirty(pte_t pte) 715 { 716 return pte_set_flags(pte, _PAGE_SOFT_DIRTY); 717 } 718 719 static inline pmd_t pmd_mksoft_dirty(pmd_t pmd) 720 { 721 return pmd_set_flags(pmd, _PAGE_SOFT_DIRTY); 722 } 723 724 static inline pud_t pud_mksoft_dirty(pud_t pud) 725 { 726 return pud_set_flags(pud, _PAGE_SOFT_DIRTY); 727 } 728 729 static inline pte_t pte_clear_soft_dirty(pte_t pte) 730 { 731 return pte_clear_flags(pte, _PAGE_SOFT_DIRTY); 732 } 733 734 static inline pmd_t pmd_clear_soft_dirty(pmd_t pmd) 735 { 736 return pmd_clear_flags(pmd, _PAGE_SOFT_DIRTY); 737 } 738 739 static inline pud_t pud_clear_soft_dirty(pud_t pud) 740 { 741 return pud_clear_flags(pud, _PAGE_SOFT_DIRTY); 742 } 743 744 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ 745 746 /* 747 * Mask out unsupported bits in a present pgprot. Non-present pgprots 748 * can use those bits for other purposes, so leave them be. 749 */ 750 static inline pgprotval_t massage_pgprot(pgprot_t pgprot) 751 { 752 pgprotval_t protval = pgprot_val(pgprot); 753 754 if (protval & _PAGE_PRESENT) 755 protval &= __supported_pte_mask; 756 757 return protval; 758 } 759 760 static inline pgprotval_t check_pgprot(pgprot_t pgprot) 761 { 762 pgprotval_t massaged_val = massage_pgprot(pgprot); 763 764 /* mmdebug.h can not be included here because of dependencies */ 765 #ifdef CONFIG_DEBUG_VM 766 WARN_ONCE(pgprot_val(pgprot) != massaged_val, 767 "attempted to set unsupported pgprot: %016llx " 768 "bits: %016llx supported: %016llx\n", 769 (u64)pgprot_val(pgprot), 770 (u64)pgprot_val(pgprot) ^ massaged_val, 771 (u64)__supported_pte_mask); 772 #endif 773 774 return massaged_val; 775 } 776 777 static inline pte_t pfn_pte(unsigned long page_nr, pgprot_t pgprot) 778 { 779 phys_addr_t pfn = (phys_addr_t)page_nr << PAGE_SHIFT; 780 pfn ^= protnone_mask(pgprot_val(pgprot)); 781 pfn &= PTE_PFN_MASK; 782 return __pte(pfn | check_pgprot(pgprot)); 783 } 784 785 static inline pmd_t pfn_pmd(unsigned long page_nr, pgprot_t pgprot) 786 { 787 phys_addr_t pfn = (phys_addr_t)page_nr << PAGE_SHIFT; 788 pfn ^= protnone_mask(pgprot_val(pgprot)); 789 pfn &= PHYSICAL_PMD_PAGE_MASK; 790 return __pmd(pfn | check_pgprot(pgprot)); 791 } 792 793 static inline pud_t pfn_pud(unsigned long page_nr, pgprot_t pgprot) 794 { 795 phys_addr_t pfn = (phys_addr_t)page_nr << PAGE_SHIFT; 796 pfn ^= protnone_mask(pgprot_val(pgprot)); 797 pfn &= PHYSICAL_PUD_PAGE_MASK; 798 return __pud(pfn | check_pgprot(pgprot)); 799 } 800 801 static inline pmd_t pmd_mkinvalid(pmd_t pmd) 802 { 803 return pfn_pmd(pmd_pfn(pmd), 804 __pgprot(pmd_flags(pmd) & ~(_PAGE_PRESENT|_PAGE_PROTNONE))); 805 } 806 807 static inline pud_t pud_mkinvalid(pud_t pud) 808 { 809 return pfn_pud(pud_pfn(pud), 810 __pgprot(pud_flags(pud) & ~(_PAGE_PRESENT|_PAGE_PROTNONE))); 811 } 812 813 static inline u64 flip_protnone_guard(u64 oldval, u64 val, u64 mask); 814 815 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 816 { 817 pteval_t val = pte_val(pte), oldval = val; 818 pte_t pte_result; 819 820 /* 821 * Chop off the NX bit (if present), and add the NX portion of 822 * the newprot (if present): 823 */ 824 val &= _PAGE_CHG_MASK; 825 val |= check_pgprot(newprot) & ~_PAGE_CHG_MASK; 826 val = flip_protnone_guard(oldval, val, PTE_PFN_MASK); 827 828 pte_result = __pte(val); 829 830 /* 831 * To avoid creating Write=0,Dirty=1 PTEs, pte_modify() needs to avoid: 832 * 1. Marking Write=0 PTEs Dirty=1 833 * 2. Marking Dirty=1 PTEs Write=0 834 * 835 * The first case cannot happen because the _PAGE_CHG_MASK will filter 836 * out any Dirty bit passed in newprot. Handle the second case by 837 * going through the mksaveddirty exercise. Only do this if the old 838 * value was Write=1 to avoid doing this on Shadow Stack PTEs. 839 */ 840 if (oldval & _PAGE_RW) 841 pte_result = pte_mksaveddirty(pte_result); 842 else 843 pte_result = pte_clear_saveddirty(pte_result); 844 845 return pte_result; 846 } 847 848 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) 849 { 850 pmdval_t val = pmd_val(pmd), oldval = val; 851 pmd_t pmd_result; 852 853 val &= (_HPAGE_CHG_MASK & ~_PAGE_DIRTY); 854 val |= check_pgprot(newprot) & ~_HPAGE_CHG_MASK; 855 val = flip_protnone_guard(oldval, val, PHYSICAL_PMD_PAGE_MASK); 856 857 pmd_result = __pmd(val); 858 859 /* 860 * Avoid creating shadow stack PMD by accident. See comment in 861 * pte_modify(). 862 */ 863 if (oldval & _PAGE_RW) 864 pmd_result = pmd_mksaveddirty(pmd_result); 865 else 866 pmd_result = pmd_clear_saveddirty(pmd_result); 867 868 return pmd_result; 869 } 870 871 static inline pud_t pud_modify(pud_t pud, pgprot_t newprot) 872 { 873 pudval_t val = pud_val(pud), oldval = val; 874 pud_t pud_result; 875 876 val &= _HPAGE_CHG_MASK; 877 val |= check_pgprot(newprot) & ~_HPAGE_CHG_MASK; 878 val = flip_protnone_guard(oldval, val, PHYSICAL_PUD_PAGE_MASK); 879 880 pud_result = __pud(val); 881 882 /* 883 * Avoid creating shadow stack PUD by accident. See comment in 884 * pte_modify(). 885 */ 886 if (oldval & _PAGE_RW) 887 pud_result = pud_mksaveddirty(pud_result); 888 else 889 pud_result = pud_clear_saveddirty(pud_result); 890 891 return pud_result; 892 } 893 894 /* 895 * mprotect needs to preserve PAT and encryption bits when updating 896 * vm_page_prot 897 */ 898 #define pgprot_modify pgprot_modify 899 static inline pgprot_t pgprot_modify(pgprot_t oldprot, pgprot_t newprot) 900 { 901 pgprotval_t preservebits = pgprot_val(oldprot) & _PAGE_CHG_MASK; 902 pgprotval_t addbits = pgprot_val(newprot) & ~_PAGE_CHG_MASK; 903 return __pgprot(preservebits | addbits); 904 } 905 906 #define pte_pgprot(x) __pgprot(pte_flags(x)) 907 #define pmd_pgprot(x) __pgprot(pmd_flags(x)) 908 #define pud_pgprot(x) __pgprot(pud_flags(x)) 909 #define p4d_pgprot(x) __pgprot(p4d_flags(x)) 910 911 #define canon_pgprot(p) __pgprot(massage_pgprot(p)) 912 913 static inline int is_new_memtype_allowed(u64 paddr, unsigned long size, 914 enum page_cache_mode pcm, 915 enum page_cache_mode new_pcm) 916 { 917 /* 918 * PAT type is always WB for untracked ranges, so no need to check. 919 */ 920 if (x86_platform.is_untracked_pat_range(paddr, paddr + size)) 921 return 1; 922 923 /* 924 * Certain new memtypes are not allowed with certain 925 * requested memtype: 926 * - request is uncached, return cannot be write-back 927 * - request is write-combine, return cannot be write-back 928 * - request is write-through, return cannot be write-back 929 * - request is write-through, return cannot be write-combine 930 */ 931 if ((pcm == _PAGE_CACHE_MODE_UC_MINUS && 932 new_pcm == _PAGE_CACHE_MODE_WB) || 933 (pcm == _PAGE_CACHE_MODE_WC && 934 new_pcm == _PAGE_CACHE_MODE_WB) || 935 (pcm == _PAGE_CACHE_MODE_WT && 936 new_pcm == _PAGE_CACHE_MODE_WB) || 937 (pcm == _PAGE_CACHE_MODE_WT && 938 new_pcm == _PAGE_CACHE_MODE_WC)) { 939 return 0; 940 } 941 942 return 1; 943 } 944 945 pmd_t *populate_extra_pmd(unsigned long vaddr); 946 pte_t *populate_extra_pte(unsigned long vaddr); 947 948 #ifdef CONFIG_MITIGATION_PAGE_TABLE_ISOLATION 949 pgd_t __pti_set_user_pgtbl(pgd_t *pgdp, pgd_t pgd); 950 951 /* 952 * Take a PGD location (pgdp) and a pgd value that needs to be set there. 953 * Populates the user and returns the resulting PGD that must be set in 954 * the kernel copy of the page tables. 955 */ 956 static inline pgd_t pti_set_user_pgtbl(pgd_t *pgdp, pgd_t pgd) 957 { 958 if (!static_cpu_has(X86_FEATURE_PTI)) 959 return pgd; 960 return __pti_set_user_pgtbl(pgdp, pgd); 961 } 962 #else /* CONFIG_MITIGATION_PAGE_TABLE_ISOLATION */ 963 static inline pgd_t pti_set_user_pgtbl(pgd_t *pgdp, pgd_t pgd) 964 { 965 return pgd; 966 } 967 #endif /* CONFIG_MITIGATION_PAGE_TABLE_ISOLATION */ 968 969 #endif /* __ASSEMBLER__ */ 970 971 972 #ifdef CONFIG_X86_32 973 # include <asm/pgtable_32.h> 974 #else 975 # include <asm/pgtable_64.h> 976 #endif 977 978 #ifndef __ASSEMBLER__ 979 #include <linux/mm_types.h> 980 #include <linux/mmdebug.h> 981 #include <linux/log2.h> 982 #include <asm/fixmap.h> 983 984 static inline int pte_none(pte_t pte) 985 { 986 return !(pte.pte & ~(_PAGE_KNL_ERRATUM_MASK)); 987 } 988 989 #define __HAVE_ARCH_PTE_SAME 990 static inline int pte_same(pte_t a, pte_t b) 991 { 992 return a.pte == b.pte; 993 } 994 995 static inline pte_t pte_advance_pfn(pte_t pte, unsigned long nr) 996 { 997 if (__pte_needs_invert(pte_val(pte))) 998 return __pte(pte_val(pte) - (nr << PFN_PTE_SHIFT)); 999 return __pte(pte_val(pte) + (nr << PFN_PTE_SHIFT)); 1000 } 1001 #define pte_advance_pfn pte_advance_pfn 1002 1003 static inline int pte_present(pte_t a) 1004 { 1005 return pte_flags(a) & (_PAGE_PRESENT | _PAGE_PROTNONE); 1006 } 1007 1008 #ifdef CONFIG_ARCH_HAS_PTE_DEVMAP 1009 static inline int pte_devmap(pte_t a) 1010 { 1011 return (pte_flags(a) & _PAGE_DEVMAP) == _PAGE_DEVMAP; 1012 } 1013 #endif 1014 1015 #define pte_accessible pte_accessible 1016 static inline bool pte_accessible(struct mm_struct *mm, pte_t a) 1017 { 1018 if (pte_flags(a) & _PAGE_PRESENT) 1019 return true; 1020 1021 if ((pte_flags(a) & _PAGE_PROTNONE) && 1022 atomic_read(&mm->tlb_flush_pending)) 1023 return true; 1024 1025 return false; 1026 } 1027 1028 static inline int pmd_present(pmd_t pmd) 1029 { 1030 /* 1031 * Checking for _PAGE_PSE is needed too because 1032 * split_huge_page will temporarily clear the present bit (but 1033 * the _PAGE_PSE flag will remain set at all times while the 1034 * _PAGE_PRESENT bit is clear). 1035 */ 1036 return pmd_flags(pmd) & (_PAGE_PRESENT | _PAGE_PROTNONE | _PAGE_PSE); 1037 } 1038 1039 #ifdef CONFIG_NUMA_BALANCING 1040 /* 1041 * These work without NUMA balancing but the kernel does not care. See the 1042 * comment in include/linux/pgtable.h 1043 */ 1044 static inline int pte_protnone(pte_t pte) 1045 { 1046 return (pte_flags(pte) & (_PAGE_PROTNONE | _PAGE_PRESENT)) 1047 == _PAGE_PROTNONE; 1048 } 1049 1050 static inline int pmd_protnone(pmd_t pmd) 1051 { 1052 return (pmd_flags(pmd) & (_PAGE_PROTNONE | _PAGE_PRESENT)) 1053 == _PAGE_PROTNONE; 1054 } 1055 #endif /* CONFIG_NUMA_BALANCING */ 1056 1057 static inline int pmd_none(pmd_t pmd) 1058 { 1059 /* Only check low word on 32-bit platforms, since it might be 1060 out of sync with upper half. */ 1061 unsigned long val = native_pmd_val(pmd); 1062 return (val & ~_PAGE_KNL_ERRATUM_MASK) == 0; 1063 } 1064 1065 static inline unsigned long pmd_page_vaddr(pmd_t pmd) 1066 { 1067 return (unsigned long)__va(pmd_val(pmd) & pmd_pfn_mask(pmd)); 1068 } 1069 1070 /* 1071 * Currently stuck as a macro due to indirect forward reference to 1072 * linux/mmzone.h's __section_mem_map_addr() definition: 1073 */ 1074 #define pmd_page(pmd) pfn_to_page(pmd_pfn(pmd)) 1075 1076 /* 1077 * Conversion functions: convert a page and protection to a page entry, 1078 * and a page entry and page directory to the page they refer to. 1079 * 1080 * (Currently stuck as a macro because of indirect forward reference 1081 * to linux/mm.h:page_to_nid()) 1082 */ 1083 #define mk_pte(page, pgprot) \ 1084 ({ \ 1085 pgprot_t __pgprot = pgprot; \ 1086 \ 1087 WARN_ON_ONCE((pgprot_val(__pgprot) & (_PAGE_DIRTY | _PAGE_RW)) == \ 1088 _PAGE_DIRTY); \ 1089 pfn_pte(page_to_pfn(page), __pgprot); \ 1090 }) 1091 1092 static inline int pmd_bad(pmd_t pmd) 1093 { 1094 return (pmd_flags(pmd) & ~(_PAGE_USER | _PAGE_ACCESSED)) != 1095 (_KERNPG_TABLE & ~_PAGE_ACCESSED); 1096 } 1097 1098 static inline unsigned long pages_to_mb(unsigned long npg) 1099 { 1100 return npg >> (20 - PAGE_SHIFT); 1101 } 1102 1103 #if CONFIG_PGTABLE_LEVELS > 2 1104 static inline int pud_none(pud_t pud) 1105 { 1106 return (native_pud_val(pud) & ~(_PAGE_KNL_ERRATUM_MASK)) == 0; 1107 } 1108 1109 static inline int pud_present(pud_t pud) 1110 { 1111 return pud_flags(pud) & _PAGE_PRESENT; 1112 } 1113 1114 static inline pmd_t *pud_pgtable(pud_t pud) 1115 { 1116 return (pmd_t *)__va(pud_val(pud) & pud_pfn_mask(pud)); 1117 } 1118 1119 /* 1120 * Currently stuck as a macro due to indirect forward reference to 1121 * linux/mmzone.h's __section_mem_map_addr() definition: 1122 */ 1123 #define pud_page(pud) pfn_to_page(pud_pfn(pud)) 1124 1125 #define pud_leaf pud_leaf 1126 static inline bool pud_leaf(pud_t pud) 1127 { 1128 return pud_val(pud) & _PAGE_PSE; 1129 } 1130 1131 static inline int pud_bad(pud_t pud) 1132 { 1133 return (pud_flags(pud) & ~(_KERNPG_TABLE | _PAGE_USER)) != 0; 1134 } 1135 #endif /* CONFIG_PGTABLE_LEVELS > 2 */ 1136 1137 #if CONFIG_PGTABLE_LEVELS > 3 1138 static inline int p4d_none(p4d_t p4d) 1139 { 1140 return (native_p4d_val(p4d) & ~(_PAGE_KNL_ERRATUM_MASK)) == 0; 1141 } 1142 1143 static inline int p4d_present(p4d_t p4d) 1144 { 1145 return p4d_flags(p4d) & _PAGE_PRESENT; 1146 } 1147 1148 static inline pud_t *p4d_pgtable(p4d_t p4d) 1149 { 1150 return (pud_t *)__va(p4d_val(p4d) & p4d_pfn_mask(p4d)); 1151 } 1152 1153 /* 1154 * Currently stuck as a macro due to indirect forward reference to 1155 * linux/mmzone.h's __section_mem_map_addr() definition: 1156 */ 1157 #define p4d_page(p4d) pfn_to_page(p4d_pfn(p4d)) 1158 1159 static inline int p4d_bad(p4d_t p4d) 1160 { 1161 unsigned long ignore_flags = _KERNPG_TABLE | _PAGE_USER; 1162 1163 if (IS_ENABLED(CONFIG_MITIGATION_PAGE_TABLE_ISOLATION)) 1164 ignore_flags |= _PAGE_NX; 1165 1166 return (p4d_flags(p4d) & ~ignore_flags) != 0; 1167 } 1168 #endif /* CONFIG_PGTABLE_LEVELS > 3 */ 1169 1170 static inline unsigned long p4d_index(unsigned long address) 1171 { 1172 return (address >> P4D_SHIFT) & (PTRS_PER_P4D - 1); 1173 } 1174 1175 #if CONFIG_PGTABLE_LEVELS > 4 1176 static inline int pgd_present(pgd_t pgd) 1177 { 1178 if (!pgtable_l5_enabled()) 1179 return 1; 1180 return pgd_flags(pgd) & _PAGE_PRESENT; 1181 } 1182 1183 static inline unsigned long pgd_page_vaddr(pgd_t pgd) 1184 { 1185 return (unsigned long)__va((unsigned long)pgd_val(pgd) & PTE_PFN_MASK); 1186 } 1187 1188 /* 1189 * Currently stuck as a macro due to indirect forward reference to 1190 * linux/mmzone.h's __section_mem_map_addr() definition: 1191 */ 1192 #define pgd_page(pgd) pfn_to_page(pgd_pfn(pgd)) 1193 1194 /* to find an entry in a page-table-directory. */ 1195 static inline p4d_t *p4d_offset(pgd_t *pgd, unsigned long address) 1196 { 1197 if (!pgtable_l5_enabled()) 1198 return (p4d_t *)pgd; 1199 return (p4d_t *)pgd_page_vaddr(*pgd) + p4d_index(address); 1200 } 1201 1202 static inline int pgd_bad(pgd_t pgd) 1203 { 1204 unsigned long ignore_flags = _PAGE_USER; 1205 1206 if (!pgtable_l5_enabled()) 1207 return 0; 1208 1209 if (IS_ENABLED(CONFIG_MITIGATION_PAGE_TABLE_ISOLATION)) 1210 ignore_flags |= _PAGE_NX; 1211 1212 return (pgd_flags(pgd) & ~ignore_flags) != _KERNPG_TABLE; 1213 } 1214 1215 static inline int pgd_none(pgd_t pgd) 1216 { 1217 if (!pgtable_l5_enabled()) 1218 return 0; 1219 /* 1220 * There is no need to do a workaround for the KNL stray 1221 * A/D bit erratum here. PGDs only point to page tables 1222 * except on 32-bit non-PAE which is not supported on 1223 * KNL. 1224 */ 1225 return !native_pgd_val(pgd); 1226 } 1227 #endif /* CONFIG_PGTABLE_LEVELS > 4 */ 1228 1229 #endif /* __ASSEMBLER__ */ 1230 1231 #define KERNEL_PGD_BOUNDARY pgd_index(PAGE_OFFSET) 1232 #define KERNEL_PGD_PTRS (PTRS_PER_PGD - KERNEL_PGD_BOUNDARY) 1233 1234 #ifndef __ASSEMBLER__ 1235 1236 extern int direct_gbpages; 1237 void init_mem_mapping(void); 1238 void early_alloc_pgt_buf(void); 1239 void __init poking_init(void); 1240 unsigned long init_memory_mapping(unsigned long start, 1241 unsigned long end, pgprot_t prot); 1242 1243 #ifdef CONFIG_X86_64 1244 extern pgd_t trampoline_pgd_entry; 1245 #endif 1246 1247 /* local pte updates need not use xchg for locking */ 1248 static inline pte_t native_local_ptep_get_and_clear(pte_t *ptep) 1249 { 1250 pte_t res = *ptep; 1251 1252 /* Pure native function needs no input for mm, addr */ 1253 native_pte_clear(NULL, 0, ptep); 1254 return res; 1255 } 1256 1257 static inline pmd_t native_local_pmdp_get_and_clear(pmd_t *pmdp) 1258 { 1259 pmd_t res = *pmdp; 1260 1261 native_pmd_clear(pmdp); 1262 return res; 1263 } 1264 1265 static inline pud_t native_local_pudp_get_and_clear(pud_t *pudp) 1266 { 1267 pud_t res = *pudp; 1268 1269 native_pud_clear(pudp); 1270 return res; 1271 } 1272 1273 static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr, 1274 pmd_t *pmdp, pmd_t pmd) 1275 { 1276 page_table_check_pmd_set(mm, pmdp, pmd); 1277 set_pmd(pmdp, pmd); 1278 } 1279 1280 static inline void set_pud_at(struct mm_struct *mm, unsigned long addr, 1281 pud_t *pudp, pud_t pud) 1282 { 1283 page_table_check_pud_set(mm, pudp, pud); 1284 native_set_pud(pudp, pud); 1285 } 1286 1287 /* 1288 * We only update the dirty/accessed state if we set 1289 * the dirty bit by hand in the kernel, since the hardware 1290 * will do the accessed bit for us, and we don't want to 1291 * race with other CPU's that might be updating the dirty 1292 * bit at the same time. 1293 */ 1294 struct vm_area_struct; 1295 1296 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 1297 extern int ptep_set_access_flags(struct vm_area_struct *vma, 1298 unsigned long address, pte_t *ptep, 1299 pte_t entry, int dirty); 1300 1301 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 1302 extern int ptep_test_and_clear_young(struct vm_area_struct *vma, 1303 unsigned long addr, pte_t *ptep); 1304 1305 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 1306 extern int ptep_clear_flush_young(struct vm_area_struct *vma, 1307 unsigned long address, pte_t *ptep); 1308 1309 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 1310 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, 1311 pte_t *ptep) 1312 { 1313 pte_t pte = native_ptep_get_and_clear(ptep); 1314 page_table_check_pte_clear(mm, pte); 1315 return pte; 1316 } 1317 1318 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL 1319 static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm, 1320 unsigned long addr, pte_t *ptep, 1321 int full) 1322 { 1323 pte_t pte; 1324 if (full) { 1325 /* 1326 * Full address destruction in progress; paravirt does not 1327 * care about updates and native needs no locking 1328 */ 1329 pte = native_local_ptep_get_and_clear(ptep); 1330 page_table_check_pte_clear(mm, pte); 1331 } else { 1332 pte = ptep_get_and_clear(mm, addr, ptep); 1333 } 1334 return pte; 1335 } 1336 1337 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 1338 static inline void ptep_set_wrprotect(struct mm_struct *mm, 1339 unsigned long addr, pte_t *ptep) 1340 { 1341 /* 1342 * Avoid accidentally creating shadow stack PTEs 1343 * (Write=0,Dirty=1). Use cmpxchg() to prevent races with 1344 * the hardware setting Dirty=1. 1345 */ 1346 pte_t old_pte, new_pte; 1347 1348 old_pte = READ_ONCE(*ptep); 1349 do { 1350 new_pte = pte_wrprotect(old_pte); 1351 } while (!try_cmpxchg((long *)&ptep->pte, (long *)&old_pte, *(long *)&new_pte)); 1352 } 1353 1354 #define flush_tlb_fix_spurious_fault(vma, address, ptep) do { } while (0) 1355 1356 #define mk_pmd(page, pgprot) pfn_pmd(page_to_pfn(page), (pgprot)) 1357 1358 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 1359 extern int pmdp_set_access_flags(struct vm_area_struct *vma, 1360 unsigned long address, pmd_t *pmdp, 1361 pmd_t entry, int dirty); 1362 extern int pudp_set_access_flags(struct vm_area_struct *vma, 1363 unsigned long address, pud_t *pudp, 1364 pud_t entry, int dirty); 1365 1366 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 1367 extern int pmdp_test_and_clear_young(struct vm_area_struct *vma, 1368 unsigned long addr, pmd_t *pmdp); 1369 extern int pudp_test_and_clear_young(struct vm_area_struct *vma, 1370 unsigned long addr, pud_t *pudp); 1371 1372 #define __HAVE_ARCH_PMDP_CLEAR_YOUNG_FLUSH 1373 extern int pmdp_clear_flush_young(struct vm_area_struct *vma, 1374 unsigned long address, pmd_t *pmdp); 1375 1376 1377 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 1378 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, unsigned long addr, 1379 pmd_t *pmdp) 1380 { 1381 pmd_t pmd = native_pmdp_get_and_clear(pmdp); 1382 1383 page_table_check_pmd_clear(mm, pmd); 1384 1385 return pmd; 1386 } 1387 1388 #define __HAVE_ARCH_PUDP_HUGE_GET_AND_CLEAR 1389 static inline pud_t pudp_huge_get_and_clear(struct mm_struct *mm, 1390 unsigned long addr, pud_t *pudp) 1391 { 1392 pud_t pud = native_pudp_get_and_clear(pudp); 1393 1394 page_table_check_pud_clear(mm, pud); 1395 1396 return pud; 1397 } 1398 1399 #define __HAVE_ARCH_PMDP_SET_WRPROTECT 1400 static inline void pmdp_set_wrprotect(struct mm_struct *mm, 1401 unsigned long addr, pmd_t *pmdp) 1402 { 1403 /* 1404 * Avoid accidentally creating shadow stack PTEs 1405 * (Write=0,Dirty=1). Use cmpxchg() to prevent races with 1406 * the hardware setting Dirty=1. 1407 */ 1408 pmd_t old_pmd, new_pmd; 1409 1410 old_pmd = READ_ONCE(*pmdp); 1411 do { 1412 new_pmd = pmd_wrprotect(old_pmd); 1413 } while (!try_cmpxchg((long *)pmdp, (long *)&old_pmd, *(long *)&new_pmd)); 1414 } 1415 1416 #ifndef pmdp_establish 1417 #define pmdp_establish pmdp_establish 1418 static inline pmd_t pmdp_establish(struct vm_area_struct *vma, 1419 unsigned long address, pmd_t *pmdp, pmd_t pmd) 1420 { 1421 page_table_check_pmd_set(vma->vm_mm, pmdp, pmd); 1422 if (IS_ENABLED(CONFIG_SMP)) { 1423 return xchg(pmdp, pmd); 1424 } else { 1425 pmd_t old = *pmdp; 1426 WRITE_ONCE(*pmdp, pmd); 1427 return old; 1428 } 1429 } 1430 #endif 1431 1432 #ifdef CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD 1433 static inline pud_t pudp_establish(struct vm_area_struct *vma, 1434 unsigned long address, pud_t *pudp, pud_t pud) 1435 { 1436 page_table_check_pud_set(vma->vm_mm, pudp, pud); 1437 if (IS_ENABLED(CONFIG_SMP)) { 1438 return xchg(pudp, pud); 1439 } else { 1440 pud_t old = *pudp; 1441 WRITE_ONCE(*pudp, pud); 1442 return old; 1443 } 1444 } 1445 #endif 1446 1447 #define __HAVE_ARCH_PMDP_INVALIDATE_AD 1448 extern pmd_t pmdp_invalidate_ad(struct vm_area_struct *vma, 1449 unsigned long address, pmd_t *pmdp); 1450 1451 pud_t pudp_invalidate(struct vm_area_struct *vma, unsigned long address, 1452 pud_t *pudp); 1453 1454 /* 1455 * Page table pages are page-aligned. The lower half of the top 1456 * level is used for userspace and the top half for the kernel. 1457 * 1458 * Returns true for parts of the PGD that map userspace and 1459 * false for the parts that map the kernel. 1460 */ 1461 static inline bool pgdp_maps_userspace(void *__ptr) 1462 { 1463 unsigned long ptr = (unsigned long)__ptr; 1464 1465 return (((ptr & ~PAGE_MASK) / sizeof(pgd_t)) < PGD_KERNEL_START); 1466 } 1467 1468 #ifdef CONFIG_MITIGATION_PAGE_TABLE_ISOLATION 1469 /* 1470 * All top-level MITIGATION_PAGE_TABLE_ISOLATION page tables are order-1 pages 1471 * (8k-aligned and 8k in size). The kernel one is at the beginning 4k and 1472 * the user one is in the last 4k. To switch between them, you 1473 * just need to flip the 12th bit in their addresses. 1474 */ 1475 #define PTI_PGTABLE_SWITCH_BIT PAGE_SHIFT 1476 1477 /* 1478 * This generates better code than the inline assembly in 1479 * __set_bit(). 1480 */ 1481 static inline void *ptr_set_bit(void *ptr, int bit) 1482 { 1483 unsigned long __ptr = (unsigned long)ptr; 1484 1485 __ptr |= BIT(bit); 1486 return (void *)__ptr; 1487 } 1488 static inline void *ptr_clear_bit(void *ptr, int bit) 1489 { 1490 unsigned long __ptr = (unsigned long)ptr; 1491 1492 __ptr &= ~BIT(bit); 1493 return (void *)__ptr; 1494 } 1495 1496 static inline pgd_t *kernel_to_user_pgdp(pgd_t *pgdp) 1497 { 1498 return ptr_set_bit(pgdp, PTI_PGTABLE_SWITCH_BIT); 1499 } 1500 1501 static inline pgd_t *user_to_kernel_pgdp(pgd_t *pgdp) 1502 { 1503 return ptr_clear_bit(pgdp, PTI_PGTABLE_SWITCH_BIT); 1504 } 1505 1506 static inline p4d_t *kernel_to_user_p4dp(p4d_t *p4dp) 1507 { 1508 return ptr_set_bit(p4dp, PTI_PGTABLE_SWITCH_BIT); 1509 } 1510 1511 static inline p4d_t *user_to_kernel_p4dp(p4d_t *p4dp) 1512 { 1513 return ptr_clear_bit(p4dp, PTI_PGTABLE_SWITCH_BIT); 1514 } 1515 #endif /* CONFIG_MITIGATION_PAGE_TABLE_ISOLATION */ 1516 1517 /* 1518 * clone_pgd_range(pgd_t *dst, pgd_t *src, int count); 1519 * 1520 * dst - pointer to pgd range anywhere on a pgd page 1521 * src - "" 1522 * count - the number of pgds to copy. 1523 * 1524 * dst and src can be on the same page, but the range must not overlap, 1525 * and must not cross a page boundary. 1526 */ 1527 static inline void clone_pgd_range(pgd_t *dst, pgd_t *src, int count) 1528 { 1529 memcpy(dst, src, count * sizeof(pgd_t)); 1530 #ifdef CONFIG_MITIGATION_PAGE_TABLE_ISOLATION 1531 if (!static_cpu_has(X86_FEATURE_PTI)) 1532 return; 1533 /* Clone the user space pgd as well */ 1534 memcpy(kernel_to_user_pgdp(dst), kernel_to_user_pgdp(src), 1535 count * sizeof(pgd_t)); 1536 #endif 1537 } 1538 1539 #define PTE_SHIFT ilog2(PTRS_PER_PTE) 1540 static inline int page_level_shift(enum pg_level level) 1541 { 1542 return (PAGE_SHIFT - PTE_SHIFT) + level * PTE_SHIFT; 1543 } 1544 static inline unsigned long page_level_size(enum pg_level level) 1545 { 1546 return 1UL << page_level_shift(level); 1547 } 1548 static inline unsigned long page_level_mask(enum pg_level level) 1549 { 1550 return ~(page_level_size(level) - 1); 1551 } 1552 1553 /* 1554 * The x86 doesn't have any external MMU info: the kernel page 1555 * tables contain all the necessary information. 1556 */ 1557 static inline void update_mmu_cache(struct vm_area_struct *vma, 1558 unsigned long addr, pte_t *ptep) 1559 { 1560 } 1561 static inline void update_mmu_cache_range(struct vm_fault *vmf, 1562 struct vm_area_struct *vma, unsigned long addr, 1563 pte_t *ptep, unsigned int nr) 1564 { 1565 } 1566 static inline void update_mmu_cache_pmd(struct vm_area_struct *vma, 1567 unsigned long addr, pmd_t *pmd) 1568 { 1569 } 1570 static inline void update_mmu_cache_pud(struct vm_area_struct *vma, 1571 unsigned long addr, pud_t *pud) 1572 { 1573 } 1574 static inline pte_t pte_swp_mkexclusive(pte_t pte) 1575 { 1576 return pte_set_flags(pte, _PAGE_SWP_EXCLUSIVE); 1577 } 1578 1579 static inline int pte_swp_exclusive(pte_t pte) 1580 { 1581 return pte_flags(pte) & _PAGE_SWP_EXCLUSIVE; 1582 } 1583 1584 static inline pte_t pte_swp_clear_exclusive(pte_t pte) 1585 { 1586 return pte_clear_flags(pte, _PAGE_SWP_EXCLUSIVE); 1587 } 1588 1589 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 1590 static inline pte_t pte_swp_mksoft_dirty(pte_t pte) 1591 { 1592 return pte_set_flags(pte, _PAGE_SWP_SOFT_DIRTY); 1593 } 1594 1595 static inline int pte_swp_soft_dirty(pte_t pte) 1596 { 1597 return pte_flags(pte) & _PAGE_SWP_SOFT_DIRTY; 1598 } 1599 1600 static inline pte_t pte_swp_clear_soft_dirty(pte_t pte) 1601 { 1602 return pte_clear_flags(pte, _PAGE_SWP_SOFT_DIRTY); 1603 } 1604 1605 #ifdef CONFIG_ARCH_ENABLE_THP_MIGRATION 1606 static inline pmd_t pmd_swp_mksoft_dirty(pmd_t pmd) 1607 { 1608 return pmd_set_flags(pmd, _PAGE_SWP_SOFT_DIRTY); 1609 } 1610 1611 static inline int pmd_swp_soft_dirty(pmd_t pmd) 1612 { 1613 return pmd_flags(pmd) & _PAGE_SWP_SOFT_DIRTY; 1614 } 1615 1616 static inline pmd_t pmd_swp_clear_soft_dirty(pmd_t pmd) 1617 { 1618 return pmd_clear_flags(pmd, _PAGE_SWP_SOFT_DIRTY); 1619 } 1620 #endif 1621 #endif 1622 1623 #ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP 1624 static inline pte_t pte_swp_mkuffd_wp(pte_t pte) 1625 { 1626 return pte_set_flags(pte, _PAGE_SWP_UFFD_WP); 1627 } 1628 1629 static inline int pte_swp_uffd_wp(pte_t pte) 1630 { 1631 return pte_flags(pte) & _PAGE_SWP_UFFD_WP; 1632 } 1633 1634 static inline pte_t pte_swp_clear_uffd_wp(pte_t pte) 1635 { 1636 return pte_clear_flags(pte, _PAGE_SWP_UFFD_WP); 1637 } 1638 1639 static inline pmd_t pmd_swp_mkuffd_wp(pmd_t pmd) 1640 { 1641 return pmd_set_flags(pmd, _PAGE_SWP_UFFD_WP); 1642 } 1643 1644 static inline int pmd_swp_uffd_wp(pmd_t pmd) 1645 { 1646 return pmd_flags(pmd) & _PAGE_SWP_UFFD_WP; 1647 } 1648 1649 static inline pmd_t pmd_swp_clear_uffd_wp(pmd_t pmd) 1650 { 1651 return pmd_clear_flags(pmd, _PAGE_SWP_UFFD_WP); 1652 } 1653 #endif /* CONFIG_HAVE_ARCH_USERFAULTFD_WP */ 1654 1655 static inline u16 pte_flags_pkey(unsigned long pte_flags) 1656 { 1657 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS 1658 /* ifdef to avoid doing 59-bit shift on 32-bit values */ 1659 return (pte_flags & _PAGE_PKEY_MASK) >> _PAGE_BIT_PKEY_BIT0; 1660 #else 1661 return 0; 1662 #endif 1663 } 1664 1665 static inline bool __pkru_allows_pkey(u16 pkey, bool write) 1666 { 1667 u32 pkru = read_pkru(); 1668 1669 if (!__pkru_allows_read(pkru, pkey)) 1670 return false; 1671 if (write && !__pkru_allows_write(pkru, pkey)) 1672 return false; 1673 1674 return true; 1675 } 1676 1677 /* 1678 * 'pteval' can come from a PTE, PMD or PUD. We only check 1679 * _PAGE_PRESENT, _PAGE_USER, and _PAGE_RW in here which are the 1680 * same value on all 3 types. 1681 */ 1682 static inline bool __pte_access_permitted(unsigned long pteval, bool write) 1683 { 1684 unsigned long need_pte_bits = _PAGE_PRESENT|_PAGE_USER; 1685 1686 /* 1687 * Write=0,Dirty=1 PTEs are shadow stack, which the kernel 1688 * shouldn't generally allow access to, but since they 1689 * are already Write=0, the below logic covers both cases. 1690 */ 1691 if (write) 1692 need_pte_bits |= _PAGE_RW; 1693 1694 if ((pteval & need_pte_bits) != need_pte_bits) 1695 return 0; 1696 1697 return __pkru_allows_pkey(pte_flags_pkey(pteval), write); 1698 } 1699 1700 #define pte_access_permitted pte_access_permitted 1701 static inline bool pte_access_permitted(pte_t pte, bool write) 1702 { 1703 return __pte_access_permitted(pte_val(pte), write); 1704 } 1705 1706 #define pmd_access_permitted pmd_access_permitted 1707 static inline bool pmd_access_permitted(pmd_t pmd, bool write) 1708 { 1709 return __pte_access_permitted(pmd_val(pmd), write); 1710 } 1711 1712 #define pud_access_permitted pud_access_permitted 1713 static inline bool pud_access_permitted(pud_t pud, bool write) 1714 { 1715 return __pte_access_permitted(pud_val(pud), write); 1716 } 1717 1718 #define __HAVE_ARCH_PFN_MODIFY_ALLOWED 1 1719 extern bool pfn_modify_allowed(unsigned long pfn, pgprot_t prot); 1720 1721 static inline bool arch_has_pfn_modify_check(void) 1722 { 1723 return boot_cpu_has_bug(X86_BUG_L1TF); 1724 } 1725 1726 #define arch_check_zapped_pte arch_check_zapped_pte 1727 void arch_check_zapped_pte(struct vm_area_struct *vma, pte_t pte); 1728 1729 #define arch_check_zapped_pmd arch_check_zapped_pmd 1730 void arch_check_zapped_pmd(struct vm_area_struct *vma, pmd_t pmd); 1731 1732 #define arch_check_zapped_pud arch_check_zapped_pud 1733 void arch_check_zapped_pud(struct vm_area_struct *vma, pud_t pud); 1734 1735 #ifdef CONFIG_XEN_PV 1736 #define arch_has_hw_nonleaf_pmd_young arch_has_hw_nonleaf_pmd_young 1737 static inline bool arch_has_hw_nonleaf_pmd_young(void) 1738 { 1739 return !cpu_feature_enabled(X86_FEATURE_XENPV); 1740 } 1741 #endif 1742 1743 #ifdef CONFIG_PAGE_TABLE_CHECK 1744 static inline bool pte_user_accessible_page(pte_t pte) 1745 { 1746 return (pte_val(pte) & _PAGE_PRESENT) && (pte_val(pte) & _PAGE_USER); 1747 } 1748 1749 static inline bool pmd_user_accessible_page(pmd_t pmd) 1750 { 1751 return pmd_leaf(pmd) && (pmd_val(pmd) & _PAGE_PRESENT) && (pmd_val(pmd) & _PAGE_USER); 1752 } 1753 1754 static inline bool pud_user_accessible_page(pud_t pud) 1755 { 1756 return pud_leaf(pud) && (pud_val(pud) & _PAGE_PRESENT) && (pud_val(pud) & _PAGE_USER); 1757 } 1758 #endif 1759 1760 #ifdef CONFIG_X86_SGX 1761 int arch_memory_failure(unsigned long pfn, int flags); 1762 #define arch_memory_failure arch_memory_failure 1763 1764 bool arch_is_platform_page(u64 paddr); 1765 #define arch_is_platform_page arch_is_platform_page 1766 #endif 1767 1768 /* 1769 * Use set_p*_safe(), and elide TLB flushing, when confident that *no* 1770 * TLB flush will be required as a result of the "set". For example, use 1771 * in scenarios where it is known ahead of time that the routine is 1772 * setting non-present entries, or re-setting an existing entry to the 1773 * same value. Otherwise, use the typical "set" helpers and flush the 1774 * TLB. 1775 */ 1776 #define set_pte_safe(ptep, pte) \ 1777 ({ \ 1778 WARN_ON_ONCE(pte_present(*ptep) && !pte_same(*ptep, pte)); \ 1779 set_pte(ptep, pte); \ 1780 }) 1781 1782 #define set_pmd_safe(pmdp, pmd) \ 1783 ({ \ 1784 WARN_ON_ONCE(pmd_present(*pmdp) && !pmd_same(*pmdp, pmd)); \ 1785 set_pmd(pmdp, pmd); \ 1786 }) 1787 1788 #define set_pud_safe(pudp, pud) \ 1789 ({ \ 1790 WARN_ON_ONCE(pud_present(*pudp) && !pud_same(*pudp, pud)); \ 1791 set_pud(pudp, pud); \ 1792 }) 1793 1794 #define set_p4d_safe(p4dp, p4d) \ 1795 ({ \ 1796 WARN_ON_ONCE(p4d_present(*p4dp) && !p4d_same(*p4dp, p4d)); \ 1797 set_p4d(p4dp, p4d); \ 1798 }) 1799 1800 #define set_pgd_safe(pgdp, pgd) \ 1801 ({ \ 1802 WARN_ON_ONCE(pgd_present(*pgdp) && !pgd_same(*pgdp, pgd)); \ 1803 set_pgd(pgdp, pgd); \ 1804 }) 1805 #endif /* __ASSEMBLER__ */ 1806 1807 #endif /* _ASM_X86_PGTABLE_H */ 1808