1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _ASM_X86_PGTABLE_H 3 #define _ASM_X86_PGTABLE_H 4 5 #include <linux/mem_encrypt.h> 6 #include <asm/page.h> 7 #include <asm/pgtable_types.h> 8 9 /* 10 * Macro to mark a page protection value as UC- 11 */ 12 #define pgprot_noncached(prot) \ 13 ((boot_cpu_data.x86 > 3) \ 14 ? (__pgprot(pgprot_val(prot) | \ 15 cachemode2protval(_PAGE_CACHE_MODE_UC_MINUS))) \ 16 : (prot)) 17 18 #ifndef __ASSEMBLY__ 19 #include <linux/spinlock.h> 20 #include <asm/x86_init.h> 21 #include <asm/pkru.h> 22 #include <asm/fpu/api.h> 23 #include <asm/coco.h> 24 #include <asm-generic/pgtable_uffd.h> 25 #include <linux/page_table_check.h> 26 27 extern pgd_t early_top_pgt[PTRS_PER_PGD]; 28 bool __init __early_make_pgtable(unsigned long address, pmdval_t pmd); 29 30 struct seq_file; 31 void ptdump_walk_pgd_level(struct seq_file *m, struct mm_struct *mm); 32 void ptdump_walk_pgd_level_debugfs(struct seq_file *m, struct mm_struct *mm, 33 bool user); 34 void ptdump_walk_pgd_level_checkwx(void); 35 void ptdump_walk_user_pgd_level_checkwx(void); 36 37 /* 38 * Macros to add or remove encryption attribute 39 */ 40 #define pgprot_encrypted(prot) __pgprot(cc_mkenc(pgprot_val(prot))) 41 #define pgprot_decrypted(prot) __pgprot(cc_mkdec(pgprot_val(prot))) 42 43 #ifdef CONFIG_DEBUG_WX 44 #define debug_checkwx() ptdump_walk_pgd_level_checkwx() 45 #define debug_checkwx_user() ptdump_walk_user_pgd_level_checkwx() 46 #else 47 #define debug_checkwx() do { } while (0) 48 #define debug_checkwx_user() do { } while (0) 49 #endif 50 51 /* 52 * ZERO_PAGE is a global shared page that is always zero: used 53 * for zero-mapped memory areas etc.. 54 */ 55 extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)] 56 __visible; 57 #define ZERO_PAGE(vaddr) ((void)(vaddr),virt_to_page(empty_zero_page)) 58 59 extern spinlock_t pgd_lock; 60 extern struct list_head pgd_list; 61 62 extern struct mm_struct *pgd_page_get_mm(struct page *page); 63 64 extern pmdval_t early_pmd_flags; 65 66 #ifdef CONFIG_PARAVIRT_XXL 67 #include <asm/paravirt.h> 68 #else /* !CONFIG_PARAVIRT_XXL */ 69 #define set_pte(ptep, pte) native_set_pte(ptep, pte) 70 71 #define set_pte_atomic(ptep, pte) \ 72 native_set_pte_atomic(ptep, pte) 73 74 #define set_pmd(pmdp, pmd) native_set_pmd(pmdp, pmd) 75 76 #ifndef __PAGETABLE_P4D_FOLDED 77 #define set_pgd(pgdp, pgd) native_set_pgd(pgdp, pgd) 78 #define pgd_clear(pgd) (pgtable_l5_enabled() ? native_pgd_clear(pgd) : 0) 79 #endif 80 81 #ifndef set_p4d 82 # define set_p4d(p4dp, p4d) native_set_p4d(p4dp, p4d) 83 #endif 84 85 #ifndef __PAGETABLE_PUD_FOLDED 86 #define p4d_clear(p4d) native_p4d_clear(p4d) 87 #endif 88 89 #ifndef set_pud 90 # define set_pud(pudp, pud) native_set_pud(pudp, pud) 91 #endif 92 93 #ifndef __PAGETABLE_PUD_FOLDED 94 #define pud_clear(pud) native_pud_clear(pud) 95 #endif 96 97 #define pte_clear(mm, addr, ptep) native_pte_clear(mm, addr, ptep) 98 #define pmd_clear(pmd) native_pmd_clear(pmd) 99 100 #define pgd_val(x) native_pgd_val(x) 101 #define __pgd(x) native_make_pgd(x) 102 103 #ifndef __PAGETABLE_P4D_FOLDED 104 #define p4d_val(x) native_p4d_val(x) 105 #define __p4d(x) native_make_p4d(x) 106 #endif 107 108 #ifndef __PAGETABLE_PUD_FOLDED 109 #define pud_val(x) native_pud_val(x) 110 #define __pud(x) native_make_pud(x) 111 #endif 112 113 #ifndef __PAGETABLE_PMD_FOLDED 114 #define pmd_val(x) native_pmd_val(x) 115 #define __pmd(x) native_make_pmd(x) 116 #endif 117 118 #define pte_val(x) native_pte_val(x) 119 #define __pte(x) native_make_pte(x) 120 121 #define arch_end_context_switch(prev) do {} while(0) 122 #endif /* CONFIG_PARAVIRT_XXL */ 123 124 /* 125 * The following only work if pte_present() is true. 126 * Undefined behaviour if not.. 127 */ 128 static inline bool pte_dirty(pte_t pte) 129 { 130 return pte_flags(pte) & _PAGE_DIRTY_BITS; 131 } 132 133 static inline bool pte_shstk(pte_t pte) 134 { 135 return cpu_feature_enabled(X86_FEATURE_SHSTK) && 136 (pte_flags(pte) & (_PAGE_RW | _PAGE_DIRTY)) == _PAGE_DIRTY; 137 } 138 139 static inline int pte_young(pte_t pte) 140 { 141 return pte_flags(pte) & _PAGE_ACCESSED; 142 } 143 144 #define pmd_dirty pmd_dirty 145 static inline bool pmd_dirty(pmd_t pmd) 146 { 147 return pmd_flags(pmd) & _PAGE_DIRTY_BITS; 148 } 149 150 static inline bool pmd_shstk(pmd_t pmd) 151 { 152 return cpu_feature_enabled(X86_FEATURE_SHSTK) && 153 (pmd_flags(pmd) & (_PAGE_RW | _PAGE_DIRTY | _PAGE_PSE)) == 154 (_PAGE_DIRTY | _PAGE_PSE); 155 } 156 157 #define pmd_young pmd_young 158 static inline int pmd_young(pmd_t pmd) 159 { 160 return pmd_flags(pmd) & _PAGE_ACCESSED; 161 } 162 163 static inline bool pud_dirty(pud_t pud) 164 { 165 return pud_flags(pud) & _PAGE_DIRTY_BITS; 166 } 167 168 static inline int pud_young(pud_t pud) 169 { 170 return pud_flags(pud) & _PAGE_ACCESSED; 171 } 172 173 static inline int pte_write(pte_t pte) 174 { 175 /* 176 * Shadow stack pages are logically writable, but do not have 177 * _PAGE_RW. Check for them separately from _PAGE_RW itself. 178 */ 179 return (pte_flags(pte) & _PAGE_RW) || pte_shstk(pte); 180 } 181 182 #define pmd_write pmd_write 183 static inline int pmd_write(pmd_t pmd) 184 { 185 /* 186 * Shadow stack pages are logically writable, but do not have 187 * _PAGE_RW. Check for them separately from _PAGE_RW itself. 188 */ 189 return (pmd_flags(pmd) & _PAGE_RW) || pmd_shstk(pmd); 190 } 191 192 #define pud_write pud_write 193 static inline int pud_write(pud_t pud) 194 { 195 return pud_flags(pud) & _PAGE_RW; 196 } 197 198 static inline int pte_huge(pte_t pte) 199 { 200 return pte_flags(pte) & _PAGE_PSE; 201 } 202 203 static inline int pte_global(pte_t pte) 204 { 205 return pte_flags(pte) & _PAGE_GLOBAL; 206 } 207 208 static inline int pte_exec(pte_t pte) 209 { 210 return !(pte_flags(pte) & _PAGE_NX); 211 } 212 213 static inline int pte_special(pte_t pte) 214 { 215 return pte_flags(pte) & _PAGE_SPECIAL; 216 } 217 218 /* Entries that were set to PROT_NONE are inverted */ 219 220 static inline u64 protnone_mask(u64 val); 221 222 #define PFN_PTE_SHIFT PAGE_SHIFT 223 224 static inline unsigned long pte_pfn(pte_t pte) 225 { 226 phys_addr_t pfn = pte_val(pte); 227 pfn ^= protnone_mask(pfn); 228 return (pfn & PTE_PFN_MASK) >> PAGE_SHIFT; 229 } 230 231 static inline unsigned long pmd_pfn(pmd_t pmd) 232 { 233 phys_addr_t pfn = pmd_val(pmd); 234 pfn ^= protnone_mask(pfn); 235 return (pfn & pmd_pfn_mask(pmd)) >> PAGE_SHIFT; 236 } 237 238 static inline unsigned long pud_pfn(pud_t pud) 239 { 240 phys_addr_t pfn = pud_val(pud); 241 pfn ^= protnone_mask(pfn); 242 return (pfn & pud_pfn_mask(pud)) >> PAGE_SHIFT; 243 } 244 245 static inline unsigned long p4d_pfn(p4d_t p4d) 246 { 247 return (p4d_val(p4d) & p4d_pfn_mask(p4d)) >> PAGE_SHIFT; 248 } 249 250 static inline unsigned long pgd_pfn(pgd_t pgd) 251 { 252 return (pgd_val(pgd) & PTE_PFN_MASK) >> PAGE_SHIFT; 253 } 254 255 #define p4d_leaf p4d_large 256 static inline int p4d_large(p4d_t p4d) 257 { 258 /* No 512 GiB pages yet */ 259 return 0; 260 } 261 262 #define pte_page(pte) pfn_to_page(pte_pfn(pte)) 263 264 #define pmd_leaf pmd_large 265 static inline int pmd_large(pmd_t pte) 266 { 267 return pmd_flags(pte) & _PAGE_PSE; 268 } 269 270 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 271 /* NOTE: when predicate huge page, consider also pmd_devmap, or use pmd_large */ 272 static inline int pmd_trans_huge(pmd_t pmd) 273 { 274 return (pmd_val(pmd) & (_PAGE_PSE|_PAGE_DEVMAP)) == _PAGE_PSE; 275 } 276 277 #ifdef CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD 278 static inline int pud_trans_huge(pud_t pud) 279 { 280 return (pud_val(pud) & (_PAGE_PSE|_PAGE_DEVMAP)) == _PAGE_PSE; 281 } 282 #endif 283 284 #define has_transparent_hugepage has_transparent_hugepage 285 static inline int has_transparent_hugepage(void) 286 { 287 return boot_cpu_has(X86_FEATURE_PSE); 288 } 289 290 #ifdef CONFIG_ARCH_HAS_PTE_DEVMAP 291 static inline int pmd_devmap(pmd_t pmd) 292 { 293 return !!(pmd_val(pmd) & _PAGE_DEVMAP); 294 } 295 296 #ifdef CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD 297 static inline int pud_devmap(pud_t pud) 298 { 299 return !!(pud_val(pud) & _PAGE_DEVMAP); 300 } 301 #else 302 static inline int pud_devmap(pud_t pud) 303 { 304 return 0; 305 } 306 #endif 307 308 static inline int pgd_devmap(pgd_t pgd) 309 { 310 return 0; 311 } 312 #endif 313 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 314 315 static inline pte_t pte_set_flags(pte_t pte, pteval_t set) 316 { 317 pteval_t v = native_pte_val(pte); 318 319 return native_make_pte(v | set); 320 } 321 322 static inline pte_t pte_clear_flags(pte_t pte, pteval_t clear) 323 { 324 pteval_t v = native_pte_val(pte); 325 326 return native_make_pte(v & ~clear); 327 } 328 329 /* 330 * Write protection operations can result in Dirty=1,Write=0 PTEs. But in the 331 * case of X86_FEATURE_USER_SHSTK, these PTEs denote shadow stack memory. So 332 * when creating dirty, write-protected memory, a software bit is used: 333 * _PAGE_BIT_SAVED_DIRTY. The following functions take a PTE and transition the 334 * Dirty bit to SavedDirty, and vice-vesra. 335 * 336 * This shifting is only done if needed. In the case of shifting 337 * Dirty->SavedDirty, the condition is if the PTE is Write=0. In the case of 338 * shifting SavedDirty->Dirty, the condition is Write=1. 339 */ 340 static inline pgprotval_t mksaveddirty_shift(pgprotval_t v) 341 { 342 pgprotval_t cond = (~v >> _PAGE_BIT_RW) & 1; 343 344 v |= ((v >> _PAGE_BIT_DIRTY) & cond) << _PAGE_BIT_SAVED_DIRTY; 345 v &= ~(cond << _PAGE_BIT_DIRTY); 346 347 return v; 348 } 349 350 static inline pgprotval_t clear_saveddirty_shift(pgprotval_t v) 351 { 352 pgprotval_t cond = (v >> _PAGE_BIT_RW) & 1; 353 354 v |= ((v >> _PAGE_BIT_SAVED_DIRTY) & cond) << _PAGE_BIT_DIRTY; 355 v &= ~(cond << _PAGE_BIT_SAVED_DIRTY); 356 357 return v; 358 } 359 360 static inline pte_t pte_mksaveddirty(pte_t pte) 361 { 362 pteval_t v = native_pte_val(pte); 363 364 v = mksaveddirty_shift(v); 365 return native_make_pte(v); 366 } 367 368 static inline pte_t pte_clear_saveddirty(pte_t pte) 369 { 370 pteval_t v = native_pte_val(pte); 371 372 v = clear_saveddirty_shift(v); 373 return native_make_pte(v); 374 } 375 376 static inline pte_t pte_wrprotect(pte_t pte) 377 { 378 pte = pte_clear_flags(pte, _PAGE_RW); 379 380 /* 381 * Blindly clearing _PAGE_RW might accidentally create 382 * a shadow stack PTE (Write=0,Dirty=1). Move the hardware 383 * dirty value to the software bit, if present. 384 */ 385 return pte_mksaveddirty(pte); 386 } 387 388 #ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP 389 static inline int pte_uffd_wp(pte_t pte) 390 { 391 bool wp = pte_flags(pte) & _PAGE_UFFD_WP; 392 393 #ifdef CONFIG_DEBUG_VM 394 /* 395 * Having write bit for wr-protect-marked present ptes is fatal, 396 * because it means the uffd-wp bit will be ignored and write will 397 * just go through. 398 * 399 * Use any chance of pgtable walking to verify this (e.g., when 400 * page swapped out or being migrated for all purposes). It means 401 * something is already wrong. Tell the admin even before the 402 * process crashes. We also nail it with wrong pgtable setup. 403 */ 404 WARN_ON_ONCE(wp && pte_write(pte)); 405 #endif 406 407 return wp; 408 } 409 410 static inline pte_t pte_mkuffd_wp(pte_t pte) 411 { 412 return pte_wrprotect(pte_set_flags(pte, _PAGE_UFFD_WP)); 413 } 414 415 static inline pte_t pte_clear_uffd_wp(pte_t pte) 416 { 417 return pte_clear_flags(pte, _PAGE_UFFD_WP); 418 } 419 #endif /* CONFIG_HAVE_ARCH_USERFAULTFD_WP */ 420 421 static inline pte_t pte_mkclean(pte_t pte) 422 { 423 return pte_clear_flags(pte, _PAGE_DIRTY_BITS); 424 } 425 426 static inline pte_t pte_mkold(pte_t pte) 427 { 428 return pte_clear_flags(pte, _PAGE_ACCESSED); 429 } 430 431 static inline pte_t pte_mkexec(pte_t pte) 432 { 433 return pte_clear_flags(pte, _PAGE_NX); 434 } 435 436 static inline pte_t pte_mkdirty(pte_t pte) 437 { 438 pte = pte_set_flags(pte, _PAGE_DIRTY | _PAGE_SOFT_DIRTY); 439 440 return pte_mksaveddirty(pte); 441 } 442 443 static inline pte_t pte_mkwrite_shstk(pte_t pte) 444 { 445 pte = pte_clear_flags(pte, _PAGE_RW); 446 447 return pte_set_flags(pte, _PAGE_DIRTY); 448 } 449 450 static inline pte_t pte_mkyoung(pte_t pte) 451 { 452 return pte_set_flags(pte, _PAGE_ACCESSED); 453 } 454 455 static inline pte_t pte_mkwrite_novma(pte_t pte) 456 { 457 return pte_set_flags(pte, _PAGE_RW); 458 } 459 460 struct vm_area_struct; 461 pte_t pte_mkwrite(pte_t pte, struct vm_area_struct *vma); 462 #define pte_mkwrite pte_mkwrite 463 464 static inline pte_t pte_mkhuge(pte_t pte) 465 { 466 return pte_set_flags(pte, _PAGE_PSE); 467 } 468 469 static inline pte_t pte_clrhuge(pte_t pte) 470 { 471 return pte_clear_flags(pte, _PAGE_PSE); 472 } 473 474 static inline pte_t pte_mkglobal(pte_t pte) 475 { 476 return pte_set_flags(pte, _PAGE_GLOBAL); 477 } 478 479 static inline pte_t pte_clrglobal(pte_t pte) 480 { 481 return pte_clear_flags(pte, _PAGE_GLOBAL); 482 } 483 484 static inline pte_t pte_mkspecial(pte_t pte) 485 { 486 return pte_set_flags(pte, _PAGE_SPECIAL); 487 } 488 489 static inline pte_t pte_mkdevmap(pte_t pte) 490 { 491 return pte_set_flags(pte, _PAGE_SPECIAL|_PAGE_DEVMAP); 492 } 493 494 static inline pmd_t pmd_set_flags(pmd_t pmd, pmdval_t set) 495 { 496 pmdval_t v = native_pmd_val(pmd); 497 498 return native_make_pmd(v | set); 499 } 500 501 static inline pmd_t pmd_clear_flags(pmd_t pmd, pmdval_t clear) 502 { 503 pmdval_t v = native_pmd_val(pmd); 504 505 return native_make_pmd(v & ~clear); 506 } 507 508 /* See comments above mksaveddirty_shift() */ 509 static inline pmd_t pmd_mksaveddirty(pmd_t pmd) 510 { 511 pmdval_t v = native_pmd_val(pmd); 512 513 v = mksaveddirty_shift(v); 514 return native_make_pmd(v); 515 } 516 517 /* See comments above mksaveddirty_shift() */ 518 static inline pmd_t pmd_clear_saveddirty(pmd_t pmd) 519 { 520 pmdval_t v = native_pmd_val(pmd); 521 522 v = clear_saveddirty_shift(v); 523 return native_make_pmd(v); 524 } 525 526 static inline pmd_t pmd_wrprotect(pmd_t pmd) 527 { 528 pmd = pmd_clear_flags(pmd, _PAGE_RW); 529 530 /* 531 * Blindly clearing _PAGE_RW might accidentally create 532 * a shadow stack PMD (RW=0, Dirty=1). Move the hardware 533 * dirty value to the software bit. 534 */ 535 return pmd_mksaveddirty(pmd); 536 } 537 538 #ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP 539 static inline int pmd_uffd_wp(pmd_t pmd) 540 { 541 return pmd_flags(pmd) & _PAGE_UFFD_WP; 542 } 543 544 static inline pmd_t pmd_mkuffd_wp(pmd_t pmd) 545 { 546 return pmd_wrprotect(pmd_set_flags(pmd, _PAGE_UFFD_WP)); 547 } 548 549 static inline pmd_t pmd_clear_uffd_wp(pmd_t pmd) 550 { 551 return pmd_clear_flags(pmd, _PAGE_UFFD_WP); 552 } 553 #endif /* CONFIG_HAVE_ARCH_USERFAULTFD_WP */ 554 555 static inline pmd_t pmd_mkold(pmd_t pmd) 556 { 557 return pmd_clear_flags(pmd, _PAGE_ACCESSED); 558 } 559 560 static inline pmd_t pmd_mkclean(pmd_t pmd) 561 { 562 return pmd_clear_flags(pmd, _PAGE_DIRTY_BITS); 563 } 564 565 static inline pmd_t pmd_mkdirty(pmd_t pmd) 566 { 567 pmd = pmd_set_flags(pmd, _PAGE_DIRTY | _PAGE_SOFT_DIRTY); 568 569 return pmd_mksaveddirty(pmd); 570 } 571 572 static inline pmd_t pmd_mkwrite_shstk(pmd_t pmd) 573 { 574 pmd = pmd_clear_flags(pmd, _PAGE_RW); 575 576 return pmd_set_flags(pmd, _PAGE_DIRTY); 577 } 578 579 static inline pmd_t pmd_mkdevmap(pmd_t pmd) 580 { 581 return pmd_set_flags(pmd, _PAGE_DEVMAP); 582 } 583 584 static inline pmd_t pmd_mkhuge(pmd_t pmd) 585 { 586 return pmd_set_flags(pmd, _PAGE_PSE); 587 } 588 589 static inline pmd_t pmd_mkyoung(pmd_t pmd) 590 { 591 return pmd_set_flags(pmd, _PAGE_ACCESSED); 592 } 593 594 static inline pmd_t pmd_mkwrite_novma(pmd_t pmd) 595 { 596 return pmd_set_flags(pmd, _PAGE_RW); 597 } 598 599 pmd_t pmd_mkwrite(pmd_t pmd, struct vm_area_struct *vma); 600 #define pmd_mkwrite pmd_mkwrite 601 602 static inline pud_t pud_set_flags(pud_t pud, pudval_t set) 603 { 604 pudval_t v = native_pud_val(pud); 605 606 return native_make_pud(v | set); 607 } 608 609 static inline pud_t pud_clear_flags(pud_t pud, pudval_t clear) 610 { 611 pudval_t v = native_pud_val(pud); 612 613 return native_make_pud(v & ~clear); 614 } 615 616 /* See comments above mksaveddirty_shift() */ 617 static inline pud_t pud_mksaveddirty(pud_t pud) 618 { 619 pudval_t v = native_pud_val(pud); 620 621 v = mksaveddirty_shift(v); 622 return native_make_pud(v); 623 } 624 625 /* See comments above mksaveddirty_shift() */ 626 static inline pud_t pud_clear_saveddirty(pud_t pud) 627 { 628 pudval_t v = native_pud_val(pud); 629 630 v = clear_saveddirty_shift(v); 631 return native_make_pud(v); 632 } 633 634 static inline pud_t pud_mkold(pud_t pud) 635 { 636 return pud_clear_flags(pud, _PAGE_ACCESSED); 637 } 638 639 static inline pud_t pud_mkclean(pud_t pud) 640 { 641 return pud_clear_flags(pud, _PAGE_DIRTY_BITS); 642 } 643 644 static inline pud_t pud_wrprotect(pud_t pud) 645 { 646 pud = pud_clear_flags(pud, _PAGE_RW); 647 648 /* 649 * Blindly clearing _PAGE_RW might accidentally create 650 * a shadow stack PUD (RW=0, Dirty=1). Move the hardware 651 * dirty value to the software bit. 652 */ 653 return pud_mksaveddirty(pud); 654 } 655 656 static inline pud_t pud_mkdirty(pud_t pud) 657 { 658 pud = pud_set_flags(pud, _PAGE_DIRTY | _PAGE_SOFT_DIRTY); 659 660 return pud_mksaveddirty(pud); 661 } 662 663 static inline pud_t pud_mkdevmap(pud_t pud) 664 { 665 return pud_set_flags(pud, _PAGE_DEVMAP); 666 } 667 668 static inline pud_t pud_mkhuge(pud_t pud) 669 { 670 return pud_set_flags(pud, _PAGE_PSE); 671 } 672 673 static inline pud_t pud_mkyoung(pud_t pud) 674 { 675 return pud_set_flags(pud, _PAGE_ACCESSED); 676 } 677 678 static inline pud_t pud_mkwrite(pud_t pud) 679 { 680 pud = pud_set_flags(pud, _PAGE_RW); 681 682 return pud_clear_saveddirty(pud); 683 } 684 685 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 686 static inline int pte_soft_dirty(pte_t pte) 687 { 688 return pte_flags(pte) & _PAGE_SOFT_DIRTY; 689 } 690 691 static inline int pmd_soft_dirty(pmd_t pmd) 692 { 693 return pmd_flags(pmd) & _PAGE_SOFT_DIRTY; 694 } 695 696 static inline int pud_soft_dirty(pud_t pud) 697 { 698 return pud_flags(pud) & _PAGE_SOFT_DIRTY; 699 } 700 701 static inline pte_t pte_mksoft_dirty(pte_t pte) 702 { 703 return pte_set_flags(pte, _PAGE_SOFT_DIRTY); 704 } 705 706 static inline pmd_t pmd_mksoft_dirty(pmd_t pmd) 707 { 708 return pmd_set_flags(pmd, _PAGE_SOFT_DIRTY); 709 } 710 711 static inline pud_t pud_mksoft_dirty(pud_t pud) 712 { 713 return pud_set_flags(pud, _PAGE_SOFT_DIRTY); 714 } 715 716 static inline pte_t pte_clear_soft_dirty(pte_t pte) 717 { 718 return pte_clear_flags(pte, _PAGE_SOFT_DIRTY); 719 } 720 721 static inline pmd_t pmd_clear_soft_dirty(pmd_t pmd) 722 { 723 return pmd_clear_flags(pmd, _PAGE_SOFT_DIRTY); 724 } 725 726 static inline pud_t pud_clear_soft_dirty(pud_t pud) 727 { 728 return pud_clear_flags(pud, _PAGE_SOFT_DIRTY); 729 } 730 731 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ 732 733 /* 734 * Mask out unsupported bits in a present pgprot. Non-present pgprots 735 * can use those bits for other purposes, so leave them be. 736 */ 737 static inline pgprotval_t massage_pgprot(pgprot_t pgprot) 738 { 739 pgprotval_t protval = pgprot_val(pgprot); 740 741 if (protval & _PAGE_PRESENT) 742 protval &= __supported_pte_mask; 743 744 return protval; 745 } 746 747 static inline pgprotval_t check_pgprot(pgprot_t pgprot) 748 { 749 pgprotval_t massaged_val = massage_pgprot(pgprot); 750 751 /* mmdebug.h can not be included here because of dependencies */ 752 #ifdef CONFIG_DEBUG_VM 753 WARN_ONCE(pgprot_val(pgprot) != massaged_val, 754 "attempted to set unsupported pgprot: %016llx " 755 "bits: %016llx supported: %016llx\n", 756 (u64)pgprot_val(pgprot), 757 (u64)pgprot_val(pgprot) ^ massaged_val, 758 (u64)__supported_pte_mask); 759 #endif 760 761 return massaged_val; 762 } 763 764 static inline pte_t pfn_pte(unsigned long page_nr, pgprot_t pgprot) 765 { 766 phys_addr_t pfn = (phys_addr_t)page_nr << PAGE_SHIFT; 767 pfn ^= protnone_mask(pgprot_val(pgprot)); 768 pfn &= PTE_PFN_MASK; 769 return __pte(pfn | check_pgprot(pgprot)); 770 } 771 772 static inline pmd_t pfn_pmd(unsigned long page_nr, pgprot_t pgprot) 773 { 774 phys_addr_t pfn = (phys_addr_t)page_nr << PAGE_SHIFT; 775 pfn ^= protnone_mask(pgprot_val(pgprot)); 776 pfn &= PHYSICAL_PMD_PAGE_MASK; 777 return __pmd(pfn | check_pgprot(pgprot)); 778 } 779 780 static inline pud_t pfn_pud(unsigned long page_nr, pgprot_t pgprot) 781 { 782 phys_addr_t pfn = (phys_addr_t)page_nr << PAGE_SHIFT; 783 pfn ^= protnone_mask(pgprot_val(pgprot)); 784 pfn &= PHYSICAL_PUD_PAGE_MASK; 785 return __pud(pfn | check_pgprot(pgprot)); 786 } 787 788 static inline pmd_t pmd_mkinvalid(pmd_t pmd) 789 { 790 return pfn_pmd(pmd_pfn(pmd), 791 __pgprot(pmd_flags(pmd) & ~(_PAGE_PRESENT|_PAGE_PROTNONE))); 792 } 793 794 static inline u64 flip_protnone_guard(u64 oldval, u64 val, u64 mask); 795 796 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 797 { 798 pteval_t val = pte_val(pte), oldval = val; 799 pte_t pte_result; 800 801 /* 802 * Chop off the NX bit (if present), and add the NX portion of 803 * the newprot (if present): 804 */ 805 val &= _PAGE_CHG_MASK; 806 val |= check_pgprot(newprot) & ~_PAGE_CHG_MASK; 807 val = flip_protnone_guard(oldval, val, PTE_PFN_MASK); 808 809 pte_result = __pte(val); 810 811 /* 812 * To avoid creating Write=0,Dirty=1 PTEs, pte_modify() needs to avoid: 813 * 1. Marking Write=0 PTEs Dirty=1 814 * 2. Marking Dirty=1 PTEs Write=0 815 * 816 * The first case cannot happen because the _PAGE_CHG_MASK will filter 817 * out any Dirty bit passed in newprot. Handle the second case by 818 * going through the mksaveddirty exercise. Only do this if the old 819 * value was Write=1 to avoid doing this on Shadow Stack PTEs. 820 */ 821 if (oldval & _PAGE_RW) 822 pte_result = pte_mksaveddirty(pte_result); 823 else 824 pte_result = pte_clear_saveddirty(pte_result); 825 826 return pte_result; 827 } 828 829 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) 830 { 831 pmdval_t val = pmd_val(pmd), oldval = val; 832 pmd_t pmd_result; 833 834 val &= (_HPAGE_CHG_MASK & ~_PAGE_DIRTY); 835 val |= check_pgprot(newprot) & ~_HPAGE_CHG_MASK; 836 val = flip_protnone_guard(oldval, val, PHYSICAL_PMD_PAGE_MASK); 837 838 pmd_result = __pmd(val); 839 840 /* 841 * To avoid creating Write=0,Dirty=1 PMDs, pte_modify() needs to avoid: 842 * 1. Marking Write=0 PMDs Dirty=1 843 * 2. Marking Dirty=1 PMDs Write=0 844 * 845 * The first case cannot happen because the _PAGE_CHG_MASK will filter 846 * out any Dirty bit passed in newprot. Handle the second case by 847 * going through the mksaveddirty exercise. Only do this if the old 848 * value was Write=1 to avoid doing this on Shadow Stack PTEs. 849 */ 850 if (oldval & _PAGE_RW) 851 pmd_result = pmd_mksaveddirty(pmd_result); 852 else 853 pmd_result = pmd_clear_saveddirty(pmd_result); 854 855 return pmd_result; 856 } 857 858 /* 859 * mprotect needs to preserve PAT and encryption bits when updating 860 * vm_page_prot 861 */ 862 #define pgprot_modify pgprot_modify 863 static inline pgprot_t pgprot_modify(pgprot_t oldprot, pgprot_t newprot) 864 { 865 pgprotval_t preservebits = pgprot_val(oldprot) & _PAGE_CHG_MASK; 866 pgprotval_t addbits = pgprot_val(newprot) & ~_PAGE_CHG_MASK; 867 return __pgprot(preservebits | addbits); 868 } 869 870 #define pte_pgprot(x) __pgprot(pte_flags(x)) 871 #define pmd_pgprot(x) __pgprot(pmd_flags(x)) 872 #define pud_pgprot(x) __pgprot(pud_flags(x)) 873 #define p4d_pgprot(x) __pgprot(p4d_flags(x)) 874 875 #define canon_pgprot(p) __pgprot(massage_pgprot(p)) 876 877 static inline int is_new_memtype_allowed(u64 paddr, unsigned long size, 878 enum page_cache_mode pcm, 879 enum page_cache_mode new_pcm) 880 { 881 /* 882 * PAT type is always WB for untracked ranges, so no need to check. 883 */ 884 if (x86_platform.is_untracked_pat_range(paddr, paddr + size)) 885 return 1; 886 887 /* 888 * Certain new memtypes are not allowed with certain 889 * requested memtype: 890 * - request is uncached, return cannot be write-back 891 * - request is write-combine, return cannot be write-back 892 * - request is write-through, return cannot be write-back 893 * - request is write-through, return cannot be write-combine 894 */ 895 if ((pcm == _PAGE_CACHE_MODE_UC_MINUS && 896 new_pcm == _PAGE_CACHE_MODE_WB) || 897 (pcm == _PAGE_CACHE_MODE_WC && 898 new_pcm == _PAGE_CACHE_MODE_WB) || 899 (pcm == _PAGE_CACHE_MODE_WT && 900 new_pcm == _PAGE_CACHE_MODE_WB) || 901 (pcm == _PAGE_CACHE_MODE_WT && 902 new_pcm == _PAGE_CACHE_MODE_WC)) { 903 return 0; 904 } 905 906 return 1; 907 } 908 909 pmd_t *populate_extra_pmd(unsigned long vaddr); 910 pte_t *populate_extra_pte(unsigned long vaddr); 911 912 #ifdef CONFIG_PAGE_TABLE_ISOLATION 913 pgd_t __pti_set_user_pgtbl(pgd_t *pgdp, pgd_t pgd); 914 915 /* 916 * Take a PGD location (pgdp) and a pgd value that needs to be set there. 917 * Populates the user and returns the resulting PGD that must be set in 918 * the kernel copy of the page tables. 919 */ 920 static inline pgd_t pti_set_user_pgtbl(pgd_t *pgdp, pgd_t pgd) 921 { 922 if (!static_cpu_has(X86_FEATURE_PTI)) 923 return pgd; 924 return __pti_set_user_pgtbl(pgdp, pgd); 925 } 926 #else /* CONFIG_PAGE_TABLE_ISOLATION */ 927 static inline pgd_t pti_set_user_pgtbl(pgd_t *pgdp, pgd_t pgd) 928 { 929 return pgd; 930 } 931 #endif /* CONFIG_PAGE_TABLE_ISOLATION */ 932 933 #endif /* __ASSEMBLY__ */ 934 935 936 #ifdef CONFIG_X86_32 937 # include <asm/pgtable_32.h> 938 #else 939 # include <asm/pgtable_64.h> 940 #endif 941 942 #ifndef __ASSEMBLY__ 943 #include <linux/mm_types.h> 944 #include <linux/mmdebug.h> 945 #include <linux/log2.h> 946 #include <asm/fixmap.h> 947 948 static inline int pte_none(pte_t pte) 949 { 950 return !(pte.pte & ~(_PAGE_KNL_ERRATUM_MASK)); 951 } 952 953 #define __HAVE_ARCH_PTE_SAME 954 static inline int pte_same(pte_t a, pte_t b) 955 { 956 return a.pte == b.pte; 957 } 958 959 static inline pte_t pte_next_pfn(pte_t pte) 960 { 961 if (__pte_needs_invert(pte_val(pte))) 962 return __pte(pte_val(pte) - (1UL << PFN_PTE_SHIFT)); 963 return __pte(pte_val(pte) + (1UL << PFN_PTE_SHIFT)); 964 } 965 #define pte_next_pfn pte_next_pfn 966 967 static inline int pte_present(pte_t a) 968 { 969 return pte_flags(a) & (_PAGE_PRESENT | _PAGE_PROTNONE); 970 } 971 972 #ifdef CONFIG_ARCH_HAS_PTE_DEVMAP 973 static inline int pte_devmap(pte_t a) 974 { 975 return (pte_flags(a) & _PAGE_DEVMAP) == _PAGE_DEVMAP; 976 } 977 #endif 978 979 #define pte_accessible pte_accessible 980 static inline bool pte_accessible(struct mm_struct *mm, pte_t a) 981 { 982 if (pte_flags(a) & _PAGE_PRESENT) 983 return true; 984 985 if ((pte_flags(a) & _PAGE_PROTNONE) && 986 atomic_read(&mm->tlb_flush_pending)) 987 return true; 988 989 return false; 990 } 991 992 static inline int pmd_present(pmd_t pmd) 993 { 994 /* 995 * Checking for _PAGE_PSE is needed too because 996 * split_huge_page will temporarily clear the present bit (but 997 * the _PAGE_PSE flag will remain set at all times while the 998 * _PAGE_PRESENT bit is clear). 999 */ 1000 return pmd_flags(pmd) & (_PAGE_PRESENT | _PAGE_PROTNONE | _PAGE_PSE); 1001 } 1002 1003 #ifdef CONFIG_NUMA_BALANCING 1004 /* 1005 * These work without NUMA balancing but the kernel does not care. See the 1006 * comment in include/linux/pgtable.h 1007 */ 1008 static inline int pte_protnone(pte_t pte) 1009 { 1010 return (pte_flags(pte) & (_PAGE_PROTNONE | _PAGE_PRESENT)) 1011 == _PAGE_PROTNONE; 1012 } 1013 1014 static inline int pmd_protnone(pmd_t pmd) 1015 { 1016 return (pmd_flags(pmd) & (_PAGE_PROTNONE | _PAGE_PRESENT)) 1017 == _PAGE_PROTNONE; 1018 } 1019 #endif /* CONFIG_NUMA_BALANCING */ 1020 1021 static inline int pmd_none(pmd_t pmd) 1022 { 1023 /* Only check low word on 32-bit platforms, since it might be 1024 out of sync with upper half. */ 1025 unsigned long val = native_pmd_val(pmd); 1026 return (val & ~_PAGE_KNL_ERRATUM_MASK) == 0; 1027 } 1028 1029 static inline unsigned long pmd_page_vaddr(pmd_t pmd) 1030 { 1031 return (unsigned long)__va(pmd_val(pmd) & pmd_pfn_mask(pmd)); 1032 } 1033 1034 /* 1035 * Currently stuck as a macro due to indirect forward reference to 1036 * linux/mmzone.h's __section_mem_map_addr() definition: 1037 */ 1038 #define pmd_page(pmd) pfn_to_page(pmd_pfn(pmd)) 1039 1040 /* 1041 * Conversion functions: convert a page and protection to a page entry, 1042 * and a page entry and page directory to the page they refer to. 1043 * 1044 * (Currently stuck as a macro because of indirect forward reference 1045 * to linux/mm.h:page_to_nid()) 1046 */ 1047 #define mk_pte(page, pgprot) \ 1048 ({ \ 1049 pgprot_t __pgprot = pgprot; \ 1050 \ 1051 WARN_ON_ONCE((pgprot_val(__pgprot) & (_PAGE_DIRTY | _PAGE_RW)) == \ 1052 _PAGE_DIRTY); \ 1053 pfn_pte(page_to_pfn(page), __pgprot); \ 1054 }) 1055 1056 static inline int pmd_bad(pmd_t pmd) 1057 { 1058 return (pmd_flags(pmd) & ~(_PAGE_USER | _PAGE_ACCESSED)) != 1059 (_KERNPG_TABLE & ~_PAGE_ACCESSED); 1060 } 1061 1062 static inline unsigned long pages_to_mb(unsigned long npg) 1063 { 1064 return npg >> (20 - PAGE_SHIFT); 1065 } 1066 1067 #if CONFIG_PGTABLE_LEVELS > 2 1068 static inline int pud_none(pud_t pud) 1069 { 1070 return (native_pud_val(pud) & ~(_PAGE_KNL_ERRATUM_MASK)) == 0; 1071 } 1072 1073 static inline int pud_present(pud_t pud) 1074 { 1075 return pud_flags(pud) & _PAGE_PRESENT; 1076 } 1077 1078 static inline pmd_t *pud_pgtable(pud_t pud) 1079 { 1080 return (pmd_t *)__va(pud_val(pud) & pud_pfn_mask(pud)); 1081 } 1082 1083 /* 1084 * Currently stuck as a macro due to indirect forward reference to 1085 * linux/mmzone.h's __section_mem_map_addr() definition: 1086 */ 1087 #define pud_page(pud) pfn_to_page(pud_pfn(pud)) 1088 1089 #define pud_leaf pud_large 1090 static inline int pud_large(pud_t pud) 1091 { 1092 return (pud_val(pud) & (_PAGE_PSE | _PAGE_PRESENT)) == 1093 (_PAGE_PSE | _PAGE_PRESENT); 1094 } 1095 1096 static inline int pud_bad(pud_t pud) 1097 { 1098 return (pud_flags(pud) & ~(_KERNPG_TABLE | _PAGE_USER)) != 0; 1099 } 1100 #else 1101 #define pud_leaf pud_large 1102 static inline int pud_large(pud_t pud) 1103 { 1104 return 0; 1105 } 1106 #endif /* CONFIG_PGTABLE_LEVELS > 2 */ 1107 1108 #if CONFIG_PGTABLE_LEVELS > 3 1109 static inline int p4d_none(p4d_t p4d) 1110 { 1111 return (native_p4d_val(p4d) & ~(_PAGE_KNL_ERRATUM_MASK)) == 0; 1112 } 1113 1114 static inline int p4d_present(p4d_t p4d) 1115 { 1116 return p4d_flags(p4d) & _PAGE_PRESENT; 1117 } 1118 1119 static inline pud_t *p4d_pgtable(p4d_t p4d) 1120 { 1121 return (pud_t *)__va(p4d_val(p4d) & p4d_pfn_mask(p4d)); 1122 } 1123 1124 /* 1125 * Currently stuck as a macro due to indirect forward reference to 1126 * linux/mmzone.h's __section_mem_map_addr() definition: 1127 */ 1128 #define p4d_page(p4d) pfn_to_page(p4d_pfn(p4d)) 1129 1130 static inline int p4d_bad(p4d_t p4d) 1131 { 1132 unsigned long ignore_flags = _KERNPG_TABLE | _PAGE_USER; 1133 1134 if (IS_ENABLED(CONFIG_PAGE_TABLE_ISOLATION)) 1135 ignore_flags |= _PAGE_NX; 1136 1137 return (p4d_flags(p4d) & ~ignore_flags) != 0; 1138 } 1139 #endif /* CONFIG_PGTABLE_LEVELS > 3 */ 1140 1141 static inline unsigned long p4d_index(unsigned long address) 1142 { 1143 return (address >> P4D_SHIFT) & (PTRS_PER_P4D - 1); 1144 } 1145 1146 #if CONFIG_PGTABLE_LEVELS > 4 1147 static inline int pgd_present(pgd_t pgd) 1148 { 1149 if (!pgtable_l5_enabled()) 1150 return 1; 1151 return pgd_flags(pgd) & _PAGE_PRESENT; 1152 } 1153 1154 static inline unsigned long pgd_page_vaddr(pgd_t pgd) 1155 { 1156 return (unsigned long)__va((unsigned long)pgd_val(pgd) & PTE_PFN_MASK); 1157 } 1158 1159 /* 1160 * Currently stuck as a macro due to indirect forward reference to 1161 * linux/mmzone.h's __section_mem_map_addr() definition: 1162 */ 1163 #define pgd_page(pgd) pfn_to_page(pgd_pfn(pgd)) 1164 1165 /* to find an entry in a page-table-directory. */ 1166 static inline p4d_t *p4d_offset(pgd_t *pgd, unsigned long address) 1167 { 1168 if (!pgtable_l5_enabled()) 1169 return (p4d_t *)pgd; 1170 return (p4d_t *)pgd_page_vaddr(*pgd) + p4d_index(address); 1171 } 1172 1173 static inline int pgd_bad(pgd_t pgd) 1174 { 1175 unsigned long ignore_flags = _PAGE_USER; 1176 1177 if (!pgtable_l5_enabled()) 1178 return 0; 1179 1180 if (IS_ENABLED(CONFIG_PAGE_TABLE_ISOLATION)) 1181 ignore_flags |= _PAGE_NX; 1182 1183 return (pgd_flags(pgd) & ~ignore_flags) != _KERNPG_TABLE; 1184 } 1185 1186 static inline int pgd_none(pgd_t pgd) 1187 { 1188 if (!pgtable_l5_enabled()) 1189 return 0; 1190 /* 1191 * There is no need to do a workaround for the KNL stray 1192 * A/D bit erratum here. PGDs only point to page tables 1193 * except on 32-bit non-PAE which is not supported on 1194 * KNL. 1195 */ 1196 return !native_pgd_val(pgd); 1197 } 1198 #endif /* CONFIG_PGTABLE_LEVELS > 4 */ 1199 1200 #endif /* __ASSEMBLY__ */ 1201 1202 #define KERNEL_PGD_BOUNDARY pgd_index(PAGE_OFFSET) 1203 #define KERNEL_PGD_PTRS (PTRS_PER_PGD - KERNEL_PGD_BOUNDARY) 1204 1205 #ifndef __ASSEMBLY__ 1206 1207 extern int direct_gbpages; 1208 void init_mem_mapping(void); 1209 void early_alloc_pgt_buf(void); 1210 extern void memblock_find_dma_reserve(void); 1211 void __init poking_init(void); 1212 unsigned long init_memory_mapping(unsigned long start, 1213 unsigned long end, pgprot_t prot); 1214 1215 #ifdef CONFIG_X86_64 1216 extern pgd_t trampoline_pgd_entry; 1217 #endif 1218 1219 /* local pte updates need not use xchg for locking */ 1220 static inline pte_t native_local_ptep_get_and_clear(pte_t *ptep) 1221 { 1222 pte_t res = *ptep; 1223 1224 /* Pure native function needs no input for mm, addr */ 1225 native_pte_clear(NULL, 0, ptep); 1226 return res; 1227 } 1228 1229 static inline pmd_t native_local_pmdp_get_and_clear(pmd_t *pmdp) 1230 { 1231 pmd_t res = *pmdp; 1232 1233 native_pmd_clear(pmdp); 1234 return res; 1235 } 1236 1237 static inline pud_t native_local_pudp_get_and_clear(pud_t *pudp) 1238 { 1239 pud_t res = *pudp; 1240 1241 native_pud_clear(pudp); 1242 return res; 1243 } 1244 1245 static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr, 1246 pmd_t *pmdp, pmd_t pmd) 1247 { 1248 page_table_check_pmd_set(mm, pmdp, pmd); 1249 set_pmd(pmdp, pmd); 1250 } 1251 1252 static inline void set_pud_at(struct mm_struct *mm, unsigned long addr, 1253 pud_t *pudp, pud_t pud) 1254 { 1255 page_table_check_pud_set(mm, pudp, pud); 1256 native_set_pud(pudp, pud); 1257 } 1258 1259 /* 1260 * We only update the dirty/accessed state if we set 1261 * the dirty bit by hand in the kernel, since the hardware 1262 * will do the accessed bit for us, and we don't want to 1263 * race with other CPU's that might be updating the dirty 1264 * bit at the same time. 1265 */ 1266 struct vm_area_struct; 1267 1268 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 1269 extern int ptep_set_access_flags(struct vm_area_struct *vma, 1270 unsigned long address, pte_t *ptep, 1271 pte_t entry, int dirty); 1272 1273 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 1274 extern int ptep_test_and_clear_young(struct vm_area_struct *vma, 1275 unsigned long addr, pte_t *ptep); 1276 1277 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 1278 extern int ptep_clear_flush_young(struct vm_area_struct *vma, 1279 unsigned long address, pte_t *ptep); 1280 1281 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 1282 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, 1283 pte_t *ptep) 1284 { 1285 pte_t pte = native_ptep_get_and_clear(ptep); 1286 page_table_check_pte_clear(mm, pte); 1287 return pte; 1288 } 1289 1290 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL 1291 static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm, 1292 unsigned long addr, pte_t *ptep, 1293 int full) 1294 { 1295 pte_t pte; 1296 if (full) { 1297 /* 1298 * Full address destruction in progress; paravirt does not 1299 * care about updates and native needs no locking 1300 */ 1301 pte = native_local_ptep_get_and_clear(ptep); 1302 page_table_check_pte_clear(mm, pte); 1303 } else { 1304 pte = ptep_get_and_clear(mm, addr, ptep); 1305 } 1306 return pte; 1307 } 1308 1309 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 1310 static inline void ptep_set_wrprotect(struct mm_struct *mm, 1311 unsigned long addr, pte_t *ptep) 1312 { 1313 /* 1314 * Avoid accidentally creating shadow stack PTEs 1315 * (Write=0,Dirty=1). Use cmpxchg() to prevent races with 1316 * the hardware setting Dirty=1. 1317 */ 1318 pte_t old_pte, new_pte; 1319 1320 old_pte = READ_ONCE(*ptep); 1321 do { 1322 new_pte = pte_wrprotect(old_pte); 1323 } while (!try_cmpxchg((long *)&ptep->pte, (long *)&old_pte, *(long *)&new_pte)); 1324 } 1325 1326 #define flush_tlb_fix_spurious_fault(vma, address, ptep) do { } while (0) 1327 1328 #define mk_pmd(page, pgprot) pfn_pmd(page_to_pfn(page), (pgprot)) 1329 1330 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 1331 extern int pmdp_set_access_flags(struct vm_area_struct *vma, 1332 unsigned long address, pmd_t *pmdp, 1333 pmd_t entry, int dirty); 1334 extern int pudp_set_access_flags(struct vm_area_struct *vma, 1335 unsigned long address, pud_t *pudp, 1336 pud_t entry, int dirty); 1337 1338 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 1339 extern int pmdp_test_and_clear_young(struct vm_area_struct *vma, 1340 unsigned long addr, pmd_t *pmdp); 1341 extern int pudp_test_and_clear_young(struct vm_area_struct *vma, 1342 unsigned long addr, pud_t *pudp); 1343 1344 #define __HAVE_ARCH_PMDP_CLEAR_YOUNG_FLUSH 1345 extern int pmdp_clear_flush_young(struct vm_area_struct *vma, 1346 unsigned long address, pmd_t *pmdp); 1347 1348 1349 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 1350 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, unsigned long addr, 1351 pmd_t *pmdp) 1352 { 1353 pmd_t pmd = native_pmdp_get_and_clear(pmdp); 1354 1355 page_table_check_pmd_clear(mm, pmd); 1356 1357 return pmd; 1358 } 1359 1360 #define __HAVE_ARCH_PUDP_HUGE_GET_AND_CLEAR 1361 static inline pud_t pudp_huge_get_and_clear(struct mm_struct *mm, 1362 unsigned long addr, pud_t *pudp) 1363 { 1364 pud_t pud = native_pudp_get_and_clear(pudp); 1365 1366 page_table_check_pud_clear(mm, pud); 1367 1368 return pud; 1369 } 1370 1371 #define __HAVE_ARCH_PMDP_SET_WRPROTECT 1372 static inline void pmdp_set_wrprotect(struct mm_struct *mm, 1373 unsigned long addr, pmd_t *pmdp) 1374 { 1375 /* 1376 * Avoid accidentally creating shadow stack PTEs 1377 * (Write=0,Dirty=1). Use cmpxchg() to prevent races with 1378 * the hardware setting Dirty=1. 1379 */ 1380 pmd_t old_pmd, new_pmd; 1381 1382 old_pmd = READ_ONCE(*pmdp); 1383 do { 1384 new_pmd = pmd_wrprotect(old_pmd); 1385 } while (!try_cmpxchg((long *)pmdp, (long *)&old_pmd, *(long *)&new_pmd)); 1386 } 1387 1388 #ifndef pmdp_establish 1389 #define pmdp_establish pmdp_establish 1390 static inline pmd_t pmdp_establish(struct vm_area_struct *vma, 1391 unsigned long address, pmd_t *pmdp, pmd_t pmd) 1392 { 1393 page_table_check_pmd_set(vma->vm_mm, pmdp, pmd); 1394 if (IS_ENABLED(CONFIG_SMP)) { 1395 return xchg(pmdp, pmd); 1396 } else { 1397 pmd_t old = *pmdp; 1398 WRITE_ONCE(*pmdp, pmd); 1399 return old; 1400 } 1401 } 1402 #endif 1403 1404 #define __HAVE_ARCH_PMDP_INVALIDATE_AD 1405 extern pmd_t pmdp_invalidate_ad(struct vm_area_struct *vma, 1406 unsigned long address, pmd_t *pmdp); 1407 1408 /* 1409 * Page table pages are page-aligned. The lower half of the top 1410 * level is used for userspace and the top half for the kernel. 1411 * 1412 * Returns true for parts of the PGD that map userspace and 1413 * false for the parts that map the kernel. 1414 */ 1415 static inline bool pgdp_maps_userspace(void *__ptr) 1416 { 1417 unsigned long ptr = (unsigned long)__ptr; 1418 1419 return (((ptr & ~PAGE_MASK) / sizeof(pgd_t)) < PGD_KERNEL_START); 1420 } 1421 1422 #define pgd_leaf pgd_large 1423 static inline int pgd_large(pgd_t pgd) { return 0; } 1424 1425 #ifdef CONFIG_PAGE_TABLE_ISOLATION 1426 /* 1427 * All top-level PAGE_TABLE_ISOLATION page tables are order-1 pages 1428 * (8k-aligned and 8k in size). The kernel one is at the beginning 4k and 1429 * the user one is in the last 4k. To switch between them, you 1430 * just need to flip the 12th bit in their addresses. 1431 */ 1432 #define PTI_PGTABLE_SWITCH_BIT PAGE_SHIFT 1433 1434 /* 1435 * This generates better code than the inline assembly in 1436 * __set_bit(). 1437 */ 1438 static inline void *ptr_set_bit(void *ptr, int bit) 1439 { 1440 unsigned long __ptr = (unsigned long)ptr; 1441 1442 __ptr |= BIT(bit); 1443 return (void *)__ptr; 1444 } 1445 static inline void *ptr_clear_bit(void *ptr, int bit) 1446 { 1447 unsigned long __ptr = (unsigned long)ptr; 1448 1449 __ptr &= ~BIT(bit); 1450 return (void *)__ptr; 1451 } 1452 1453 static inline pgd_t *kernel_to_user_pgdp(pgd_t *pgdp) 1454 { 1455 return ptr_set_bit(pgdp, PTI_PGTABLE_SWITCH_BIT); 1456 } 1457 1458 static inline pgd_t *user_to_kernel_pgdp(pgd_t *pgdp) 1459 { 1460 return ptr_clear_bit(pgdp, PTI_PGTABLE_SWITCH_BIT); 1461 } 1462 1463 static inline p4d_t *kernel_to_user_p4dp(p4d_t *p4dp) 1464 { 1465 return ptr_set_bit(p4dp, PTI_PGTABLE_SWITCH_BIT); 1466 } 1467 1468 static inline p4d_t *user_to_kernel_p4dp(p4d_t *p4dp) 1469 { 1470 return ptr_clear_bit(p4dp, PTI_PGTABLE_SWITCH_BIT); 1471 } 1472 #endif /* CONFIG_PAGE_TABLE_ISOLATION */ 1473 1474 /* 1475 * clone_pgd_range(pgd_t *dst, pgd_t *src, int count); 1476 * 1477 * dst - pointer to pgd range anywhere on a pgd page 1478 * src - "" 1479 * count - the number of pgds to copy. 1480 * 1481 * dst and src can be on the same page, but the range must not overlap, 1482 * and must not cross a page boundary. 1483 */ 1484 static inline void clone_pgd_range(pgd_t *dst, pgd_t *src, int count) 1485 { 1486 memcpy(dst, src, count * sizeof(pgd_t)); 1487 #ifdef CONFIG_PAGE_TABLE_ISOLATION 1488 if (!static_cpu_has(X86_FEATURE_PTI)) 1489 return; 1490 /* Clone the user space pgd as well */ 1491 memcpy(kernel_to_user_pgdp(dst), kernel_to_user_pgdp(src), 1492 count * sizeof(pgd_t)); 1493 #endif 1494 } 1495 1496 #define PTE_SHIFT ilog2(PTRS_PER_PTE) 1497 static inline int page_level_shift(enum pg_level level) 1498 { 1499 return (PAGE_SHIFT - PTE_SHIFT) + level * PTE_SHIFT; 1500 } 1501 static inline unsigned long page_level_size(enum pg_level level) 1502 { 1503 return 1UL << page_level_shift(level); 1504 } 1505 static inline unsigned long page_level_mask(enum pg_level level) 1506 { 1507 return ~(page_level_size(level) - 1); 1508 } 1509 1510 /* 1511 * The x86 doesn't have any external MMU info: the kernel page 1512 * tables contain all the necessary information. 1513 */ 1514 static inline void update_mmu_cache(struct vm_area_struct *vma, 1515 unsigned long addr, pte_t *ptep) 1516 { 1517 } 1518 static inline void update_mmu_cache_range(struct vm_fault *vmf, 1519 struct vm_area_struct *vma, unsigned long addr, 1520 pte_t *ptep, unsigned int nr) 1521 { 1522 } 1523 static inline void update_mmu_cache_pmd(struct vm_area_struct *vma, 1524 unsigned long addr, pmd_t *pmd) 1525 { 1526 } 1527 static inline void update_mmu_cache_pud(struct vm_area_struct *vma, 1528 unsigned long addr, pud_t *pud) 1529 { 1530 } 1531 static inline pte_t pte_swp_mkexclusive(pte_t pte) 1532 { 1533 return pte_set_flags(pte, _PAGE_SWP_EXCLUSIVE); 1534 } 1535 1536 static inline int pte_swp_exclusive(pte_t pte) 1537 { 1538 return pte_flags(pte) & _PAGE_SWP_EXCLUSIVE; 1539 } 1540 1541 static inline pte_t pte_swp_clear_exclusive(pte_t pte) 1542 { 1543 return pte_clear_flags(pte, _PAGE_SWP_EXCLUSIVE); 1544 } 1545 1546 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 1547 static inline pte_t pte_swp_mksoft_dirty(pte_t pte) 1548 { 1549 return pte_set_flags(pte, _PAGE_SWP_SOFT_DIRTY); 1550 } 1551 1552 static inline int pte_swp_soft_dirty(pte_t pte) 1553 { 1554 return pte_flags(pte) & _PAGE_SWP_SOFT_DIRTY; 1555 } 1556 1557 static inline pte_t pte_swp_clear_soft_dirty(pte_t pte) 1558 { 1559 return pte_clear_flags(pte, _PAGE_SWP_SOFT_DIRTY); 1560 } 1561 1562 #ifdef CONFIG_ARCH_ENABLE_THP_MIGRATION 1563 static inline pmd_t pmd_swp_mksoft_dirty(pmd_t pmd) 1564 { 1565 return pmd_set_flags(pmd, _PAGE_SWP_SOFT_DIRTY); 1566 } 1567 1568 static inline int pmd_swp_soft_dirty(pmd_t pmd) 1569 { 1570 return pmd_flags(pmd) & _PAGE_SWP_SOFT_DIRTY; 1571 } 1572 1573 static inline pmd_t pmd_swp_clear_soft_dirty(pmd_t pmd) 1574 { 1575 return pmd_clear_flags(pmd, _PAGE_SWP_SOFT_DIRTY); 1576 } 1577 #endif 1578 #endif 1579 1580 #ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP 1581 static inline pte_t pte_swp_mkuffd_wp(pte_t pte) 1582 { 1583 return pte_set_flags(pte, _PAGE_SWP_UFFD_WP); 1584 } 1585 1586 static inline int pte_swp_uffd_wp(pte_t pte) 1587 { 1588 return pte_flags(pte) & _PAGE_SWP_UFFD_WP; 1589 } 1590 1591 static inline pte_t pte_swp_clear_uffd_wp(pte_t pte) 1592 { 1593 return pte_clear_flags(pte, _PAGE_SWP_UFFD_WP); 1594 } 1595 1596 static inline pmd_t pmd_swp_mkuffd_wp(pmd_t pmd) 1597 { 1598 return pmd_set_flags(pmd, _PAGE_SWP_UFFD_WP); 1599 } 1600 1601 static inline int pmd_swp_uffd_wp(pmd_t pmd) 1602 { 1603 return pmd_flags(pmd) & _PAGE_SWP_UFFD_WP; 1604 } 1605 1606 static inline pmd_t pmd_swp_clear_uffd_wp(pmd_t pmd) 1607 { 1608 return pmd_clear_flags(pmd, _PAGE_SWP_UFFD_WP); 1609 } 1610 #endif /* CONFIG_HAVE_ARCH_USERFAULTFD_WP */ 1611 1612 static inline u16 pte_flags_pkey(unsigned long pte_flags) 1613 { 1614 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS 1615 /* ifdef to avoid doing 59-bit shift on 32-bit values */ 1616 return (pte_flags & _PAGE_PKEY_MASK) >> _PAGE_BIT_PKEY_BIT0; 1617 #else 1618 return 0; 1619 #endif 1620 } 1621 1622 static inline bool __pkru_allows_pkey(u16 pkey, bool write) 1623 { 1624 u32 pkru = read_pkru(); 1625 1626 if (!__pkru_allows_read(pkru, pkey)) 1627 return false; 1628 if (write && !__pkru_allows_write(pkru, pkey)) 1629 return false; 1630 1631 return true; 1632 } 1633 1634 /* 1635 * 'pteval' can come from a PTE, PMD or PUD. We only check 1636 * _PAGE_PRESENT, _PAGE_USER, and _PAGE_RW in here which are the 1637 * same value on all 3 types. 1638 */ 1639 static inline bool __pte_access_permitted(unsigned long pteval, bool write) 1640 { 1641 unsigned long need_pte_bits = _PAGE_PRESENT|_PAGE_USER; 1642 1643 /* 1644 * Write=0,Dirty=1 PTEs are shadow stack, which the kernel 1645 * shouldn't generally allow access to, but since they 1646 * are already Write=0, the below logic covers both cases. 1647 */ 1648 if (write) 1649 need_pte_bits |= _PAGE_RW; 1650 1651 if ((pteval & need_pte_bits) != need_pte_bits) 1652 return 0; 1653 1654 return __pkru_allows_pkey(pte_flags_pkey(pteval), write); 1655 } 1656 1657 #define pte_access_permitted pte_access_permitted 1658 static inline bool pte_access_permitted(pte_t pte, bool write) 1659 { 1660 return __pte_access_permitted(pte_val(pte), write); 1661 } 1662 1663 #define pmd_access_permitted pmd_access_permitted 1664 static inline bool pmd_access_permitted(pmd_t pmd, bool write) 1665 { 1666 return __pte_access_permitted(pmd_val(pmd), write); 1667 } 1668 1669 #define pud_access_permitted pud_access_permitted 1670 static inline bool pud_access_permitted(pud_t pud, bool write) 1671 { 1672 return __pte_access_permitted(pud_val(pud), write); 1673 } 1674 1675 #define __HAVE_ARCH_PFN_MODIFY_ALLOWED 1 1676 extern bool pfn_modify_allowed(unsigned long pfn, pgprot_t prot); 1677 1678 static inline bool arch_has_pfn_modify_check(void) 1679 { 1680 return boot_cpu_has_bug(X86_BUG_L1TF); 1681 } 1682 1683 #define arch_check_zapped_pte arch_check_zapped_pte 1684 void arch_check_zapped_pte(struct vm_area_struct *vma, pte_t pte); 1685 1686 #define arch_check_zapped_pmd arch_check_zapped_pmd 1687 void arch_check_zapped_pmd(struct vm_area_struct *vma, pmd_t pmd); 1688 1689 #ifdef CONFIG_XEN_PV 1690 #define arch_has_hw_nonleaf_pmd_young arch_has_hw_nonleaf_pmd_young 1691 static inline bool arch_has_hw_nonleaf_pmd_young(void) 1692 { 1693 return !cpu_feature_enabled(X86_FEATURE_XENPV); 1694 } 1695 #endif 1696 1697 #ifdef CONFIG_PAGE_TABLE_CHECK 1698 static inline bool pte_user_accessible_page(pte_t pte) 1699 { 1700 return (pte_val(pte) & _PAGE_PRESENT) && (pte_val(pte) & _PAGE_USER); 1701 } 1702 1703 static inline bool pmd_user_accessible_page(pmd_t pmd) 1704 { 1705 return pmd_leaf(pmd) && (pmd_val(pmd) & _PAGE_PRESENT) && (pmd_val(pmd) & _PAGE_USER); 1706 } 1707 1708 static inline bool pud_user_accessible_page(pud_t pud) 1709 { 1710 return pud_leaf(pud) && (pud_val(pud) & _PAGE_PRESENT) && (pud_val(pud) & _PAGE_USER); 1711 } 1712 #endif 1713 1714 #ifdef CONFIG_X86_SGX 1715 int arch_memory_failure(unsigned long pfn, int flags); 1716 #define arch_memory_failure arch_memory_failure 1717 1718 bool arch_is_platform_page(u64 paddr); 1719 #define arch_is_platform_page arch_is_platform_page 1720 #endif 1721 1722 #endif /* __ASSEMBLY__ */ 1723 1724 #endif /* _ASM_X86_PGTABLE_H */ 1725