1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _ASM_X86_PGTABLE_H 3 #define _ASM_X86_PGTABLE_H 4 5 #include <linux/mem_encrypt.h> 6 #include <asm/page.h> 7 #include <asm/pgtable_types.h> 8 9 /* 10 * Macro to mark a page protection value as UC- 11 */ 12 #define pgprot_noncached(prot) \ 13 ((boot_cpu_data.x86 > 3) \ 14 ? (__pgprot(pgprot_val(prot) | \ 15 cachemode2protval(_PAGE_CACHE_MODE_UC_MINUS))) \ 16 : (prot)) 17 18 /* 19 * Macros to add or remove encryption attribute 20 */ 21 #define pgprot_encrypted(prot) __pgprot(__sme_set(pgprot_val(prot))) 22 #define pgprot_decrypted(prot) __pgprot(__sme_clr(pgprot_val(prot))) 23 24 #ifndef __ASSEMBLY__ 25 #include <asm/x86_init.h> 26 #include <asm/fpu/xstate.h> 27 #include <asm/fpu/api.h> 28 #include <asm-generic/pgtable_uffd.h> 29 30 extern pgd_t early_top_pgt[PTRS_PER_PGD]; 31 int __init __early_make_pgtable(unsigned long address, pmdval_t pmd); 32 33 void ptdump_walk_pgd_level(struct seq_file *m, struct mm_struct *mm); 34 void ptdump_walk_pgd_level_debugfs(struct seq_file *m, struct mm_struct *mm, 35 bool user); 36 void ptdump_walk_pgd_level_checkwx(void); 37 void ptdump_walk_user_pgd_level_checkwx(void); 38 39 #ifdef CONFIG_DEBUG_WX 40 #define debug_checkwx() ptdump_walk_pgd_level_checkwx() 41 #define debug_checkwx_user() ptdump_walk_user_pgd_level_checkwx() 42 #else 43 #define debug_checkwx() do { } while (0) 44 #define debug_checkwx_user() do { } while (0) 45 #endif 46 47 /* 48 * ZERO_PAGE is a global shared page that is always zero: used 49 * for zero-mapped memory areas etc.. 50 */ 51 extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)] 52 __visible; 53 #define ZERO_PAGE(vaddr) ((void)(vaddr),virt_to_page(empty_zero_page)) 54 55 extern spinlock_t pgd_lock; 56 extern struct list_head pgd_list; 57 58 extern struct mm_struct *pgd_page_get_mm(struct page *page); 59 60 extern pmdval_t early_pmd_flags; 61 62 #ifdef CONFIG_PARAVIRT_XXL 63 #include <asm/paravirt.h> 64 #else /* !CONFIG_PARAVIRT_XXL */ 65 #define set_pte(ptep, pte) native_set_pte(ptep, pte) 66 #define set_pte_at(mm, addr, ptep, pte) native_set_pte_at(mm, addr, ptep, pte) 67 68 #define set_pte_atomic(ptep, pte) \ 69 native_set_pte_atomic(ptep, pte) 70 71 #define set_pmd(pmdp, pmd) native_set_pmd(pmdp, pmd) 72 73 #ifndef __PAGETABLE_P4D_FOLDED 74 #define set_pgd(pgdp, pgd) native_set_pgd(pgdp, pgd) 75 #define pgd_clear(pgd) (pgtable_l5_enabled() ? native_pgd_clear(pgd) : 0) 76 #endif 77 78 #ifndef set_p4d 79 # define set_p4d(p4dp, p4d) native_set_p4d(p4dp, p4d) 80 #endif 81 82 #ifndef __PAGETABLE_PUD_FOLDED 83 #define p4d_clear(p4d) native_p4d_clear(p4d) 84 #endif 85 86 #ifndef set_pud 87 # define set_pud(pudp, pud) native_set_pud(pudp, pud) 88 #endif 89 90 #ifndef __PAGETABLE_PUD_FOLDED 91 #define pud_clear(pud) native_pud_clear(pud) 92 #endif 93 94 #define pte_clear(mm, addr, ptep) native_pte_clear(mm, addr, ptep) 95 #define pmd_clear(pmd) native_pmd_clear(pmd) 96 97 #define pgd_val(x) native_pgd_val(x) 98 #define __pgd(x) native_make_pgd(x) 99 100 #ifndef __PAGETABLE_P4D_FOLDED 101 #define p4d_val(x) native_p4d_val(x) 102 #define __p4d(x) native_make_p4d(x) 103 #endif 104 105 #ifndef __PAGETABLE_PUD_FOLDED 106 #define pud_val(x) native_pud_val(x) 107 #define __pud(x) native_make_pud(x) 108 #endif 109 110 #ifndef __PAGETABLE_PMD_FOLDED 111 #define pmd_val(x) native_pmd_val(x) 112 #define __pmd(x) native_make_pmd(x) 113 #endif 114 115 #define pte_val(x) native_pte_val(x) 116 #define __pte(x) native_make_pte(x) 117 118 #define arch_end_context_switch(prev) do {} while(0) 119 #endif /* CONFIG_PARAVIRT_XXL */ 120 121 /* 122 * The following only work if pte_present() is true. 123 * Undefined behaviour if not.. 124 */ 125 static inline int pte_dirty(pte_t pte) 126 { 127 return pte_flags(pte) & _PAGE_DIRTY; 128 } 129 130 131 static inline u32 read_pkru(void) 132 { 133 if (boot_cpu_has(X86_FEATURE_OSPKE)) 134 return rdpkru(); 135 return 0; 136 } 137 138 static inline void write_pkru(u32 pkru) 139 { 140 struct pkru_state *pk; 141 142 if (!boot_cpu_has(X86_FEATURE_OSPKE)) 143 return; 144 145 pk = get_xsave_addr(¤t->thread.fpu.state.xsave, XFEATURE_PKRU); 146 147 /* 148 * The PKRU value in xstate needs to be in sync with the value that is 149 * written to the CPU. The FPU restore on return to userland would 150 * otherwise load the previous value again. 151 */ 152 fpregs_lock(); 153 if (pk) 154 pk->pkru = pkru; 155 __write_pkru(pkru); 156 fpregs_unlock(); 157 } 158 159 static inline int pte_young(pte_t pte) 160 { 161 return pte_flags(pte) & _PAGE_ACCESSED; 162 } 163 164 static inline int pmd_dirty(pmd_t pmd) 165 { 166 return pmd_flags(pmd) & _PAGE_DIRTY; 167 } 168 169 static inline int pmd_young(pmd_t pmd) 170 { 171 return pmd_flags(pmd) & _PAGE_ACCESSED; 172 } 173 174 static inline int pud_dirty(pud_t pud) 175 { 176 return pud_flags(pud) & _PAGE_DIRTY; 177 } 178 179 static inline int pud_young(pud_t pud) 180 { 181 return pud_flags(pud) & _PAGE_ACCESSED; 182 } 183 184 static inline int pte_write(pte_t pte) 185 { 186 return pte_flags(pte) & _PAGE_RW; 187 } 188 189 static inline int pte_huge(pte_t pte) 190 { 191 return pte_flags(pte) & _PAGE_PSE; 192 } 193 194 static inline int pte_global(pte_t pte) 195 { 196 return pte_flags(pte) & _PAGE_GLOBAL; 197 } 198 199 static inline int pte_exec(pte_t pte) 200 { 201 return !(pte_flags(pte) & _PAGE_NX); 202 } 203 204 static inline int pte_special(pte_t pte) 205 { 206 return pte_flags(pte) & _PAGE_SPECIAL; 207 } 208 209 /* Entries that were set to PROT_NONE are inverted */ 210 211 static inline u64 protnone_mask(u64 val); 212 213 static inline unsigned long pte_pfn(pte_t pte) 214 { 215 phys_addr_t pfn = pte_val(pte); 216 pfn ^= protnone_mask(pfn); 217 return (pfn & PTE_PFN_MASK) >> PAGE_SHIFT; 218 } 219 220 static inline unsigned long pmd_pfn(pmd_t pmd) 221 { 222 phys_addr_t pfn = pmd_val(pmd); 223 pfn ^= protnone_mask(pfn); 224 return (pfn & pmd_pfn_mask(pmd)) >> PAGE_SHIFT; 225 } 226 227 static inline unsigned long pud_pfn(pud_t pud) 228 { 229 phys_addr_t pfn = pud_val(pud); 230 pfn ^= protnone_mask(pfn); 231 return (pfn & pud_pfn_mask(pud)) >> PAGE_SHIFT; 232 } 233 234 static inline unsigned long p4d_pfn(p4d_t p4d) 235 { 236 return (p4d_val(p4d) & p4d_pfn_mask(p4d)) >> PAGE_SHIFT; 237 } 238 239 static inline unsigned long pgd_pfn(pgd_t pgd) 240 { 241 return (pgd_val(pgd) & PTE_PFN_MASK) >> PAGE_SHIFT; 242 } 243 244 #define p4d_leaf p4d_large 245 static inline int p4d_large(p4d_t p4d) 246 { 247 /* No 512 GiB pages yet */ 248 return 0; 249 } 250 251 #define pte_page(pte) pfn_to_page(pte_pfn(pte)) 252 253 #define pmd_leaf pmd_large 254 static inline int pmd_large(pmd_t pte) 255 { 256 return pmd_flags(pte) & _PAGE_PSE; 257 } 258 259 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 260 static inline int pmd_trans_huge(pmd_t pmd) 261 { 262 return (pmd_val(pmd) & (_PAGE_PSE|_PAGE_DEVMAP)) == _PAGE_PSE; 263 } 264 265 #ifdef CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD 266 static inline int pud_trans_huge(pud_t pud) 267 { 268 return (pud_val(pud) & (_PAGE_PSE|_PAGE_DEVMAP)) == _PAGE_PSE; 269 } 270 #endif 271 272 #define has_transparent_hugepage has_transparent_hugepage 273 static inline int has_transparent_hugepage(void) 274 { 275 return boot_cpu_has(X86_FEATURE_PSE); 276 } 277 278 #ifdef CONFIG_ARCH_HAS_PTE_DEVMAP 279 static inline int pmd_devmap(pmd_t pmd) 280 { 281 return !!(pmd_val(pmd) & _PAGE_DEVMAP); 282 } 283 284 #ifdef CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD 285 static inline int pud_devmap(pud_t pud) 286 { 287 return !!(pud_val(pud) & _PAGE_DEVMAP); 288 } 289 #else 290 static inline int pud_devmap(pud_t pud) 291 { 292 return 0; 293 } 294 #endif 295 296 static inline int pgd_devmap(pgd_t pgd) 297 { 298 return 0; 299 } 300 #endif 301 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 302 303 static inline pte_t pte_set_flags(pte_t pte, pteval_t set) 304 { 305 pteval_t v = native_pte_val(pte); 306 307 return native_make_pte(v | set); 308 } 309 310 static inline pte_t pte_clear_flags(pte_t pte, pteval_t clear) 311 { 312 pteval_t v = native_pte_val(pte); 313 314 return native_make_pte(v & ~clear); 315 } 316 317 #ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP 318 static inline int pte_uffd_wp(pte_t pte) 319 { 320 return pte_flags(pte) & _PAGE_UFFD_WP; 321 } 322 323 static inline pte_t pte_mkuffd_wp(pte_t pte) 324 { 325 return pte_set_flags(pte, _PAGE_UFFD_WP); 326 } 327 328 static inline pte_t pte_clear_uffd_wp(pte_t pte) 329 { 330 return pte_clear_flags(pte, _PAGE_UFFD_WP); 331 } 332 #endif /* CONFIG_HAVE_ARCH_USERFAULTFD_WP */ 333 334 static inline pte_t pte_mkclean(pte_t pte) 335 { 336 return pte_clear_flags(pte, _PAGE_DIRTY); 337 } 338 339 static inline pte_t pte_mkold(pte_t pte) 340 { 341 return pte_clear_flags(pte, _PAGE_ACCESSED); 342 } 343 344 static inline pte_t pte_wrprotect(pte_t pte) 345 { 346 return pte_clear_flags(pte, _PAGE_RW); 347 } 348 349 static inline pte_t pte_mkexec(pte_t pte) 350 { 351 return pte_clear_flags(pte, _PAGE_NX); 352 } 353 354 static inline pte_t pte_mkdirty(pte_t pte) 355 { 356 return pte_set_flags(pte, _PAGE_DIRTY | _PAGE_SOFT_DIRTY); 357 } 358 359 static inline pte_t pte_mkyoung(pte_t pte) 360 { 361 return pte_set_flags(pte, _PAGE_ACCESSED); 362 } 363 364 static inline pte_t pte_mkwrite(pte_t pte) 365 { 366 return pte_set_flags(pte, _PAGE_RW); 367 } 368 369 static inline pte_t pte_mkhuge(pte_t pte) 370 { 371 return pte_set_flags(pte, _PAGE_PSE); 372 } 373 374 static inline pte_t pte_clrhuge(pte_t pte) 375 { 376 return pte_clear_flags(pte, _PAGE_PSE); 377 } 378 379 static inline pte_t pte_mkglobal(pte_t pte) 380 { 381 return pte_set_flags(pte, _PAGE_GLOBAL); 382 } 383 384 static inline pte_t pte_clrglobal(pte_t pte) 385 { 386 return pte_clear_flags(pte, _PAGE_GLOBAL); 387 } 388 389 static inline pte_t pte_mkspecial(pte_t pte) 390 { 391 return pte_set_flags(pte, _PAGE_SPECIAL); 392 } 393 394 static inline pte_t pte_mkdevmap(pte_t pte) 395 { 396 return pte_set_flags(pte, _PAGE_SPECIAL|_PAGE_DEVMAP); 397 } 398 399 static inline pmd_t pmd_set_flags(pmd_t pmd, pmdval_t set) 400 { 401 pmdval_t v = native_pmd_val(pmd); 402 403 return native_make_pmd(v | set); 404 } 405 406 static inline pmd_t pmd_clear_flags(pmd_t pmd, pmdval_t clear) 407 { 408 pmdval_t v = native_pmd_val(pmd); 409 410 return native_make_pmd(v & ~clear); 411 } 412 413 #ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP 414 static inline int pmd_uffd_wp(pmd_t pmd) 415 { 416 return pmd_flags(pmd) & _PAGE_UFFD_WP; 417 } 418 419 static inline pmd_t pmd_mkuffd_wp(pmd_t pmd) 420 { 421 return pmd_set_flags(pmd, _PAGE_UFFD_WP); 422 } 423 424 static inline pmd_t pmd_clear_uffd_wp(pmd_t pmd) 425 { 426 return pmd_clear_flags(pmd, _PAGE_UFFD_WP); 427 } 428 #endif /* CONFIG_HAVE_ARCH_USERFAULTFD_WP */ 429 430 static inline pmd_t pmd_mkold(pmd_t pmd) 431 { 432 return pmd_clear_flags(pmd, _PAGE_ACCESSED); 433 } 434 435 static inline pmd_t pmd_mkclean(pmd_t pmd) 436 { 437 return pmd_clear_flags(pmd, _PAGE_DIRTY); 438 } 439 440 static inline pmd_t pmd_wrprotect(pmd_t pmd) 441 { 442 return pmd_clear_flags(pmd, _PAGE_RW); 443 } 444 445 static inline pmd_t pmd_mkdirty(pmd_t pmd) 446 { 447 return pmd_set_flags(pmd, _PAGE_DIRTY | _PAGE_SOFT_DIRTY); 448 } 449 450 static inline pmd_t pmd_mkdevmap(pmd_t pmd) 451 { 452 return pmd_set_flags(pmd, _PAGE_DEVMAP); 453 } 454 455 static inline pmd_t pmd_mkhuge(pmd_t pmd) 456 { 457 return pmd_set_flags(pmd, _PAGE_PSE); 458 } 459 460 static inline pmd_t pmd_mkyoung(pmd_t pmd) 461 { 462 return pmd_set_flags(pmd, _PAGE_ACCESSED); 463 } 464 465 static inline pmd_t pmd_mkwrite(pmd_t pmd) 466 { 467 return pmd_set_flags(pmd, _PAGE_RW); 468 } 469 470 static inline pud_t pud_set_flags(pud_t pud, pudval_t set) 471 { 472 pudval_t v = native_pud_val(pud); 473 474 return native_make_pud(v | set); 475 } 476 477 static inline pud_t pud_clear_flags(pud_t pud, pudval_t clear) 478 { 479 pudval_t v = native_pud_val(pud); 480 481 return native_make_pud(v & ~clear); 482 } 483 484 static inline pud_t pud_mkold(pud_t pud) 485 { 486 return pud_clear_flags(pud, _PAGE_ACCESSED); 487 } 488 489 static inline pud_t pud_mkclean(pud_t pud) 490 { 491 return pud_clear_flags(pud, _PAGE_DIRTY); 492 } 493 494 static inline pud_t pud_wrprotect(pud_t pud) 495 { 496 return pud_clear_flags(pud, _PAGE_RW); 497 } 498 499 static inline pud_t pud_mkdirty(pud_t pud) 500 { 501 return pud_set_flags(pud, _PAGE_DIRTY | _PAGE_SOFT_DIRTY); 502 } 503 504 static inline pud_t pud_mkdevmap(pud_t pud) 505 { 506 return pud_set_flags(pud, _PAGE_DEVMAP); 507 } 508 509 static inline pud_t pud_mkhuge(pud_t pud) 510 { 511 return pud_set_flags(pud, _PAGE_PSE); 512 } 513 514 static inline pud_t pud_mkyoung(pud_t pud) 515 { 516 return pud_set_flags(pud, _PAGE_ACCESSED); 517 } 518 519 static inline pud_t pud_mkwrite(pud_t pud) 520 { 521 return pud_set_flags(pud, _PAGE_RW); 522 } 523 524 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 525 static inline int pte_soft_dirty(pte_t pte) 526 { 527 return pte_flags(pte) & _PAGE_SOFT_DIRTY; 528 } 529 530 static inline int pmd_soft_dirty(pmd_t pmd) 531 { 532 return pmd_flags(pmd) & _PAGE_SOFT_DIRTY; 533 } 534 535 static inline int pud_soft_dirty(pud_t pud) 536 { 537 return pud_flags(pud) & _PAGE_SOFT_DIRTY; 538 } 539 540 static inline pte_t pte_mksoft_dirty(pte_t pte) 541 { 542 return pte_set_flags(pte, _PAGE_SOFT_DIRTY); 543 } 544 545 static inline pmd_t pmd_mksoft_dirty(pmd_t pmd) 546 { 547 return pmd_set_flags(pmd, _PAGE_SOFT_DIRTY); 548 } 549 550 static inline pud_t pud_mksoft_dirty(pud_t pud) 551 { 552 return pud_set_flags(pud, _PAGE_SOFT_DIRTY); 553 } 554 555 static inline pte_t pte_clear_soft_dirty(pte_t pte) 556 { 557 return pte_clear_flags(pte, _PAGE_SOFT_DIRTY); 558 } 559 560 static inline pmd_t pmd_clear_soft_dirty(pmd_t pmd) 561 { 562 return pmd_clear_flags(pmd, _PAGE_SOFT_DIRTY); 563 } 564 565 static inline pud_t pud_clear_soft_dirty(pud_t pud) 566 { 567 return pud_clear_flags(pud, _PAGE_SOFT_DIRTY); 568 } 569 570 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ 571 572 /* 573 * Mask out unsupported bits in a present pgprot. Non-present pgprots 574 * can use those bits for other purposes, so leave them be. 575 */ 576 static inline pgprotval_t massage_pgprot(pgprot_t pgprot) 577 { 578 pgprotval_t protval = pgprot_val(pgprot); 579 580 if (protval & _PAGE_PRESENT) 581 protval &= __supported_pte_mask; 582 583 return protval; 584 } 585 586 static inline pgprotval_t check_pgprot(pgprot_t pgprot) 587 { 588 pgprotval_t massaged_val = massage_pgprot(pgprot); 589 590 /* mmdebug.h can not be included here because of dependencies */ 591 #ifdef CONFIG_DEBUG_VM 592 WARN_ONCE(pgprot_val(pgprot) != massaged_val, 593 "attempted to set unsupported pgprot: %016llx " 594 "bits: %016llx supported: %016llx\n", 595 (u64)pgprot_val(pgprot), 596 (u64)pgprot_val(pgprot) ^ massaged_val, 597 (u64)__supported_pte_mask); 598 #endif 599 600 return massaged_val; 601 } 602 603 static inline pte_t pfn_pte(unsigned long page_nr, pgprot_t pgprot) 604 { 605 phys_addr_t pfn = (phys_addr_t)page_nr << PAGE_SHIFT; 606 pfn ^= protnone_mask(pgprot_val(pgprot)); 607 pfn &= PTE_PFN_MASK; 608 return __pte(pfn | check_pgprot(pgprot)); 609 } 610 611 static inline pmd_t pfn_pmd(unsigned long page_nr, pgprot_t pgprot) 612 { 613 phys_addr_t pfn = (phys_addr_t)page_nr << PAGE_SHIFT; 614 pfn ^= protnone_mask(pgprot_val(pgprot)); 615 pfn &= PHYSICAL_PMD_PAGE_MASK; 616 return __pmd(pfn | check_pgprot(pgprot)); 617 } 618 619 static inline pud_t pfn_pud(unsigned long page_nr, pgprot_t pgprot) 620 { 621 phys_addr_t pfn = (phys_addr_t)page_nr << PAGE_SHIFT; 622 pfn ^= protnone_mask(pgprot_val(pgprot)); 623 pfn &= PHYSICAL_PUD_PAGE_MASK; 624 return __pud(pfn | check_pgprot(pgprot)); 625 } 626 627 static inline pmd_t pmd_mknotpresent(pmd_t pmd) 628 { 629 return pfn_pmd(pmd_pfn(pmd), 630 __pgprot(pmd_flags(pmd) & ~(_PAGE_PRESENT|_PAGE_PROTNONE))); 631 } 632 633 static inline u64 flip_protnone_guard(u64 oldval, u64 val, u64 mask); 634 635 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 636 { 637 pteval_t val = pte_val(pte), oldval = val; 638 639 /* 640 * Chop off the NX bit (if present), and add the NX portion of 641 * the newprot (if present): 642 */ 643 val &= _PAGE_CHG_MASK; 644 val |= check_pgprot(newprot) & ~_PAGE_CHG_MASK; 645 val = flip_protnone_guard(oldval, val, PTE_PFN_MASK); 646 return __pte(val); 647 } 648 649 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) 650 { 651 pmdval_t val = pmd_val(pmd), oldval = val; 652 653 val &= _HPAGE_CHG_MASK; 654 val |= check_pgprot(newprot) & ~_HPAGE_CHG_MASK; 655 val = flip_protnone_guard(oldval, val, PHYSICAL_PMD_PAGE_MASK); 656 return __pmd(val); 657 } 658 659 /* 660 * mprotect needs to preserve PAT and encryption bits when updating 661 * vm_page_prot 662 */ 663 #define pgprot_modify pgprot_modify 664 static inline pgprot_t pgprot_modify(pgprot_t oldprot, pgprot_t newprot) 665 { 666 pgprotval_t preservebits = pgprot_val(oldprot) & _PAGE_CHG_MASK; 667 pgprotval_t addbits = pgprot_val(newprot) & ~_PAGE_CHG_MASK; 668 return __pgprot(preservebits | addbits); 669 } 670 671 #define pte_pgprot(x) __pgprot(pte_flags(x)) 672 #define pmd_pgprot(x) __pgprot(pmd_flags(x)) 673 #define pud_pgprot(x) __pgprot(pud_flags(x)) 674 #define p4d_pgprot(x) __pgprot(p4d_flags(x)) 675 676 #define canon_pgprot(p) __pgprot(massage_pgprot(p)) 677 678 static inline pgprot_t arch_filter_pgprot(pgprot_t prot) 679 { 680 return canon_pgprot(prot); 681 } 682 683 static inline int is_new_memtype_allowed(u64 paddr, unsigned long size, 684 enum page_cache_mode pcm, 685 enum page_cache_mode new_pcm) 686 { 687 /* 688 * PAT type is always WB for untracked ranges, so no need to check. 689 */ 690 if (x86_platform.is_untracked_pat_range(paddr, paddr + size)) 691 return 1; 692 693 /* 694 * Certain new memtypes are not allowed with certain 695 * requested memtype: 696 * - request is uncached, return cannot be write-back 697 * - request is write-combine, return cannot be write-back 698 * - request is write-through, return cannot be write-back 699 * - request is write-through, return cannot be write-combine 700 */ 701 if ((pcm == _PAGE_CACHE_MODE_UC_MINUS && 702 new_pcm == _PAGE_CACHE_MODE_WB) || 703 (pcm == _PAGE_CACHE_MODE_WC && 704 new_pcm == _PAGE_CACHE_MODE_WB) || 705 (pcm == _PAGE_CACHE_MODE_WT && 706 new_pcm == _PAGE_CACHE_MODE_WB) || 707 (pcm == _PAGE_CACHE_MODE_WT && 708 new_pcm == _PAGE_CACHE_MODE_WC)) { 709 return 0; 710 } 711 712 return 1; 713 } 714 715 pmd_t *populate_extra_pmd(unsigned long vaddr); 716 pte_t *populate_extra_pte(unsigned long vaddr); 717 718 #ifdef CONFIG_PAGE_TABLE_ISOLATION 719 pgd_t __pti_set_user_pgtbl(pgd_t *pgdp, pgd_t pgd); 720 721 /* 722 * Take a PGD location (pgdp) and a pgd value that needs to be set there. 723 * Populates the user and returns the resulting PGD that must be set in 724 * the kernel copy of the page tables. 725 */ 726 static inline pgd_t pti_set_user_pgtbl(pgd_t *pgdp, pgd_t pgd) 727 { 728 if (!static_cpu_has(X86_FEATURE_PTI)) 729 return pgd; 730 return __pti_set_user_pgtbl(pgdp, pgd); 731 } 732 #else /* CONFIG_PAGE_TABLE_ISOLATION */ 733 static inline pgd_t pti_set_user_pgtbl(pgd_t *pgdp, pgd_t pgd) 734 { 735 return pgd; 736 } 737 #endif /* CONFIG_PAGE_TABLE_ISOLATION */ 738 739 #endif /* __ASSEMBLY__ */ 740 741 742 #ifdef CONFIG_X86_32 743 # include <asm/pgtable_32.h> 744 #else 745 # include <asm/pgtable_64.h> 746 #endif 747 748 #ifndef __ASSEMBLY__ 749 #include <linux/mm_types.h> 750 #include <linux/mmdebug.h> 751 #include <linux/log2.h> 752 #include <asm/fixmap.h> 753 754 static inline int pte_none(pte_t pte) 755 { 756 return !(pte.pte & ~(_PAGE_KNL_ERRATUM_MASK)); 757 } 758 759 #define __HAVE_ARCH_PTE_SAME 760 static inline int pte_same(pte_t a, pte_t b) 761 { 762 return a.pte == b.pte; 763 } 764 765 static inline int pte_present(pte_t a) 766 { 767 return pte_flags(a) & (_PAGE_PRESENT | _PAGE_PROTNONE); 768 } 769 770 #ifdef CONFIG_ARCH_HAS_PTE_DEVMAP 771 static inline int pte_devmap(pte_t a) 772 { 773 return (pte_flags(a) & _PAGE_DEVMAP) == _PAGE_DEVMAP; 774 } 775 #endif 776 777 #define pte_accessible pte_accessible 778 static inline bool pte_accessible(struct mm_struct *mm, pte_t a) 779 { 780 if (pte_flags(a) & _PAGE_PRESENT) 781 return true; 782 783 if ((pte_flags(a) & _PAGE_PROTNONE) && 784 mm_tlb_flush_pending(mm)) 785 return true; 786 787 return false; 788 } 789 790 static inline int pmd_present(pmd_t pmd) 791 { 792 /* 793 * Checking for _PAGE_PSE is needed too because 794 * split_huge_page will temporarily clear the present bit (but 795 * the _PAGE_PSE flag will remain set at all times while the 796 * _PAGE_PRESENT bit is clear). 797 */ 798 return pmd_flags(pmd) & (_PAGE_PRESENT | _PAGE_PROTNONE | _PAGE_PSE); 799 } 800 801 #ifdef CONFIG_NUMA_BALANCING 802 /* 803 * These work without NUMA balancing but the kernel does not care. See the 804 * comment in include/asm-generic/pgtable.h 805 */ 806 static inline int pte_protnone(pte_t pte) 807 { 808 return (pte_flags(pte) & (_PAGE_PROTNONE | _PAGE_PRESENT)) 809 == _PAGE_PROTNONE; 810 } 811 812 static inline int pmd_protnone(pmd_t pmd) 813 { 814 return (pmd_flags(pmd) & (_PAGE_PROTNONE | _PAGE_PRESENT)) 815 == _PAGE_PROTNONE; 816 } 817 #endif /* CONFIG_NUMA_BALANCING */ 818 819 static inline int pmd_none(pmd_t pmd) 820 { 821 /* Only check low word on 32-bit platforms, since it might be 822 out of sync with upper half. */ 823 unsigned long val = native_pmd_val(pmd); 824 return (val & ~_PAGE_KNL_ERRATUM_MASK) == 0; 825 } 826 827 static inline unsigned long pmd_page_vaddr(pmd_t pmd) 828 { 829 return (unsigned long)__va(pmd_val(pmd) & pmd_pfn_mask(pmd)); 830 } 831 832 /* 833 * Currently stuck as a macro due to indirect forward reference to 834 * linux/mmzone.h's __section_mem_map_addr() definition: 835 */ 836 #define pmd_page(pmd) pfn_to_page(pmd_pfn(pmd)) 837 838 /* 839 * the pmd page can be thought of an array like this: pmd_t[PTRS_PER_PMD] 840 * 841 * this macro returns the index of the entry in the pmd page which would 842 * control the given virtual address 843 */ 844 static inline unsigned long pmd_index(unsigned long address) 845 { 846 return (address >> PMD_SHIFT) & (PTRS_PER_PMD - 1); 847 } 848 849 /* 850 * Conversion functions: convert a page and protection to a page entry, 851 * and a page entry and page directory to the page they refer to. 852 * 853 * (Currently stuck as a macro because of indirect forward reference 854 * to linux/mm.h:page_to_nid()) 855 */ 856 #define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot)) 857 858 /* 859 * the pte page can be thought of an array like this: pte_t[PTRS_PER_PTE] 860 * 861 * this function returns the index of the entry in the pte page which would 862 * control the given virtual address 863 */ 864 static inline unsigned long pte_index(unsigned long address) 865 { 866 return (address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1); 867 } 868 869 static inline pte_t *pte_offset_kernel(pmd_t *pmd, unsigned long address) 870 { 871 return (pte_t *)pmd_page_vaddr(*pmd) + pte_index(address); 872 } 873 874 static inline int pmd_bad(pmd_t pmd) 875 { 876 return (pmd_flags(pmd) & ~_PAGE_USER) != _KERNPG_TABLE; 877 } 878 879 static inline unsigned long pages_to_mb(unsigned long npg) 880 { 881 return npg >> (20 - PAGE_SHIFT); 882 } 883 884 #if CONFIG_PGTABLE_LEVELS > 2 885 static inline int pud_none(pud_t pud) 886 { 887 return (native_pud_val(pud) & ~(_PAGE_KNL_ERRATUM_MASK)) == 0; 888 } 889 890 static inline int pud_present(pud_t pud) 891 { 892 return pud_flags(pud) & _PAGE_PRESENT; 893 } 894 895 static inline unsigned long pud_page_vaddr(pud_t pud) 896 { 897 return (unsigned long)__va(pud_val(pud) & pud_pfn_mask(pud)); 898 } 899 900 /* 901 * Currently stuck as a macro due to indirect forward reference to 902 * linux/mmzone.h's __section_mem_map_addr() definition: 903 */ 904 #define pud_page(pud) pfn_to_page(pud_pfn(pud)) 905 906 /* Find an entry in the second-level page table.. */ 907 static inline pmd_t *pmd_offset(pud_t *pud, unsigned long address) 908 { 909 return (pmd_t *)pud_page_vaddr(*pud) + pmd_index(address); 910 } 911 912 #define pud_leaf pud_large 913 static inline int pud_large(pud_t pud) 914 { 915 return (pud_val(pud) & (_PAGE_PSE | _PAGE_PRESENT)) == 916 (_PAGE_PSE | _PAGE_PRESENT); 917 } 918 919 static inline int pud_bad(pud_t pud) 920 { 921 return (pud_flags(pud) & ~(_KERNPG_TABLE | _PAGE_USER)) != 0; 922 } 923 #else 924 #define pud_leaf pud_large 925 static inline int pud_large(pud_t pud) 926 { 927 return 0; 928 } 929 #endif /* CONFIG_PGTABLE_LEVELS > 2 */ 930 931 static inline unsigned long pud_index(unsigned long address) 932 { 933 return (address >> PUD_SHIFT) & (PTRS_PER_PUD - 1); 934 } 935 936 #if CONFIG_PGTABLE_LEVELS > 3 937 static inline int p4d_none(p4d_t p4d) 938 { 939 return (native_p4d_val(p4d) & ~(_PAGE_KNL_ERRATUM_MASK)) == 0; 940 } 941 942 static inline int p4d_present(p4d_t p4d) 943 { 944 return p4d_flags(p4d) & _PAGE_PRESENT; 945 } 946 947 static inline unsigned long p4d_page_vaddr(p4d_t p4d) 948 { 949 return (unsigned long)__va(p4d_val(p4d) & p4d_pfn_mask(p4d)); 950 } 951 952 /* 953 * Currently stuck as a macro due to indirect forward reference to 954 * linux/mmzone.h's __section_mem_map_addr() definition: 955 */ 956 #define p4d_page(p4d) pfn_to_page(p4d_pfn(p4d)) 957 958 /* Find an entry in the third-level page table.. */ 959 static inline pud_t *pud_offset(p4d_t *p4d, unsigned long address) 960 { 961 return (pud_t *)p4d_page_vaddr(*p4d) + pud_index(address); 962 } 963 964 static inline int p4d_bad(p4d_t p4d) 965 { 966 unsigned long ignore_flags = _KERNPG_TABLE | _PAGE_USER; 967 968 if (IS_ENABLED(CONFIG_PAGE_TABLE_ISOLATION)) 969 ignore_flags |= _PAGE_NX; 970 971 return (p4d_flags(p4d) & ~ignore_flags) != 0; 972 } 973 #endif /* CONFIG_PGTABLE_LEVELS > 3 */ 974 975 static inline unsigned long p4d_index(unsigned long address) 976 { 977 return (address >> P4D_SHIFT) & (PTRS_PER_P4D - 1); 978 } 979 980 #if CONFIG_PGTABLE_LEVELS > 4 981 static inline int pgd_present(pgd_t pgd) 982 { 983 if (!pgtable_l5_enabled()) 984 return 1; 985 return pgd_flags(pgd) & _PAGE_PRESENT; 986 } 987 988 static inline unsigned long pgd_page_vaddr(pgd_t pgd) 989 { 990 return (unsigned long)__va((unsigned long)pgd_val(pgd) & PTE_PFN_MASK); 991 } 992 993 /* 994 * Currently stuck as a macro due to indirect forward reference to 995 * linux/mmzone.h's __section_mem_map_addr() definition: 996 */ 997 #define pgd_page(pgd) pfn_to_page(pgd_pfn(pgd)) 998 999 /* to find an entry in a page-table-directory. */ 1000 static inline p4d_t *p4d_offset(pgd_t *pgd, unsigned long address) 1001 { 1002 if (!pgtable_l5_enabled()) 1003 return (p4d_t *)pgd; 1004 return (p4d_t *)pgd_page_vaddr(*pgd) + p4d_index(address); 1005 } 1006 1007 static inline int pgd_bad(pgd_t pgd) 1008 { 1009 unsigned long ignore_flags = _PAGE_USER; 1010 1011 if (!pgtable_l5_enabled()) 1012 return 0; 1013 1014 if (IS_ENABLED(CONFIG_PAGE_TABLE_ISOLATION)) 1015 ignore_flags |= _PAGE_NX; 1016 1017 return (pgd_flags(pgd) & ~ignore_flags) != _KERNPG_TABLE; 1018 } 1019 1020 static inline int pgd_none(pgd_t pgd) 1021 { 1022 if (!pgtable_l5_enabled()) 1023 return 0; 1024 /* 1025 * There is no need to do a workaround for the KNL stray 1026 * A/D bit erratum here. PGDs only point to page tables 1027 * except on 32-bit non-PAE which is not supported on 1028 * KNL. 1029 */ 1030 return !native_pgd_val(pgd); 1031 } 1032 #endif /* CONFIG_PGTABLE_LEVELS > 4 */ 1033 1034 #endif /* __ASSEMBLY__ */ 1035 1036 /* 1037 * the pgd page can be thought of an array like this: pgd_t[PTRS_PER_PGD] 1038 * 1039 * this macro returns the index of the entry in the pgd page which would 1040 * control the given virtual address 1041 */ 1042 #define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1)) 1043 1044 /* 1045 * pgd_offset() returns a (pgd_t *) 1046 * pgd_index() is used get the offset into the pgd page's array of pgd_t's; 1047 */ 1048 #define pgd_offset_pgd(pgd, address) (pgd + pgd_index((address))) 1049 /* 1050 * a shortcut to get a pgd_t in a given mm 1051 */ 1052 #define pgd_offset(mm, address) pgd_offset_pgd((mm)->pgd, (address)) 1053 /* 1054 * a shortcut which implies the use of the kernel's pgd, instead 1055 * of a process's 1056 */ 1057 #define pgd_offset_k(address) pgd_offset(&init_mm, (address)) 1058 1059 1060 #define KERNEL_PGD_BOUNDARY pgd_index(PAGE_OFFSET) 1061 #define KERNEL_PGD_PTRS (PTRS_PER_PGD - KERNEL_PGD_BOUNDARY) 1062 1063 #ifndef __ASSEMBLY__ 1064 1065 extern int direct_gbpages; 1066 void init_mem_mapping(void); 1067 void early_alloc_pgt_buf(void); 1068 extern void memblock_find_dma_reserve(void); 1069 1070 #ifdef CONFIG_X86_64 1071 /* Realmode trampoline initialization. */ 1072 extern pgd_t trampoline_pgd_entry; 1073 static inline void __meminit init_trampoline_default(void) 1074 { 1075 /* Default trampoline pgd value */ 1076 trampoline_pgd_entry = init_top_pgt[pgd_index(__PAGE_OFFSET)]; 1077 } 1078 1079 void __init poking_init(void); 1080 1081 # ifdef CONFIG_RANDOMIZE_MEMORY 1082 void __meminit init_trampoline(void); 1083 # else 1084 # define init_trampoline init_trampoline_default 1085 # endif 1086 #else 1087 static inline void init_trampoline(void) { } 1088 #endif 1089 1090 /* local pte updates need not use xchg for locking */ 1091 static inline pte_t native_local_ptep_get_and_clear(pte_t *ptep) 1092 { 1093 pte_t res = *ptep; 1094 1095 /* Pure native function needs no input for mm, addr */ 1096 native_pte_clear(NULL, 0, ptep); 1097 return res; 1098 } 1099 1100 static inline pmd_t native_local_pmdp_get_and_clear(pmd_t *pmdp) 1101 { 1102 pmd_t res = *pmdp; 1103 1104 native_pmd_clear(pmdp); 1105 return res; 1106 } 1107 1108 static inline pud_t native_local_pudp_get_and_clear(pud_t *pudp) 1109 { 1110 pud_t res = *pudp; 1111 1112 native_pud_clear(pudp); 1113 return res; 1114 } 1115 1116 static inline void native_set_pte_at(struct mm_struct *mm, unsigned long addr, 1117 pte_t *ptep , pte_t pte) 1118 { 1119 native_set_pte(ptep, pte); 1120 } 1121 1122 static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr, 1123 pmd_t *pmdp, pmd_t pmd) 1124 { 1125 set_pmd(pmdp, pmd); 1126 } 1127 1128 static inline void set_pud_at(struct mm_struct *mm, unsigned long addr, 1129 pud_t *pudp, pud_t pud) 1130 { 1131 native_set_pud(pudp, pud); 1132 } 1133 1134 /* 1135 * We only update the dirty/accessed state if we set 1136 * the dirty bit by hand in the kernel, since the hardware 1137 * will do the accessed bit for us, and we don't want to 1138 * race with other CPU's that might be updating the dirty 1139 * bit at the same time. 1140 */ 1141 struct vm_area_struct; 1142 1143 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 1144 extern int ptep_set_access_flags(struct vm_area_struct *vma, 1145 unsigned long address, pte_t *ptep, 1146 pte_t entry, int dirty); 1147 1148 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 1149 extern int ptep_test_and_clear_young(struct vm_area_struct *vma, 1150 unsigned long addr, pte_t *ptep); 1151 1152 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 1153 extern int ptep_clear_flush_young(struct vm_area_struct *vma, 1154 unsigned long address, pte_t *ptep); 1155 1156 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 1157 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, 1158 pte_t *ptep) 1159 { 1160 pte_t pte = native_ptep_get_and_clear(ptep); 1161 return pte; 1162 } 1163 1164 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL 1165 static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm, 1166 unsigned long addr, pte_t *ptep, 1167 int full) 1168 { 1169 pte_t pte; 1170 if (full) { 1171 /* 1172 * Full address destruction in progress; paravirt does not 1173 * care about updates and native needs no locking 1174 */ 1175 pte = native_local_ptep_get_and_clear(ptep); 1176 } else { 1177 pte = ptep_get_and_clear(mm, addr, ptep); 1178 } 1179 return pte; 1180 } 1181 1182 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 1183 static inline void ptep_set_wrprotect(struct mm_struct *mm, 1184 unsigned long addr, pte_t *ptep) 1185 { 1186 clear_bit(_PAGE_BIT_RW, (unsigned long *)&ptep->pte); 1187 } 1188 1189 #define flush_tlb_fix_spurious_fault(vma, address) do { } while (0) 1190 1191 #define mk_pmd(page, pgprot) pfn_pmd(page_to_pfn(page), (pgprot)) 1192 1193 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 1194 extern int pmdp_set_access_flags(struct vm_area_struct *vma, 1195 unsigned long address, pmd_t *pmdp, 1196 pmd_t entry, int dirty); 1197 extern int pudp_set_access_flags(struct vm_area_struct *vma, 1198 unsigned long address, pud_t *pudp, 1199 pud_t entry, int dirty); 1200 1201 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 1202 extern int pmdp_test_and_clear_young(struct vm_area_struct *vma, 1203 unsigned long addr, pmd_t *pmdp); 1204 extern int pudp_test_and_clear_young(struct vm_area_struct *vma, 1205 unsigned long addr, pud_t *pudp); 1206 1207 #define __HAVE_ARCH_PMDP_CLEAR_YOUNG_FLUSH 1208 extern int pmdp_clear_flush_young(struct vm_area_struct *vma, 1209 unsigned long address, pmd_t *pmdp); 1210 1211 1212 #define pmd_write pmd_write 1213 static inline int pmd_write(pmd_t pmd) 1214 { 1215 return pmd_flags(pmd) & _PAGE_RW; 1216 } 1217 1218 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 1219 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, unsigned long addr, 1220 pmd_t *pmdp) 1221 { 1222 return native_pmdp_get_and_clear(pmdp); 1223 } 1224 1225 #define __HAVE_ARCH_PUDP_HUGE_GET_AND_CLEAR 1226 static inline pud_t pudp_huge_get_and_clear(struct mm_struct *mm, 1227 unsigned long addr, pud_t *pudp) 1228 { 1229 return native_pudp_get_and_clear(pudp); 1230 } 1231 1232 #define __HAVE_ARCH_PMDP_SET_WRPROTECT 1233 static inline void pmdp_set_wrprotect(struct mm_struct *mm, 1234 unsigned long addr, pmd_t *pmdp) 1235 { 1236 clear_bit(_PAGE_BIT_RW, (unsigned long *)pmdp); 1237 } 1238 1239 #define pud_write pud_write 1240 static inline int pud_write(pud_t pud) 1241 { 1242 return pud_flags(pud) & _PAGE_RW; 1243 } 1244 1245 #ifndef pmdp_establish 1246 #define pmdp_establish pmdp_establish 1247 static inline pmd_t pmdp_establish(struct vm_area_struct *vma, 1248 unsigned long address, pmd_t *pmdp, pmd_t pmd) 1249 { 1250 if (IS_ENABLED(CONFIG_SMP)) { 1251 return xchg(pmdp, pmd); 1252 } else { 1253 pmd_t old = *pmdp; 1254 WRITE_ONCE(*pmdp, pmd); 1255 return old; 1256 } 1257 } 1258 #endif 1259 /* 1260 * Page table pages are page-aligned. The lower half of the top 1261 * level is used for userspace and the top half for the kernel. 1262 * 1263 * Returns true for parts of the PGD that map userspace and 1264 * false for the parts that map the kernel. 1265 */ 1266 static inline bool pgdp_maps_userspace(void *__ptr) 1267 { 1268 unsigned long ptr = (unsigned long)__ptr; 1269 1270 return (((ptr & ~PAGE_MASK) / sizeof(pgd_t)) < PGD_KERNEL_START); 1271 } 1272 1273 #define pgd_leaf pgd_large 1274 static inline int pgd_large(pgd_t pgd) { return 0; } 1275 1276 #ifdef CONFIG_PAGE_TABLE_ISOLATION 1277 /* 1278 * All top-level PAGE_TABLE_ISOLATION page tables are order-1 pages 1279 * (8k-aligned and 8k in size). The kernel one is at the beginning 4k and 1280 * the user one is in the last 4k. To switch between them, you 1281 * just need to flip the 12th bit in their addresses. 1282 */ 1283 #define PTI_PGTABLE_SWITCH_BIT PAGE_SHIFT 1284 1285 /* 1286 * This generates better code than the inline assembly in 1287 * __set_bit(). 1288 */ 1289 static inline void *ptr_set_bit(void *ptr, int bit) 1290 { 1291 unsigned long __ptr = (unsigned long)ptr; 1292 1293 __ptr |= BIT(bit); 1294 return (void *)__ptr; 1295 } 1296 static inline void *ptr_clear_bit(void *ptr, int bit) 1297 { 1298 unsigned long __ptr = (unsigned long)ptr; 1299 1300 __ptr &= ~BIT(bit); 1301 return (void *)__ptr; 1302 } 1303 1304 static inline pgd_t *kernel_to_user_pgdp(pgd_t *pgdp) 1305 { 1306 return ptr_set_bit(pgdp, PTI_PGTABLE_SWITCH_BIT); 1307 } 1308 1309 static inline pgd_t *user_to_kernel_pgdp(pgd_t *pgdp) 1310 { 1311 return ptr_clear_bit(pgdp, PTI_PGTABLE_SWITCH_BIT); 1312 } 1313 1314 static inline p4d_t *kernel_to_user_p4dp(p4d_t *p4dp) 1315 { 1316 return ptr_set_bit(p4dp, PTI_PGTABLE_SWITCH_BIT); 1317 } 1318 1319 static inline p4d_t *user_to_kernel_p4dp(p4d_t *p4dp) 1320 { 1321 return ptr_clear_bit(p4dp, PTI_PGTABLE_SWITCH_BIT); 1322 } 1323 #endif /* CONFIG_PAGE_TABLE_ISOLATION */ 1324 1325 /* 1326 * clone_pgd_range(pgd_t *dst, pgd_t *src, int count); 1327 * 1328 * dst - pointer to pgd range anwhere on a pgd page 1329 * src - "" 1330 * count - the number of pgds to copy. 1331 * 1332 * dst and src can be on the same page, but the range must not overlap, 1333 * and must not cross a page boundary. 1334 */ 1335 static inline void clone_pgd_range(pgd_t *dst, pgd_t *src, int count) 1336 { 1337 memcpy(dst, src, count * sizeof(pgd_t)); 1338 #ifdef CONFIG_PAGE_TABLE_ISOLATION 1339 if (!static_cpu_has(X86_FEATURE_PTI)) 1340 return; 1341 /* Clone the user space pgd as well */ 1342 memcpy(kernel_to_user_pgdp(dst), kernel_to_user_pgdp(src), 1343 count * sizeof(pgd_t)); 1344 #endif 1345 } 1346 1347 #define PTE_SHIFT ilog2(PTRS_PER_PTE) 1348 static inline int page_level_shift(enum pg_level level) 1349 { 1350 return (PAGE_SHIFT - PTE_SHIFT) + level * PTE_SHIFT; 1351 } 1352 static inline unsigned long page_level_size(enum pg_level level) 1353 { 1354 return 1UL << page_level_shift(level); 1355 } 1356 static inline unsigned long page_level_mask(enum pg_level level) 1357 { 1358 return ~(page_level_size(level) - 1); 1359 } 1360 1361 /* 1362 * The x86 doesn't have any external MMU info: the kernel page 1363 * tables contain all the necessary information. 1364 */ 1365 static inline void update_mmu_cache(struct vm_area_struct *vma, 1366 unsigned long addr, pte_t *ptep) 1367 { 1368 } 1369 static inline void update_mmu_cache_pmd(struct vm_area_struct *vma, 1370 unsigned long addr, pmd_t *pmd) 1371 { 1372 } 1373 static inline void update_mmu_cache_pud(struct vm_area_struct *vma, 1374 unsigned long addr, pud_t *pud) 1375 { 1376 } 1377 1378 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 1379 static inline pte_t pte_swp_mksoft_dirty(pte_t pte) 1380 { 1381 return pte_set_flags(pte, _PAGE_SWP_SOFT_DIRTY); 1382 } 1383 1384 static inline int pte_swp_soft_dirty(pte_t pte) 1385 { 1386 return pte_flags(pte) & _PAGE_SWP_SOFT_DIRTY; 1387 } 1388 1389 static inline pte_t pte_swp_clear_soft_dirty(pte_t pte) 1390 { 1391 return pte_clear_flags(pte, _PAGE_SWP_SOFT_DIRTY); 1392 } 1393 1394 #ifdef CONFIG_ARCH_ENABLE_THP_MIGRATION 1395 static inline pmd_t pmd_swp_mksoft_dirty(pmd_t pmd) 1396 { 1397 return pmd_set_flags(pmd, _PAGE_SWP_SOFT_DIRTY); 1398 } 1399 1400 static inline int pmd_swp_soft_dirty(pmd_t pmd) 1401 { 1402 return pmd_flags(pmd) & _PAGE_SWP_SOFT_DIRTY; 1403 } 1404 1405 static inline pmd_t pmd_swp_clear_soft_dirty(pmd_t pmd) 1406 { 1407 return pmd_clear_flags(pmd, _PAGE_SWP_SOFT_DIRTY); 1408 } 1409 #endif 1410 #endif 1411 1412 #ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP 1413 static inline pte_t pte_swp_mkuffd_wp(pte_t pte) 1414 { 1415 return pte_set_flags(pte, _PAGE_SWP_UFFD_WP); 1416 } 1417 1418 static inline int pte_swp_uffd_wp(pte_t pte) 1419 { 1420 return pte_flags(pte) & _PAGE_SWP_UFFD_WP; 1421 } 1422 1423 static inline pte_t pte_swp_clear_uffd_wp(pte_t pte) 1424 { 1425 return pte_clear_flags(pte, _PAGE_SWP_UFFD_WP); 1426 } 1427 1428 static inline pmd_t pmd_swp_mkuffd_wp(pmd_t pmd) 1429 { 1430 return pmd_set_flags(pmd, _PAGE_SWP_UFFD_WP); 1431 } 1432 1433 static inline int pmd_swp_uffd_wp(pmd_t pmd) 1434 { 1435 return pmd_flags(pmd) & _PAGE_SWP_UFFD_WP; 1436 } 1437 1438 static inline pmd_t pmd_swp_clear_uffd_wp(pmd_t pmd) 1439 { 1440 return pmd_clear_flags(pmd, _PAGE_SWP_UFFD_WP); 1441 } 1442 #endif /* CONFIG_HAVE_ARCH_USERFAULTFD_WP */ 1443 1444 #define PKRU_AD_BIT 0x1 1445 #define PKRU_WD_BIT 0x2 1446 #define PKRU_BITS_PER_PKEY 2 1447 1448 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS 1449 extern u32 init_pkru_value; 1450 #else 1451 #define init_pkru_value 0 1452 #endif 1453 1454 static inline bool __pkru_allows_read(u32 pkru, u16 pkey) 1455 { 1456 int pkru_pkey_bits = pkey * PKRU_BITS_PER_PKEY; 1457 return !(pkru & (PKRU_AD_BIT << pkru_pkey_bits)); 1458 } 1459 1460 static inline bool __pkru_allows_write(u32 pkru, u16 pkey) 1461 { 1462 int pkru_pkey_bits = pkey * PKRU_BITS_PER_PKEY; 1463 /* 1464 * Access-disable disables writes too so we need to check 1465 * both bits here. 1466 */ 1467 return !(pkru & ((PKRU_AD_BIT|PKRU_WD_BIT) << pkru_pkey_bits)); 1468 } 1469 1470 static inline u16 pte_flags_pkey(unsigned long pte_flags) 1471 { 1472 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS 1473 /* ifdef to avoid doing 59-bit shift on 32-bit values */ 1474 return (pte_flags & _PAGE_PKEY_MASK) >> _PAGE_BIT_PKEY_BIT0; 1475 #else 1476 return 0; 1477 #endif 1478 } 1479 1480 static inline bool __pkru_allows_pkey(u16 pkey, bool write) 1481 { 1482 u32 pkru = read_pkru(); 1483 1484 if (!__pkru_allows_read(pkru, pkey)) 1485 return false; 1486 if (write && !__pkru_allows_write(pkru, pkey)) 1487 return false; 1488 1489 return true; 1490 } 1491 1492 /* 1493 * 'pteval' can come from a PTE, PMD or PUD. We only check 1494 * _PAGE_PRESENT, _PAGE_USER, and _PAGE_RW in here which are the 1495 * same value on all 3 types. 1496 */ 1497 static inline bool __pte_access_permitted(unsigned long pteval, bool write) 1498 { 1499 unsigned long need_pte_bits = _PAGE_PRESENT|_PAGE_USER; 1500 1501 if (write) 1502 need_pte_bits |= _PAGE_RW; 1503 1504 if ((pteval & need_pte_bits) != need_pte_bits) 1505 return 0; 1506 1507 return __pkru_allows_pkey(pte_flags_pkey(pteval), write); 1508 } 1509 1510 #define pte_access_permitted pte_access_permitted 1511 static inline bool pte_access_permitted(pte_t pte, bool write) 1512 { 1513 return __pte_access_permitted(pte_val(pte), write); 1514 } 1515 1516 #define pmd_access_permitted pmd_access_permitted 1517 static inline bool pmd_access_permitted(pmd_t pmd, bool write) 1518 { 1519 return __pte_access_permitted(pmd_val(pmd), write); 1520 } 1521 1522 #define pud_access_permitted pud_access_permitted 1523 static inline bool pud_access_permitted(pud_t pud, bool write) 1524 { 1525 return __pte_access_permitted(pud_val(pud), write); 1526 } 1527 1528 #define __HAVE_ARCH_PFN_MODIFY_ALLOWED 1 1529 extern bool pfn_modify_allowed(unsigned long pfn, pgprot_t prot); 1530 1531 static inline bool arch_has_pfn_modify_check(void) 1532 { 1533 return boot_cpu_has_bug(X86_BUG_L1TF); 1534 } 1535 1536 #define arch_faults_on_old_pte arch_faults_on_old_pte 1537 static inline bool arch_faults_on_old_pte(void) 1538 { 1539 return false; 1540 } 1541 1542 #include <asm-generic/pgtable.h> 1543 #endif /* __ASSEMBLY__ */ 1544 1545 #endif /* _ASM_X86_PGTABLE_H */ 1546