1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _ASM_X86_PGTABLE_H 3 #define _ASM_X86_PGTABLE_H 4 5 #include <linux/mem_encrypt.h> 6 #include <asm/page.h> 7 #include <asm/pgtable_types.h> 8 9 /* 10 * Macro to mark a page protection value as UC- 11 */ 12 #define pgprot_noncached(prot) \ 13 ((boot_cpu_data.x86 > 3) \ 14 ? (__pgprot(pgprot_val(prot) | \ 15 cachemode2protval(_PAGE_CACHE_MODE_UC_MINUS))) \ 16 : (prot)) 17 18 #ifndef __ASSEMBLER__ 19 #include <linux/spinlock.h> 20 #include <asm/x86_init.h> 21 #include <asm/pkru.h> 22 #include <asm/fpu/api.h> 23 #include <asm/coco.h> 24 #include <asm-generic/pgtable_uffd.h> 25 #include <linux/page_table_check.h> 26 27 extern pgd_t early_top_pgt[PTRS_PER_PGD]; 28 bool __init __early_make_pgtable(unsigned long address, pmdval_t pmd); 29 30 struct seq_file; 31 void ptdump_walk_pgd_level(struct seq_file *m, struct mm_struct *mm); 32 void ptdump_walk_pgd_level_debugfs(struct seq_file *m, struct mm_struct *mm, 33 bool user); 34 bool ptdump_walk_pgd_level_checkwx(void); 35 #define ptdump_check_wx ptdump_walk_pgd_level_checkwx 36 void ptdump_walk_user_pgd_level_checkwx(void); 37 38 /* 39 * Macros to add or remove encryption attribute 40 */ 41 #define pgprot_encrypted(prot) __pgprot(cc_mkenc(pgprot_val(prot))) 42 #define pgprot_decrypted(prot) __pgprot(cc_mkdec(pgprot_val(prot))) 43 44 #ifdef CONFIG_DEBUG_WX 45 #define debug_checkwx_user() ptdump_walk_user_pgd_level_checkwx() 46 #else 47 #define debug_checkwx_user() do { } while (0) 48 #endif 49 50 /* 51 * ZERO_PAGE is a global shared page that is always zero: used 52 * for zero-mapped memory areas etc.. 53 */ 54 extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)] 55 __visible; 56 #define ZERO_PAGE(vaddr) ((void)(vaddr),virt_to_page(empty_zero_page)) 57 58 extern spinlock_t pgd_lock; 59 extern struct list_head pgd_list; 60 61 extern struct mm_struct *pgd_page_get_mm(struct page *page); 62 63 extern pmdval_t early_pmd_flags; 64 65 #ifdef CONFIG_PARAVIRT_XXL 66 #include <asm/paravirt.h> 67 #else /* !CONFIG_PARAVIRT_XXL */ 68 #define set_pte(ptep, pte) native_set_pte(ptep, pte) 69 70 #define set_pte_atomic(ptep, pte) \ 71 native_set_pte_atomic(ptep, pte) 72 73 #define set_pmd(pmdp, pmd) native_set_pmd(pmdp, pmd) 74 75 #ifndef __PAGETABLE_P4D_FOLDED 76 #define set_pgd(pgdp, pgd) native_set_pgd(pgdp, pgd) 77 #define pgd_clear(pgd) (pgtable_l5_enabled() ? native_pgd_clear(pgd) : 0) 78 #endif 79 80 #ifndef set_p4d 81 # define set_p4d(p4dp, p4d) native_set_p4d(p4dp, p4d) 82 #endif 83 84 #ifndef __PAGETABLE_PUD_FOLDED 85 #define p4d_clear(p4d) native_p4d_clear(p4d) 86 #endif 87 88 #ifndef set_pud 89 # define set_pud(pudp, pud) native_set_pud(pudp, pud) 90 #endif 91 92 #ifndef __PAGETABLE_PUD_FOLDED 93 #define pud_clear(pud) native_pud_clear(pud) 94 #endif 95 96 #define pte_clear(mm, addr, ptep) native_pte_clear(mm, addr, ptep) 97 #define pmd_clear(pmd) native_pmd_clear(pmd) 98 99 #define pgd_val(x) native_pgd_val(x) 100 #define __pgd(x) native_make_pgd(x) 101 102 #ifndef __PAGETABLE_P4D_FOLDED 103 #define p4d_val(x) native_p4d_val(x) 104 #define __p4d(x) native_make_p4d(x) 105 #endif 106 107 #ifndef __PAGETABLE_PUD_FOLDED 108 #define pud_val(x) native_pud_val(x) 109 #define __pud(x) native_make_pud(x) 110 #endif 111 112 #ifndef __PAGETABLE_PMD_FOLDED 113 #define pmd_val(x) native_pmd_val(x) 114 #define __pmd(x) native_make_pmd(x) 115 #endif 116 117 #define pte_val(x) native_pte_val(x) 118 #define __pte(x) native_make_pte(x) 119 120 #define arch_end_context_switch(prev) do {} while(0) 121 #endif /* CONFIG_PARAVIRT_XXL */ 122 123 static inline pmd_t pmd_set_flags(pmd_t pmd, pmdval_t set) 124 { 125 pmdval_t v = native_pmd_val(pmd); 126 127 return native_make_pmd(v | set); 128 } 129 130 static inline pmd_t pmd_clear_flags(pmd_t pmd, pmdval_t clear) 131 { 132 pmdval_t v = native_pmd_val(pmd); 133 134 return native_make_pmd(v & ~clear); 135 } 136 137 static inline pud_t pud_set_flags(pud_t pud, pudval_t set) 138 { 139 pudval_t v = native_pud_val(pud); 140 141 return native_make_pud(v | set); 142 } 143 144 static inline pud_t pud_clear_flags(pud_t pud, pudval_t clear) 145 { 146 pudval_t v = native_pud_val(pud); 147 148 return native_make_pud(v & ~clear); 149 } 150 151 /* 152 * The following only work if pte_present() is true. 153 * Undefined behaviour if not.. 154 */ 155 static inline bool pte_dirty(pte_t pte) 156 { 157 return pte_flags(pte) & _PAGE_DIRTY_BITS; 158 } 159 160 static inline bool pte_shstk(pte_t pte) 161 { 162 return cpu_feature_enabled(X86_FEATURE_SHSTK) && 163 (pte_flags(pte) & (_PAGE_RW | _PAGE_DIRTY)) == _PAGE_DIRTY; 164 } 165 166 static inline int pte_young(pte_t pte) 167 { 168 return pte_flags(pte) & _PAGE_ACCESSED; 169 } 170 171 static inline bool pte_decrypted(pte_t pte) 172 { 173 return cc_mkdec(pte_val(pte)) == pte_val(pte); 174 } 175 176 #define pmd_dirty pmd_dirty 177 static inline bool pmd_dirty(pmd_t pmd) 178 { 179 return pmd_flags(pmd) & _PAGE_DIRTY_BITS; 180 } 181 182 static inline bool pmd_shstk(pmd_t pmd) 183 { 184 return cpu_feature_enabled(X86_FEATURE_SHSTK) && 185 (pmd_flags(pmd) & (_PAGE_RW | _PAGE_DIRTY | _PAGE_PSE)) == 186 (_PAGE_DIRTY | _PAGE_PSE); 187 } 188 189 #define pmd_young pmd_young 190 static inline int pmd_young(pmd_t pmd) 191 { 192 return pmd_flags(pmd) & _PAGE_ACCESSED; 193 } 194 195 static inline bool pud_dirty(pud_t pud) 196 { 197 return pud_flags(pud) & _PAGE_DIRTY_BITS; 198 } 199 200 static inline int pud_young(pud_t pud) 201 { 202 return pud_flags(pud) & _PAGE_ACCESSED; 203 } 204 205 static inline bool pud_shstk(pud_t pud) 206 { 207 return cpu_feature_enabled(X86_FEATURE_SHSTK) && 208 (pud_flags(pud) & (_PAGE_RW | _PAGE_DIRTY | _PAGE_PSE)) == 209 (_PAGE_DIRTY | _PAGE_PSE); 210 } 211 212 static inline int pte_write(pte_t pte) 213 { 214 /* 215 * Shadow stack pages are logically writable, but do not have 216 * _PAGE_RW. Check for them separately from _PAGE_RW itself. 217 */ 218 return (pte_flags(pte) & _PAGE_RW) || pte_shstk(pte); 219 } 220 221 #define pmd_write pmd_write 222 static inline int pmd_write(pmd_t pmd) 223 { 224 /* 225 * Shadow stack pages are logically writable, but do not have 226 * _PAGE_RW. Check for them separately from _PAGE_RW itself. 227 */ 228 return (pmd_flags(pmd) & _PAGE_RW) || pmd_shstk(pmd); 229 } 230 231 #define pud_write pud_write 232 static inline int pud_write(pud_t pud) 233 { 234 return pud_flags(pud) & _PAGE_RW; 235 } 236 237 static inline int pte_huge(pte_t pte) 238 { 239 return pte_flags(pte) & _PAGE_PSE; 240 } 241 242 static inline int pte_global(pte_t pte) 243 { 244 return pte_flags(pte) & _PAGE_GLOBAL; 245 } 246 247 static inline int pte_exec(pte_t pte) 248 { 249 return !(pte_flags(pte) & _PAGE_NX); 250 } 251 252 static inline int pte_special(pte_t pte) 253 { 254 return pte_flags(pte) & _PAGE_SPECIAL; 255 } 256 257 /* Entries that were set to PROT_NONE are inverted */ 258 259 static inline u64 protnone_mask(u64 val); 260 261 #define PFN_PTE_SHIFT PAGE_SHIFT 262 263 static inline unsigned long pte_pfn(pte_t pte) 264 { 265 phys_addr_t pfn = pte_val(pte); 266 pfn ^= protnone_mask(pfn); 267 return (pfn & PTE_PFN_MASK) >> PAGE_SHIFT; 268 } 269 270 static inline unsigned long pmd_pfn(pmd_t pmd) 271 { 272 phys_addr_t pfn = pmd_val(pmd); 273 pfn ^= protnone_mask(pfn); 274 return (pfn & pmd_pfn_mask(pmd)) >> PAGE_SHIFT; 275 } 276 277 #define pud_pfn pud_pfn 278 static inline unsigned long pud_pfn(pud_t pud) 279 { 280 phys_addr_t pfn = pud_val(pud); 281 pfn ^= protnone_mask(pfn); 282 return (pfn & pud_pfn_mask(pud)) >> PAGE_SHIFT; 283 } 284 285 static inline unsigned long p4d_pfn(p4d_t p4d) 286 { 287 return (p4d_val(p4d) & p4d_pfn_mask(p4d)) >> PAGE_SHIFT; 288 } 289 290 static inline unsigned long pgd_pfn(pgd_t pgd) 291 { 292 return (pgd_val(pgd) & PTE_PFN_MASK) >> PAGE_SHIFT; 293 } 294 295 #define p4d_leaf p4d_leaf 296 static inline bool p4d_leaf(p4d_t p4d) 297 { 298 /* No 512 GiB pages yet */ 299 return 0; 300 } 301 302 #define pte_page(pte) pfn_to_page(pte_pfn(pte)) 303 304 #define pmd_leaf pmd_leaf 305 static inline bool pmd_leaf(pmd_t pte) 306 { 307 return pmd_flags(pte) & _PAGE_PSE; 308 } 309 310 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 311 /* NOTE: when predicate huge page, consider also pmd_devmap, or use pmd_leaf */ 312 static inline int pmd_trans_huge(pmd_t pmd) 313 { 314 return (pmd_val(pmd) & (_PAGE_PSE|_PAGE_DEVMAP)) == _PAGE_PSE; 315 } 316 317 #ifdef CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD 318 static inline int pud_trans_huge(pud_t pud) 319 { 320 return (pud_val(pud) & (_PAGE_PSE|_PAGE_DEVMAP)) == _PAGE_PSE; 321 } 322 #endif 323 324 #define has_transparent_hugepage has_transparent_hugepage 325 static inline int has_transparent_hugepage(void) 326 { 327 return boot_cpu_has(X86_FEATURE_PSE); 328 } 329 330 #ifdef CONFIG_ARCH_HAS_PTE_DEVMAP 331 static inline int pmd_devmap(pmd_t pmd) 332 { 333 return !!(pmd_val(pmd) & _PAGE_DEVMAP); 334 } 335 336 #ifdef CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD 337 static inline int pud_devmap(pud_t pud) 338 { 339 return !!(pud_val(pud) & _PAGE_DEVMAP); 340 } 341 #else 342 static inline int pud_devmap(pud_t pud) 343 { 344 return 0; 345 } 346 #endif 347 348 #ifdef CONFIG_ARCH_SUPPORTS_PMD_PFNMAP 349 static inline bool pmd_special(pmd_t pmd) 350 { 351 return pmd_flags(pmd) & _PAGE_SPECIAL; 352 } 353 354 static inline pmd_t pmd_mkspecial(pmd_t pmd) 355 { 356 return pmd_set_flags(pmd, _PAGE_SPECIAL); 357 } 358 #endif /* CONFIG_ARCH_SUPPORTS_PMD_PFNMAP */ 359 360 #ifdef CONFIG_ARCH_SUPPORTS_PUD_PFNMAP 361 static inline bool pud_special(pud_t pud) 362 { 363 return pud_flags(pud) & _PAGE_SPECIAL; 364 } 365 366 static inline pud_t pud_mkspecial(pud_t pud) 367 { 368 return pud_set_flags(pud, _PAGE_SPECIAL); 369 } 370 #endif /* CONFIG_ARCH_SUPPORTS_PUD_PFNMAP */ 371 372 static inline int pgd_devmap(pgd_t pgd) 373 { 374 return 0; 375 } 376 #endif 377 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 378 379 static inline pte_t pte_set_flags(pte_t pte, pteval_t set) 380 { 381 pteval_t v = native_pte_val(pte); 382 383 return native_make_pte(v | set); 384 } 385 386 static inline pte_t pte_clear_flags(pte_t pte, pteval_t clear) 387 { 388 pteval_t v = native_pte_val(pte); 389 390 return native_make_pte(v & ~clear); 391 } 392 393 /* 394 * Write protection operations can result in Dirty=1,Write=0 PTEs. But in the 395 * case of X86_FEATURE_USER_SHSTK, these PTEs denote shadow stack memory. So 396 * when creating dirty, write-protected memory, a software bit is used: 397 * _PAGE_BIT_SAVED_DIRTY. The following functions take a PTE and transition the 398 * Dirty bit to SavedDirty, and vice-vesra. 399 * 400 * This shifting is only done if needed. In the case of shifting 401 * Dirty->SavedDirty, the condition is if the PTE is Write=0. In the case of 402 * shifting SavedDirty->Dirty, the condition is Write=1. 403 */ 404 static inline pgprotval_t mksaveddirty_shift(pgprotval_t v) 405 { 406 pgprotval_t cond = (~v >> _PAGE_BIT_RW) & 1; 407 408 v |= ((v >> _PAGE_BIT_DIRTY) & cond) << _PAGE_BIT_SAVED_DIRTY; 409 v &= ~(cond << _PAGE_BIT_DIRTY); 410 411 return v; 412 } 413 414 static inline pgprotval_t clear_saveddirty_shift(pgprotval_t v) 415 { 416 pgprotval_t cond = (v >> _PAGE_BIT_RW) & 1; 417 418 v |= ((v >> _PAGE_BIT_SAVED_DIRTY) & cond) << _PAGE_BIT_DIRTY; 419 v &= ~(cond << _PAGE_BIT_SAVED_DIRTY); 420 421 return v; 422 } 423 424 static inline pte_t pte_mksaveddirty(pte_t pte) 425 { 426 pteval_t v = native_pte_val(pte); 427 428 v = mksaveddirty_shift(v); 429 return native_make_pte(v); 430 } 431 432 static inline pte_t pte_clear_saveddirty(pte_t pte) 433 { 434 pteval_t v = native_pte_val(pte); 435 436 v = clear_saveddirty_shift(v); 437 return native_make_pte(v); 438 } 439 440 static inline pte_t pte_wrprotect(pte_t pte) 441 { 442 pte = pte_clear_flags(pte, _PAGE_RW); 443 444 /* 445 * Blindly clearing _PAGE_RW might accidentally create 446 * a shadow stack PTE (Write=0,Dirty=1). Move the hardware 447 * dirty value to the software bit, if present. 448 */ 449 return pte_mksaveddirty(pte); 450 } 451 452 #ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP 453 static inline int pte_uffd_wp(pte_t pte) 454 { 455 return pte_flags(pte) & _PAGE_UFFD_WP; 456 } 457 458 static inline pte_t pte_mkuffd_wp(pte_t pte) 459 { 460 return pte_wrprotect(pte_set_flags(pte, _PAGE_UFFD_WP)); 461 } 462 463 static inline pte_t pte_clear_uffd_wp(pte_t pte) 464 { 465 return pte_clear_flags(pte, _PAGE_UFFD_WP); 466 } 467 #endif /* CONFIG_HAVE_ARCH_USERFAULTFD_WP */ 468 469 static inline pte_t pte_mkclean(pte_t pte) 470 { 471 return pte_clear_flags(pte, _PAGE_DIRTY_BITS); 472 } 473 474 static inline pte_t pte_mkold(pte_t pte) 475 { 476 return pte_clear_flags(pte, _PAGE_ACCESSED); 477 } 478 479 static inline pte_t pte_mkexec(pte_t pte) 480 { 481 return pte_clear_flags(pte, _PAGE_NX); 482 } 483 484 static inline pte_t pte_mkdirty(pte_t pte) 485 { 486 pte = pte_set_flags(pte, _PAGE_DIRTY | _PAGE_SOFT_DIRTY); 487 488 return pte_mksaveddirty(pte); 489 } 490 491 static inline pte_t pte_mkwrite_shstk(pte_t pte) 492 { 493 pte = pte_clear_flags(pte, _PAGE_RW); 494 495 return pte_set_flags(pte, _PAGE_DIRTY); 496 } 497 498 static inline pte_t pte_mkyoung(pte_t pte) 499 { 500 return pte_set_flags(pte, _PAGE_ACCESSED); 501 } 502 503 static inline pte_t pte_mkwrite_novma(pte_t pte) 504 { 505 return pte_set_flags(pte, _PAGE_RW); 506 } 507 508 struct vm_area_struct; 509 pte_t pte_mkwrite(pte_t pte, struct vm_area_struct *vma); 510 #define pte_mkwrite pte_mkwrite 511 512 static inline pte_t pte_mkhuge(pte_t pte) 513 { 514 return pte_set_flags(pte, _PAGE_PSE); 515 } 516 517 static inline pte_t pte_clrhuge(pte_t pte) 518 { 519 return pte_clear_flags(pte, _PAGE_PSE); 520 } 521 522 static inline pte_t pte_mkglobal(pte_t pte) 523 { 524 return pte_set_flags(pte, _PAGE_GLOBAL); 525 } 526 527 static inline pte_t pte_clrglobal(pte_t pte) 528 { 529 return pte_clear_flags(pte, _PAGE_GLOBAL); 530 } 531 532 static inline pte_t pte_mkspecial(pte_t pte) 533 { 534 return pte_set_flags(pte, _PAGE_SPECIAL); 535 } 536 537 static inline pte_t pte_mkdevmap(pte_t pte) 538 { 539 return pte_set_flags(pte, _PAGE_SPECIAL|_PAGE_DEVMAP); 540 } 541 542 /* See comments above mksaveddirty_shift() */ 543 static inline pmd_t pmd_mksaveddirty(pmd_t pmd) 544 { 545 pmdval_t v = native_pmd_val(pmd); 546 547 v = mksaveddirty_shift(v); 548 return native_make_pmd(v); 549 } 550 551 /* See comments above mksaveddirty_shift() */ 552 static inline pmd_t pmd_clear_saveddirty(pmd_t pmd) 553 { 554 pmdval_t v = native_pmd_val(pmd); 555 556 v = clear_saveddirty_shift(v); 557 return native_make_pmd(v); 558 } 559 560 static inline pmd_t pmd_wrprotect(pmd_t pmd) 561 { 562 pmd = pmd_clear_flags(pmd, _PAGE_RW); 563 564 /* 565 * Blindly clearing _PAGE_RW might accidentally create 566 * a shadow stack PMD (RW=0, Dirty=1). Move the hardware 567 * dirty value to the software bit. 568 */ 569 return pmd_mksaveddirty(pmd); 570 } 571 572 #ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP 573 static inline int pmd_uffd_wp(pmd_t pmd) 574 { 575 return pmd_flags(pmd) & _PAGE_UFFD_WP; 576 } 577 578 static inline pmd_t pmd_mkuffd_wp(pmd_t pmd) 579 { 580 return pmd_wrprotect(pmd_set_flags(pmd, _PAGE_UFFD_WP)); 581 } 582 583 static inline pmd_t pmd_clear_uffd_wp(pmd_t pmd) 584 { 585 return pmd_clear_flags(pmd, _PAGE_UFFD_WP); 586 } 587 #endif /* CONFIG_HAVE_ARCH_USERFAULTFD_WP */ 588 589 static inline pmd_t pmd_mkold(pmd_t pmd) 590 { 591 return pmd_clear_flags(pmd, _PAGE_ACCESSED); 592 } 593 594 static inline pmd_t pmd_mkclean(pmd_t pmd) 595 { 596 return pmd_clear_flags(pmd, _PAGE_DIRTY_BITS); 597 } 598 599 static inline pmd_t pmd_mkdirty(pmd_t pmd) 600 { 601 pmd = pmd_set_flags(pmd, _PAGE_DIRTY | _PAGE_SOFT_DIRTY); 602 603 return pmd_mksaveddirty(pmd); 604 } 605 606 static inline pmd_t pmd_mkwrite_shstk(pmd_t pmd) 607 { 608 pmd = pmd_clear_flags(pmd, _PAGE_RW); 609 610 return pmd_set_flags(pmd, _PAGE_DIRTY); 611 } 612 613 static inline pmd_t pmd_mkdevmap(pmd_t pmd) 614 { 615 return pmd_set_flags(pmd, _PAGE_DEVMAP); 616 } 617 618 static inline pmd_t pmd_mkhuge(pmd_t pmd) 619 { 620 return pmd_set_flags(pmd, _PAGE_PSE); 621 } 622 623 static inline pmd_t pmd_mkyoung(pmd_t pmd) 624 { 625 return pmd_set_flags(pmd, _PAGE_ACCESSED); 626 } 627 628 static inline pmd_t pmd_mkwrite_novma(pmd_t pmd) 629 { 630 return pmd_set_flags(pmd, _PAGE_RW); 631 } 632 633 pmd_t pmd_mkwrite(pmd_t pmd, struct vm_area_struct *vma); 634 #define pmd_mkwrite pmd_mkwrite 635 636 /* See comments above mksaveddirty_shift() */ 637 static inline pud_t pud_mksaveddirty(pud_t pud) 638 { 639 pudval_t v = native_pud_val(pud); 640 641 v = mksaveddirty_shift(v); 642 return native_make_pud(v); 643 } 644 645 /* See comments above mksaveddirty_shift() */ 646 static inline pud_t pud_clear_saveddirty(pud_t pud) 647 { 648 pudval_t v = native_pud_val(pud); 649 650 v = clear_saveddirty_shift(v); 651 return native_make_pud(v); 652 } 653 654 static inline pud_t pud_mkold(pud_t pud) 655 { 656 return pud_clear_flags(pud, _PAGE_ACCESSED); 657 } 658 659 static inline pud_t pud_mkclean(pud_t pud) 660 { 661 return pud_clear_flags(pud, _PAGE_DIRTY_BITS); 662 } 663 664 static inline pud_t pud_wrprotect(pud_t pud) 665 { 666 pud = pud_clear_flags(pud, _PAGE_RW); 667 668 /* 669 * Blindly clearing _PAGE_RW might accidentally create 670 * a shadow stack PUD (RW=0, Dirty=1). Move the hardware 671 * dirty value to the software bit. 672 */ 673 return pud_mksaveddirty(pud); 674 } 675 676 static inline pud_t pud_mkdirty(pud_t pud) 677 { 678 pud = pud_set_flags(pud, _PAGE_DIRTY | _PAGE_SOFT_DIRTY); 679 680 return pud_mksaveddirty(pud); 681 } 682 683 static inline pud_t pud_mkdevmap(pud_t pud) 684 { 685 return pud_set_flags(pud, _PAGE_DEVMAP); 686 } 687 688 static inline pud_t pud_mkhuge(pud_t pud) 689 { 690 return pud_set_flags(pud, _PAGE_PSE); 691 } 692 693 static inline pud_t pud_mkyoung(pud_t pud) 694 { 695 return pud_set_flags(pud, _PAGE_ACCESSED); 696 } 697 698 static inline pud_t pud_mkwrite(pud_t pud) 699 { 700 pud = pud_set_flags(pud, _PAGE_RW); 701 702 return pud_clear_saveddirty(pud); 703 } 704 705 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 706 static inline int pte_soft_dirty(pte_t pte) 707 { 708 return pte_flags(pte) & _PAGE_SOFT_DIRTY; 709 } 710 711 static inline int pmd_soft_dirty(pmd_t pmd) 712 { 713 return pmd_flags(pmd) & _PAGE_SOFT_DIRTY; 714 } 715 716 static inline int pud_soft_dirty(pud_t pud) 717 { 718 return pud_flags(pud) & _PAGE_SOFT_DIRTY; 719 } 720 721 static inline pte_t pte_mksoft_dirty(pte_t pte) 722 { 723 return pte_set_flags(pte, _PAGE_SOFT_DIRTY); 724 } 725 726 static inline pmd_t pmd_mksoft_dirty(pmd_t pmd) 727 { 728 return pmd_set_flags(pmd, _PAGE_SOFT_DIRTY); 729 } 730 731 static inline pud_t pud_mksoft_dirty(pud_t pud) 732 { 733 return pud_set_flags(pud, _PAGE_SOFT_DIRTY); 734 } 735 736 static inline pte_t pte_clear_soft_dirty(pte_t pte) 737 { 738 return pte_clear_flags(pte, _PAGE_SOFT_DIRTY); 739 } 740 741 static inline pmd_t pmd_clear_soft_dirty(pmd_t pmd) 742 { 743 return pmd_clear_flags(pmd, _PAGE_SOFT_DIRTY); 744 } 745 746 static inline pud_t pud_clear_soft_dirty(pud_t pud) 747 { 748 return pud_clear_flags(pud, _PAGE_SOFT_DIRTY); 749 } 750 751 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ 752 753 /* 754 * Mask out unsupported bits in a present pgprot. Non-present pgprots 755 * can use those bits for other purposes, so leave them be. 756 */ 757 static inline pgprotval_t massage_pgprot(pgprot_t pgprot) 758 { 759 pgprotval_t protval = pgprot_val(pgprot); 760 761 if (protval & _PAGE_PRESENT) 762 protval &= __supported_pte_mask; 763 764 return protval; 765 } 766 767 static inline pgprotval_t check_pgprot(pgprot_t pgprot) 768 { 769 pgprotval_t massaged_val = massage_pgprot(pgprot); 770 771 /* mmdebug.h can not be included here because of dependencies */ 772 #ifdef CONFIG_DEBUG_VM 773 WARN_ONCE(pgprot_val(pgprot) != massaged_val, 774 "attempted to set unsupported pgprot: %016llx " 775 "bits: %016llx supported: %016llx\n", 776 (u64)pgprot_val(pgprot), 777 (u64)pgprot_val(pgprot) ^ massaged_val, 778 (u64)__supported_pte_mask); 779 #endif 780 781 return massaged_val; 782 } 783 784 static inline pte_t pfn_pte(unsigned long page_nr, pgprot_t pgprot) 785 { 786 phys_addr_t pfn = (phys_addr_t)page_nr << PAGE_SHIFT; 787 /* This bit combination is used to mark shadow stacks */ 788 WARN_ON_ONCE((pgprot_val(pgprot) & (_PAGE_DIRTY | _PAGE_RW)) == 789 _PAGE_DIRTY); 790 pfn ^= protnone_mask(pgprot_val(pgprot)); 791 pfn &= PTE_PFN_MASK; 792 return __pte(pfn | check_pgprot(pgprot)); 793 } 794 795 static inline pmd_t pfn_pmd(unsigned long page_nr, pgprot_t pgprot) 796 { 797 phys_addr_t pfn = (phys_addr_t)page_nr << PAGE_SHIFT; 798 pfn ^= protnone_mask(pgprot_val(pgprot)); 799 pfn &= PHYSICAL_PMD_PAGE_MASK; 800 return __pmd(pfn | check_pgprot(pgprot)); 801 } 802 803 static inline pud_t pfn_pud(unsigned long page_nr, pgprot_t pgprot) 804 { 805 phys_addr_t pfn = (phys_addr_t)page_nr << PAGE_SHIFT; 806 pfn ^= protnone_mask(pgprot_val(pgprot)); 807 pfn &= PHYSICAL_PUD_PAGE_MASK; 808 return __pud(pfn | check_pgprot(pgprot)); 809 } 810 811 static inline pmd_t pmd_mkinvalid(pmd_t pmd) 812 { 813 return pfn_pmd(pmd_pfn(pmd), 814 __pgprot(pmd_flags(pmd) & ~(_PAGE_PRESENT|_PAGE_PROTNONE))); 815 } 816 817 static inline pud_t pud_mkinvalid(pud_t pud) 818 { 819 return pfn_pud(pud_pfn(pud), 820 __pgprot(pud_flags(pud) & ~(_PAGE_PRESENT|_PAGE_PROTNONE))); 821 } 822 823 static inline u64 flip_protnone_guard(u64 oldval, u64 val, u64 mask); 824 825 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 826 { 827 pteval_t val = pte_val(pte), oldval = val; 828 pte_t pte_result; 829 830 /* 831 * Chop off the NX bit (if present), and add the NX portion of 832 * the newprot (if present): 833 */ 834 val &= _PAGE_CHG_MASK; 835 val |= check_pgprot(newprot) & ~_PAGE_CHG_MASK; 836 val = flip_protnone_guard(oldval, val, PTE_PFN_MASK); 837 838 pte_result = __pte(val); 839 840 /* 841 * To avoid creating Write=0,Dirty=1 PTEs, pte_modify() needs to avoid: 842 * 1. Marking Write=0 PTEs Dirty=1 843 * 2. Marking Dirty=1 PTEs Write=0 844 * 845 * The first case cannot happen because the _PAGE_CHG_MASK will filter 846 * out any Dirty bit passed in newprot. Handle the second case by 847 * going through the mksaveddirty exercise. Only do this if the old 848 * value was Write=1 to avoid doing this on Shadow Stack PTEs. 849 */ 850 if (oldval & _PAGE_RW) 851 pte_result = pte_mksaveddirty(pte_result); 852 else 853 pte_result = pte_clear_saveddirty(pte_result); 854 855 return pte_result; 856 } 857 858 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) 859 { 860 pmdval_t val = pmd_val(pmd), oldval = val; 861 pmd_t pmd_result; 862 863 val &= (_HPAGE_CHG_MASK & ~_PAGE_DIRTY); 864 val |= check_pgprot(newprot) & ~_HPAGE_CHG_MASK; 865 val = flip_protnone_guard(oldval, val, PHYSICAL_PMD_PAGE_MASK); 866 867 pmd_result = __pmd(val); 868 869 /* 870 * Avoid creating shadow stack PMD by accident. See comment in 871 * pte_modify(). 872 */ 873 if (oldval & _PAGE_RW) 874 pmd_result = pmd_mksaveddirty(pmd_result); 875 else 876 pmd_result = pmd_clear_saveddirty(pmd_result); 877 878 return pmd_result; 879 } 880 881 static inline pud_t pud_modify(pud_t pud, pgprot_t newprot) 882 { 883 pudval_t val = pud_val(pud), oldval = val; 884 pud_t pud_result; 885 886 val &= _HPAGE_CHG_MASK; 887 val |= check_pgprot(newprot) & ~_HPAGE_CHG_MASK; 888 val = flip_protnone_guard(oldval, val, PHYSICAL_PUD_PAGE_MASK); 889 890 pud_result = __pud(val); 891 892 /* 893 * Avoid creating shadow stack PUD by accident. See comment in 894 * pte_modify(). 895 */ 896 if (oldval & _PAGE_RW) 897 pud_result = pud_mksaveddirty(pud_result); 898 else 899 pud_result = pud_clear_saveddirty(pud_result); 900 901 return pud_result; 902 } 903 904 /* 905 * mprotect needs to preserve PAT and encryption bits when updating 906 * vm_page_prot 907 */ 908 #define pgprot_modify pgprot_modify 909 static inline pgprot_t pgprot_modify(pgprot_t oldprot, pgprot_t newprot) 910 { 911 pgprotval_t preservebits = pgprot_val(oldprot) & _PAGE_CHG_MASK; 912 pgprotval_t addbits = pgprot_val(newprot) & ~_PAGE_CHG_MASK; 913 return __pgprot(preservebits | addbits); 914 } 915 916 #define pte_pgprot(x) __pgprot(pte_flags(x)) 917 #define pmd_pgprot(x) __pgprot(pmd_flags(x)) 918 #define pud_pgprot(x) __pgprot(pud_flags(x)) 919 #define p4d_pgprot(x) __pgprot(p4d_flags(x)) 920 921 #define canon_pgprot(p) __pgprot(massage_pgprot(p)) 922 923 static inline int is_new_memtype_allowed(u64 paddr, unsigned long size, 924 enum page_cache_mode pcm, 925 enum page_cache_mode new_pcm) 926 { 927 /* 928 * PAT type is always WB for untracked ranges, so no need to check. 929 */ 930 if (x86_platform.is_untracked_pat_range(paddr, paddr + size)) 931 return 1; 932 933 /* 934 * Certain new memtypes are not allowed with certain 935 * requested memtype: 936 * - request is uncached, return cannot be write-back 937 * - request is write-combine, return cannot be write-back 938 * - request is write-through, return cannot be write-back 939 * - request is write-through, return cannot be write-combine 940 */ 941 if ((pcm == _PAGE_CACHE_MODE_UC_MINUS && 942 new_pcm == _PAGE_CACHE_MODE_WB) || 943 (pcm == _PAGE_CACHE_MODE_WC && 944 new_pcm == _PAGE_CACHE_MODE_WB) || 945 (pcm == _PAGE_CACHE_MODE_WT && 946 new_pcm == _PAGE_CACHE_MODE_WB) || 947 (pcm == _PAGE_CACHE_MODE_WT && 948 new_pcm == _PAGE_CACHE_MODE_WC)) { 949 return 0; 950 } 951 952 return 1; 953 } 954 955 pmd_t *populate_extra_pmd(unsigned long vaddr); 956 pte_t *populate_extra_pte(unsigned long vaddr); 957 958 #ifdef CONFIG_MITIGATION_PAGE_TABLE_ISOLATION 959 pgd_t __pti_set_user_pgtbl(pgd_t *pgdp, pgd_t pgd); 960 961 /* 962 * Take a PGD location (pgdp) and a pgd value that needs to be set there. 963 * Populates the user and returns the resulting PGD that must be set in 964 * the kernel copy of the page tables. 965 */ 966 static inline pgd_t pti_set_user_pgtbl(pgd_t *pgdp, pgd_t pgd) 967 { 968 if (!static_cpu_has(X86_FEATURE_PTI)) 969 return pgd; 970 return __pti_set_user_pgtbl(pgdp, pgd); 971 } 972 #else /* CONFIG_MITIGATION_PAGE_TABLE_ISOLATION */ 973 static inline pgd_t pti_set_user_pgtbl(pgd_t *pgdp, pgd_t pgd) 974 { 975 return pgd; 976 } 977 #endif /* CONFIG_MITIGATION_PAGE_TABLE_ISOLATION */ 978 979 #endif /* __ASSEMBLER__ */ 980 981 982 #ifdef CONFIG_X86_32 983 # include <asm/pgtable_32.h> 984 #else 985 # include <asm/pgtable_64.h> 986 #endif 987 988 #ifndef __ASSEMBLER__ 989 #include <linux/mm_types.h> 990 #include <linux/mmdebug.h> 991 #include <linux/log2.h> 992 #include <asm/fixmap.h> 993 994 static inline int pte_none(pte_t pte) 995 { 996 return !(pte.pte & ~(_PAGE_KNL_ERRATUM_MASK)); 997 } 998 999 #define __HAVE_ARCH_PTE_SAME 1000 static inline int pte_same(pte_t a, pte_t b) 1001 { 1002 return a.pte == b.pte; 1003 } 1004 1005 static inline pte_t pte_advance_pfn(pte_t pte, unsigned long nr) 1006 { 1007 if (__pte_needs_invert(pte_val(pte))) 1008 return __pte(pte_val(pte) - (nr << PFN_PTE_SHIFT)); 1009 return __pte(pte_val(pte) + (nr << PFN_PTE_SHIFT)); 1010 } 1011 #define pte_advance_pfn pte_advance_pfn 1012 1013 static inline int pte_present(pte_t a) 1014 { 1015 return pte_flags(a) & (_PAGE_PRESENT | _PAGE_PROTNONE); 1016 } 1017 1018 #ifdef CONFIG_ARCH_HAS_PTE_DEVMAP 1019 static inline int pte_devmap(pte_t a) 1020 { 1021 return (pte_flags(a) & _PAGE_DEVMAP) == _PAGE_DEVMAP; 1022 } 1023 #endif 1024 1025 #define pte_accessible pte_accessible 1026 static inline bool pte_accessible(struct mm_struct *mm, pte_t a) 1027 { 1028 if (pte_flags(a) & _PAGE_PRESENT) 1029 return true; 1030 1031 if ((pte_flags(a) & _PAGE_PROTNONE) && 1032 atomic_read(&mm->tlb_flush_pending)) 1033 return true; 1034 1035 return false; 1036 } 1037 1038 static inline int pmd_present(pmd_t pmd) 1039 { 1040 /* 1041 * Checking for _PAGE_PSE is needed too because 1042 * split_huge_page will temporarily clear the present bit (but 1043 * the _PAGE_PSE flag will remain set at all times while the 1044 * _PAGE_PRESENT bit is clear). 1045 */ 1046 return pmd_flags(pmd) & (_PAGE_PRESENT | _PAGE_PROTNONE | _PAGE_PSE); 1047 } 1048 1049 #ifdef CONFIG_NUMA_BALANCING 1050 /* 1051 * These work without NUMA balancing but the kernel does not care. See the 1052 * comment in include/linux/pgtable.h 1053 */ 1054 static inline int pte_protnone(pte_t pte) 1055 { 1056 return (pte_flags(pte) & (_PAGE_PROTNONE | _PAGE_PRESENT)) 1057 == _PAGE_PROTNONE; 1058 } 1059 1060 static inline int pmd_protnone(pmd_t pmd) 1061 { 1062 return (pmd_flags(pmd) & (_PAGE_PROTNONE | _PAGE_PRESENT)) 1063 == _PAGE_PROTNONE; 1064 } 1065 #endif /* CONFIG_NUMA_BALANCING */ 1066 1067 static inline int pmd_none(pmd_t pmd) 1068 { 1069 /* Only check low word on 32-bit platforms, since it might be 1070 out of sync with upper half. */ 1071 unsigned long val = native_pmd_val(pmd); 1072 return (val & ~_PAGE_KNL_ERRATUM_MASK) == 0; 1073 } 1074 1075 static inline unsigned long pmd_page_vaddr(pmd_t pmd) 1076 { 1077 return (unsigned long)__va(pmd_val(pmd) & pmd_pfn_mask(pmd)); 1078 } 1079 1080 /* 1081 * Currently stuck as a macro due to indirect forward reference to 1082 * linux/mmzone.h's __section_mem_map_addr() definition: 1083 */ 1084 #define pmd_page(pmd) pfn_to_page(pmd_pfn(pmd)) 1085 1086 static inline int pmd_bad(pmd_t pmd) 1087 { 1088 return (pmd_flags(pmd) & ~(_PAGE_USER | _PAGE_ACCESSED)) != 1089 (_KERNPG_TABLE & ~_PAGE_ACCESSED); 1090 } 1091 1092 static inline unsigned long pages_to_mb(unsigned long npg) 1093 { 1094 return npg >> (20 - PAGE_SHIFT); 1095 } 1096 1097 #if CONFIG_PGTABLE_LEVELS > 2 1098 static inline int pud_none(pud_t pud) 1099 { 1100 return (native_pud_val(pud) & ~(_PAGE_KNL_ERRATUM_MASK)) == 0; 1101 } 1102 1103 static inline int pud_present(pud_t pud) 1104 { 1105 return pud_flags(pud) & _PAGE_PRESENT; 1106 } 1107 1108 static inline pmd_t *pud_pgtable(pud_t pud) 1109 { 1110 return (pmd_t *)__va(pud_val(pud) & pud_pfn_mask(pud)); 1111 } 1112 1113 /* 1114 * Currently stuck as a macro due to indirect forward reference to 1115 * linux/mmzone.h's __section_mem_map_addr() definition: 1116 */ 1117 #define pud_page(pud) pfn_to_page(pud_pfn(pud)) 1118 1119 #define pud_leaf pud_leaf 1120 static inline bool pud_leaf(pud_t pud) 1121 { 1122 return pud_val(pud) & _PAGE_PSE; 1123 } 1124 1125 static inline int pud_bad(pud_t pud) 1126 { 1127 return (pud_flags(pud) & ~(_KERNPG_TABLE | _PAGE_USER)) != 0; 1128 } 1129 #endif /* CONFIG_PGTABLE_LEVELS > 2 */ 1130 1131 #if CONFIG_PGTABLE_LEVELS > 3 1132 static inline int p4d_none(p4d_t p4d) 1133 { 1134 return (native_p4d_val(p4d) & ~(_PAGE_KNL_ERRATUM_MASK)) == 0; 1135 } 1136 1137 static inline int p4d_present(p4d_t p4d) 1138 { 1139 return p4d_flags(p4d) & _PAGE_PRESENT; 1140 } 1141 1142 static inline pud_t *p4d_pgtable(p4d_t p4d) 1143 { 1144 return (pud_t *)__va(p4d_val(p4d) & p4d_pfn_mask(p4d)); 1145 } 1146 1147 /* 1148 * Currently stuck as a macro due to indirect forward reference to 1149 * linux/mmzone.h's __section_mem_map_addr() definition: 1150 */ 1151 #define p4d_page(p4d) pfn_to_page(p4d_pfn(p4d)) 1152 1153 static inline int p4d_bad(p4d_t p4d) 1154 { 1155 unsigned long ignore_flags = _KERNPG_TABLE | _PAGE_USER; 1156 1157 if (IS_ENABLED(CONFIG_MITIGATION_PAGE_TABLE_ISOLATION)) 1158 ignore_flags |= _PAGE_NX; 1159 1160 return (p4d_flags(p4d) & ~ignore_flags) != 0; 1161 } 1162 #endif /* CONFIG_PGTABLE_LEVELS > 3 */ 1163 1164 static inline unsigned long p4d_index(unsigned long address) 1165 { 1166 return (address >> P4D_SHIFT) & (PTRS_PER_P4D - 1); 1167 } 1168 1169 #if CONFIG_PGTABLE_LEVELS > 4 1170 static inline int pgd_present(pgd_t pgd) 1171 { 1172 if (!pgtable_l5_enabled()) 1173 return 1; 1174 return pgd_flags(pgd) & _PAGE_PRESENT; 1175 } 1176 1177 static inline unsigned long pgd_page_vaddr(pgd_t pgd) 1178 { 1179 return (unsigned long)__va((unsigned long)pgd_val(pgd) & PTE_PFN_MASK); 1180 } 1181 1182 /* 1183 * Currently stuck as a macro due to indirect forward reference to 1184 * linux/mmzone.h's __section_mem_map_addr() definition: 1185 */ 1186 #define pgd_page(pgd) pfn_to_page(pgd_pfn(pgd)) 1187 1188 /* to find an entry in a page-table-directory. */ 1189 static inline p4d_t *p4d_offset(pgd_t *pgd, unsigned long address) 1190 { 1191 if (!pgtable_l5_enabled()) 1192 return (p4d_t *)pgd; 1193 return (p4d_t *)pgd_page_vaddr(*pgd) + p4d_index(address); 1194 } 1195 1196 static inline int pgd_bad(pgd_t pgd) 1197 { 1198 unsigned long ignore_flags = _PAGE_USER; 1199 1200 if (!pgtable_l5_enabled()) 1201 return 0; 1202 1203 if (IS_ENABLED(CONFIG_MITIGATION_PAGE_TABLE_ISOLATION)) 1204 ignore_flags |= _PAGE_NX; 1205 1206 return (pgd_flags(pgd) & ~ignore_flags) != _KERNPG_TABLE; 1207 } 1208 1209 static inline int pgd_none(pgd_t pgd) 1210 { 1211 if (!pgtable_l5_enabled()) 1212 return 0; 1213 /* 1214 * There is no need to do a workaround for the KNL stray 1215 * A/D bit erratum here. PGDs only point to page tables 1216 * except on 32-bit non-PAE which is not supported on 1217 * KNL. 1218 */ 1219 return !native_pgd_val(pgd); 1220 } 1221 #endif /* CONFIG_PGTABLE_LEVELS > 4 */ 1222 1223 #endif /* __ASSEMBLER__ */ 1224 1225 #define KERNEL_PGD_BOUNDARY pgd_index(PAGE_OFFSET) 1226 #define KERNEL_PGD_PTRS (PTRS_PER_PGD - KERNEL_PGD_BOUNDARY) 1227 1228 #ifndef __ASSEMBLER__ 1229 1230 extern int direct_gbpages; 1231 void init_mem_mapping(void); 1232 void early_alloc_pgt_buf(void); 1233 void __init poking_init(void); 1234 unsigned long init_memory_mapping(unsigned long start, 1235 unsigned long end, pgprot_t prot); 1236 1237 #ifdef CONFIG_X86_64 1238 extern pgd_t trampoline_pgd_entry; 1239 #endif 1240 1241 /* local pte updates need not use xchg for locking */ 1242 static inline pte_t native_local_ptep_get_and_clear(pte_t *ptep) 1243 { 1244 pte_t res = *ptep; 1245 1246 /* Pure native function needs no input for mm, addr */ 1247 native_pte_clear(NULL, 0, ptep); 1248 return res; 1249 } 1250 1251 static inline pmd_t native_local_pmdp_get_and_clear(pmd_t *pmdp) 1252 { 1253 pmd_t res = *pmdp; 1254 1255 native_pmd_clear(pmdp); 1256 return res; 1257 } 1258 1259 static inline pud_t native_local_pudp_get_and_clear(pud_t *pudp) 1260 { 1261 pud_t res = *pudp; 1262 1263 native_pud_clear(pudp); 1264 return res; 1265 } 1266 1267 static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr, 1268 pmd_t *pmdp, pmd_t pmd) 1269 { 1270 page_table_check_pmd_set(mm, pmdp, pmd); 1271 set_pmd(pmdp, pmd); 1272 } 1273 1274 static inline void set_pud_at(struct mm_struct *mm, unsigned long addr, 1275 pud_t *pudp, pud_t pud) 1276 { 1277 page_table_check_pud_set(mm, pudp, pud); 1278 native_set_pud(pudp, pud); 1279 } 1280 1281 /* 1282 * We only update the dirty/accessed state if we set 1283 * the dirty bit by hand in the kernel, since the hardware 1284 * will do the accessed bit for us, and we don't want to 1285 * race with other CPU's that might be updating the dirty 1286 * bit at the same time. 1287 */ 1288 struct vm_area_struct; 1289 1290 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 1291 extern int ptep_set_access_flags(struct vm_area_struct *vma, 1292 unsigned long address, pte_t *ptep, 1293 pte_t entry, int dirty); 1294 1295 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 1296 extern int ptep_test_and_clear_young(struct vm_area_struct *vma, 1297 unsigned long addr, pte_t *ptep); 1298 1299 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 1300 extern int ptep_clear_flush_young(struct vm_area_struct *vma, 1301 unsigned long address, pte_t *ptep); 1302 1303 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 1304 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, 1305 pte_t *ptep) 1306 { 1307 pte_t pte = native_ptep_get_and_clear(ptep); 1308 page_table_check_pte_clear(mm, pte); 1309 return pte; 1310 } 1311 1312 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL 1313 static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm, 1314 unsigned long addr, pte_t *ptep, 1315 int full) 1316 { 1317 pte_t pte; 1318 if (full) { 1319 /* 1320 * Full address destruction in progress; paravirt does not 1321 * care about updates and native needs no locking 1322 */ 1323 pte = native_local_ptep_get_and_clear(ptep); 1324 page_table_check_pte_clear(mm, pte); 1325 } else { 1326 pte = ptep_get_and_clear(mm, addr, ptep); 1327 } 1328 return pte; 1329 } 1330 1331 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 1332 static inline void ptep_set_wrprotect(struct mm_struct *mm, 1333 unsigned long addr, pte_t *ptep) 1334 { 1335 /* 1336 * Avoid accidentally creating shadow stack PTEs 1337 * (Write=0,Dirty=1). Use cmpxchg() to prevent races with 1338 * the hardware setting Dirty=1. 1339 */ 1340 pte_t old_pte, new_pte; 1341 1342 old_pte = READ_ONCE(*ptep); 1343 do { 1344 new_pte = pte_wrprotect(old_pte); 1345 } while (!try_cmpxchg((long *)&ptep->pte, (long *)&old_pte, *(long *)&new_pte)); 1346 } 1347 1348 #define flush_tlb_fix_spurious_fault(vma, address, ptep) do { } while (0) 1349 1350 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 1351 extern int pmdp_set_access_flags(struct vm_area_struct *vma, 1352 unsigned long address, pmd_t *pmdp, 1353 pmd_t entry, int dirty); 1354 extern int pudp_set_access_flags(struct vm_area_struct *vma, 1355 unsigned long address, pud_t *pudp, 1356 pud_t entry, int dirty); 1357 1358 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 1359 extern int pmdp_test_and_clear_young(struct vm_area_struct *vma, 1360 unsigned long addr, pmd_t *pmdp); 1361 extern int pudp_test_and_clear_young(struct vm_area_struct *vma, 1362 unsigned long addr, pud_t *pudp); 1363 1364 #define __HAVE_ARCH_PMDP_CLEAR_YOUNG_FLUSH 1365 extern int pmdp_clear_flush_young(struct vm_area_struct *vma, 1366 unsigned long address, pmd_t *pmdp); 1367 1368 1369 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 1370 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, unsigned long addr, 1371 pmd_t *pmdp) 1372 { 1373 pmd_t pmd = native_pmdp_get_and_clear(pmdp); 1374 1375 page_table_check_pmd_clear(mm, pmd); 1376 1377 return pmd; 1378 } 1379 1380 #define __HAVE_ARCH_PUDP_HUGE_GET_AND_CLEAR 1381 static inline pud_t pudp_huge_get_and_clear(struct mm_struct *mm, 1382 unsigned long addr, pud_t *pudp) 1383 { 1384 pud_t pud = native_pudp_get_and_clear(pudp); 1385 1386 page_table_check_pud_clear(mm, pud); 1387 1388 return pud; 1389 } 1390 1391 #define __HAVE_ARCH_PMDP_SET_WRPROTECT 1392 static inline void pmdp_set_wrprotect(struct mm_struct *mm, 1393 unsigned long addr, pmd_t *pmdp) 1394 { 1395 /* 1396 * Avoid accidentally creating shadow stack PTEs 1397 * (Write=0,Dirty=1). Use cmpxchg() to prevent races with 1398 * the hardware setting Dirty=1. 1399 */ 1400 pmd_t old_pmd, new_pmd; 1401 1402 old_pmd = READ_ONCE(*pmdp); 1403 do { 1404 new_pmd = pmd_wrprotect(old_pmd); 1405 } while (!try_cmpxchg((long *)pmdp, (long *)&old_pmd, *(long *)&new_pmd)); 1406 } 1407 1408 #ifndef pmdp_establish 1409 #define pmdp_establish pmdp_establish 1410 static inline pmd_t pmdp_establish(struct vm_area_struct *vma, 1411 unsigned long address, pmd_t *pmdp, pmd_t pmd) 1412 { 1413 page_table_check_pmd_set(vma->vm_mm, pmdp, pmd); 1414 if (IS_ENABLED(CONFIG_SMP)) { 1415 return xchg(pmdp, pmd); 1416 } else { 1417 pmd_t old = *pmdp; 1418 WRITE_ONCE(*pmdp, pmd); 1419 return old; 1420 } 1421 } 1422 #endif 1423 1424 #ifdef CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD 1425 static inline pud_t pudp_establish(struct vm_area_struct *vma, 1426 unsigned long address, pud_t *pudp, pud_t pud) 1427 { 1428 page_table_check_pud_set(vma->vm_mm, pudp, pud); 1429 if (IS_ENABLED(CONFIG_SMP)) { 1430 return xchg(pudp, pud); 1431 } else { 1432 pud_t old = *pudp; 1433 WRITE_ONCE(*pudp, pud); 1434 return old; 1435 } 1436 } 1437 #endif 1438 1439 #define __HAVE_ARCH_PMDP_INVALIDATE_AD 1440 extern pmd_t pmdp_invalidate_ad(struct vm_area_struct *vma, 1441 unsigned long address, pmd_t *pmdp); 1442 1443 pud_t pudp_invalidate(struct vm_area_struct *vma, unsigned long address, 1444 pud_t *pudp); 1445 1446 /* 1447 * Page table pages are page-aligned. The lower half of the top 1448 * level is used for userspace and the top half for the kernel. 1449 * 1450 * Returns true for parts of the PGD that map userspace and 1451 * false for the parts that map the kernel. 1452 */ 1453 static inline bool pgdp_maps_userspace(void *__ptr) 1454 { 1455 unsigned long ptr = (unsigned long)__ptr; 1456 1457 return (((ptr & ~PAGE_MASK) / sizeof(pgd_t)) < PGD_KERNEL_START); 1458 } 1459 1460 #define pgd_leaf pgd_leaf 1461 static inline bool pgd_leaf(pgd_t pgd) { return false; } 1462 1463 #ifdef CONFIG_MITIGATION_PAGE_TABLE_ISOLATION 1464 /* 1465 * All top-level MITIGATION_PAGE_TABLE_ISOLATION page tables are order-1 pages 1466 * (8k-aligned and 8k in size). The kernel one is at the beginning 4k and 1467 * the user one is in the last 4k. To switch between them, you 1468 * just need to flip the 12th bit in their addresses. 1469 */ 1470 #define PTI_PGTABLE_SWITCH_BIT PAGE_SHIFT 1471 1472 /* 1473 * This generates better code than the inline assembly in 1474 * __set_bit(). 1475 */ 1476 static inline void *ptr_set_bit(void *ptr, int bit) 1477 { 1478 unsigned long __ptr = (unsigned long)ptr; 1479 1480 __ptr |= BIT(bit); 1481 return (void *)__ptr; 1482 } 1483 static inline void *ptr_clear_bit(void *ptr, int bit) 1484 { 1485 unsigned long __ptr = (unsigned long)ptr; 1486 1487 __ptr &= ~BIT(bit); 1488 return (void *)__ptr; 1489 } 1490 1491 static inline pgd_t *kernel_to_user_pgdp(pgd_t *pgdp) 1492 { 1493 return ptr_set_bit(pgdp, PTI_PGTABLE_SWITCH_BIT); 1494 } 1495 1496 static inline pgd_t *user_to_kernel_pgdp(pgd_t *pgdp) 1497 { 1498 return ptr_clear_bit(pgdp, PTI_PGTABLE_SWITCH_BIT); 1499 } 1500 1501 static inline p4d_t *kernel_to_user_p4dp(p4d_t *p4dp) 1502 { 1503 return ptr_set_bit(p4dp, PTI_PGTABLE_SWITCH_BIT); 1504 } 1505 1506 static inline p4d_t *user_to_kernel_p4dp(p4d_t *p4dp) 1507 { 1508 return ptr_clear_bit(p4dp, PTI_PGTABLE_SWITCH_BIT); 1509 } 1510 #endif /* CONFIG_MITIGATION_PAGE_TABLE_ISOLATION */ 1511 1512 /* 1513 * clone_pgd_range(pgd_t *dst, pgd_t *src, int count); 1514 * 1515 * dst - pointer to pgd range anywhere on a pgd page 1516 * src - "" 1517 * count - the number of pgds to copy. 1518 * 1519 * dst and src can be on the same page, but the range must not overlap, 1520 * and must not cross a page boundary. 1521 */ 1522 static inline void clone_pgd_range(pgd_t *dst, pgd_t *src, int count) 1523 { 1524 memcpy(dst, src, count * sizeof(pgd_t)); 1525 #ifdef CONFIG_MITIGATION_PAGE_TABLE_ISOLATION 1526 if (!static_cpu_has(X86_FEATURE_PTI)) 1527 return; 1528 /* Clone the user space pgd as well */ 1529 memcpy(kernel_to_user_pgdp(dst), kernel_to_user_pgdp(src), 1530 count * sizeof(pgd_t)); 1531 #endif 1532 } 1533 1534 #define PTE_SHIFT ilog2(PTRS_PER_PTE) 1535 static inline int page_level_shift(enum pg_level level) 1536 { 1537 return (PAGE_SHIFT - PTE_SHIFT) + level * PTE_SHIFT; 1538 } 1539 static inline unsigned long page_level_size(enum pg_level level) 1540 { 1541 return 1UL << page_level_shift(level); 1542 } 1543 static inline unsigned long page_level_mask(enum pg_level level) 1544 { 1545 return ~(page_level_size(level) - 1); 1546 } 1547 1548 /* 1549 * The x86 doesn't have any external MMU info: the kernel page 1550 * tables contain all the necessary information. 1551 */ 1552 static inline void update_mmu_cache(struct vm_area_struct *vma, 1553 unsigned long addr, pte_t *ptep) 1554 { 1555 } 1556 static inline void update_mmu_cache_range(struct vm_fault *vmf, 1557 struct vm_area_struct *vma, unsigned long addr, 1558 pte_t *ptep, unsigned int nr) 1559 { 1560 } 1561 static inline void update_mmu_cache_pmd(struct vm_area_struct *vma, 1562 unsigned long addr, pmd_t *pmd) 1563 { 1564 } 1565 static inline void update_mmu_cache_pud(struct vm_area_struct *vma, 1566 unsigned long addr, pud_t *pud) 1567 { 1568 } 1569 static inline pte_t pte_swp_mkexclusive(pte_t pte) 1570 { 1571 return pte_set_flags(pte, _PAGE_SWP_EXCLUSIVE); 1572 } 1573 1574 static inline int pte_swp_exclusive(pte_t pte) 1575 { 1576 return pte_flags(pte) & _PAGE_SWP_EXCLUSIVE; 1577 } 1578 1579 static inline pte_t pte_swp_clear_exclusive(pte_t pte) 1580 { 1581 return pte_clear_flags(pte, _PAGE_SWP_EXCLUSIVE); 1582 } 1583 1584 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 1585 static inline pte_t pte_swp_mksoft_dirty(pte_t pte) 1586 { 1587 return pte_set_flags(pte, _PAGE_SWP_SOFT_DIRTY); 1588 } 1589 1590 static inline int pte_swp_soft_dirty(pte_t pte) 1591 { 1592 return pte_flags(pte) & _PAGE_SWP_SOFT_DIRTY; 1593 } 1594 1595 static inline pte_t pte_swp_clear_soft_dirty(pte_t pte) 1596 { 1597 return pte_clear_flags(pte, _PAGE_SWP_SOFT_DIRTY); 1598 } 1599 1600 #ifdef CONFIG_ARCH_ENABLE_THP_MIGRATION 1601 static inline pmd_t pmd_swp_mksoft_dirty(pmd_t pmd) 1602 { 1603 return pmd_set_flags(pmd, _PAGE_SWP_SOFT_DIRTY); 1604 } 1605 1606 static inline int pmd_swp_soft_dirty(pmd_t pmd) 1607 { 1608 return pmd_flags(pmd) & _PAGE_SWP_SOFT_DIRTY; 1609 } 1610 1611 static inline pmd_t pmd_swp_clear_soft_dirty(pmd_t pmd) 1612 { 1613 return pmd_clear_flags(pmd, _PAGE_SWP_SOFT_DIRTY); 1614 } 1615 #endif 1616 #endif 1617 1618 #ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP 1619 static inline pte_t pte_swp_mkuffd_wp(pte_t pte) 1620 { 1621 return pte_set_flags(pte, _PAGE_SWP_UFFD_WP); 1622 } 1623 1624 static inline int pte_swp_uffd_wp(pte_t pte) 1625 { 1626 return pte_flags(pte) & _PAGE_SWP_UFFD_WP; 1627 } 1628 1629 static inline pte_t pte_swp_clear_uffd_wp(pte_t pte) 1630 { 1631 return pte_clear_flags(pte, _PAGE_SWP_UFFD_WP); 1632 } 1633 1634 static inline pmd_t pmd_swp_mkuffd_wp(pmd_t pmd) 1635 { 1636 return pmd_set_flags(pmd, _PAGE_SWP_UFFD_WP); 1637 } 1638 1639 static inline int pmd_swp_uffd_wp(pmd_t pmd) 1640 { 1641 return pmd_flags(pmd) & _PAGE_SWP_UFFD_WP; 1642 } 1643 1644 static inline pmd_t pmd_swp_clear_uffd_wp(pmd_t pmd) 1645 { 1646 return pmd_clear_flags(pmd, _PAGE_SWP_UFFD_WP); 1647 } 1648 #endif /* CONFIG_HAVE_ARCH_USERFAULTFD_WP */ 1649 1650 static inline u16 pte_flags_pkey(unsigned long pte_flags) 1651 { 1652 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS 1653 /* ifdef to avoid doing 59-bit shift on 32-bit values */ 1654 return (pte_flags & _PAGE_PKEY_MASK) >> _PAGE_BIT_PKEY_BIT0; 1655 #else 1656 return 0; 1657 #endif 1658 } 1659 1660 static inline bool __pkru_allows_pkey(u16 pkey, bool write) 1661 { 1662 u32 pkru = read_pkru(); 1663 1664 if (!__pkru_allows_read(pkru, pkey)) 1665 return false; 1666 if (write && !__pkru_allows_write(pkru, pkey)) 1667 return false; 1668 1669 return true; 1670 } 1671 1672 /* 1673 * 'pteval' can come from a PTE, PMD or PUD. We only check 1674 * _PAGE_PRESENT, _PAGE_USER, and _PAGE_RW in here which are the 1675 * same value on all 3 types. 1676 */ 1677 static inline bool __pte_access_permitted(unsigned long pteval, bool write) 1678 { 1679 unsigned long need_pte_bits = _PAGE_PRESENT|_PAGE_USER; 1680 1681 /* 1682 * Write=0,Dirty=1 PTEs are shadow stack, which the kernel 1683 * shouldn't generally allow access to, but since they 1684 * are already Write=0, the below logic covers both cases. 1685 */ 1686 if (write) 1687 need_pte_bits |= _PAGE_RW; 1688 1689 if ((pteval & need_pte_bits) != need_pte_bits) 1690 return 0; 1691 1692 return __pkru_allows_pkey(pte_flags_pkey(pteval), write); 1693 } 1694 1695 #define pte_access_permitted pte_access_permitted 1696 static inline bool pte_access_permitted(pte_t pte, bool write) 1697 { 1698 return __pte_access_permitted(pte_val(pte), write); 1699 } 1700 1701 #define pmd_access_permitted pmd_access_permitted 1702 static inline bool pmd_access_permitted(pmd_t pmd, bool write) 1703 { 1704 return __pte_access_permitted(pmd_val(pmd), write); 1705 } 1706 1707 #define pud_access_permitted pud_access_permitted 1708 static inline bool pud_access_permitted(pud_t pud, bool write) 1709 { 1710 return __pte_access_permitted(pud_val(pud), write); 1711 } 1712 1713 #define __HAVE_ARCH_PFN_MODIFY_ALLOWED 1 1714 extern bool pfn_modify_allowed(unsigned long pfn, pgprot_t prot); 1715 1716 static inline bool arch_has_pfn_modify_check(void) 1717 { 1718 return boot_cpu_has_bug(X86_BUG_L1TF); 1719 } 1720 1721 #define arch_check_zapped_pte arch_check_zapped_pte 1722 void arch_check_zapped_pte(struct vm_area_struct *vma, pte_t pte); 1723 1724 #define arch_check_zapped_pmd arch_check_zapped_pmd 1725 void arch_check_zapped_pmd(struct vm_area_struct *vma, pmd_t pmd); 1726 1727 #define arch_check_zapped_pud arch_check_zapped_pud 1728 void arch_check_zapped_pud(struct vm_area_struct *vma, pud_t pud); 1729 1730 #ifdef CONFIG_XEN_PV 1731 #define arch_has_hw_nonleaf_pmd_young arch_has_hw_nonleaf_pmd_young 1732 static inline bool arch_has_hw_nonleaf_pmd_young(void) 1733 { 1734 return !cpu_feature_enabled(X86_FEATURE_XENPV); 1735 } 1736 #endif 1737 1738 #ifdef CONFIG_PAGE_TABLE_CHECK 1739 static inline bool pte_user_accessible_page(pte_t pte) 1740 { 1741 return (pte_val(pte) & _PAGE_PRESENT) && (pte_val(pte) & _PAGE_USER); 1742 } 1743 1744 static inline bool pmd_user_accessible_page(pmd_t pmd) 1745 { 1746 return pmd_leaf(pmd) && (pmd_val(pmd) & _PAGE_PRESENT) && (pmd_val(pmd) & _PAGE_USER); 1747 } 1748 1749 static inline bool pud_user_accessible_page(pud_t pud) 1750 { 1751 return pud_leaf(pud) && (pud_val(pud) & _PAGE_PRESENT) && (pud_val(pud) & _PAGE_USER); 1752 } 1753 #endif 1754 1755 #ifdef CONFIG_X86_SGX 1756 int arch_memory_failure(unsigned long pfn, int flags); 1757 #define arch_memory_failure arch_memory_failure 1758 1759 bool arch_is_platform_page(u64 paddr); 1760 #define arch_is_platform_page arch_is_platform_page 1761 #endif 1762 1763 /* 1764 * Use set_p*_safe(), and elide TLB flushing, when confident that *no* 1765 * TLB flush will be required as a result of the "set". For example, use 1766 * in scenarios where it is known ahead of time that the routine is 1767 * setting non-present entries, or re-setting an existing entry to the 1768 * same value. Otherwise, use the typical "set" helpers and flush the 1769 * TLB. 1770 */ 1771 #define set_pte_safe(ptep, pte) \ 1772 ({ \ 1773 WARN_ON_ONCE(pte_present(*ptep) && !pte_same(*ptep, pte)); \ 1774 set_pte(ptep, pte); \ 1775 }) 1776 1777 #define set_pmd_safe(pmdp, pmd) \ 1778 ({ \ 1779 WARN_ON_ONCE(pmd_present(*pmdp) && !pmd_same(*pmdp, pmd)); \ 1780 set_pmd(pmdp, pmd); \ 1781 }) 1782 1783 #define set_pud_safe(pudp, pud) \ 1784 ({ \ 1785 WARN_ON_ONCE(pud_present(*pudp) && !pud_same(*pudp, pud)); \ 1786 set_pud(pudp, pud); \ 1787 }) 1788 1789 #define set_p4d_safe(p4dp, p4d) \ 1790 ({ \ 1791 WARN_ON_ONCE(p4d_present(*p4dp) && !p4d_same(*p4dp, p4d)); \ 1792 set_p4d(p4dp, p4d); \ 1793 }) 1794 1795 #define set_pgd_safe(pgdp, pgd) \ 1796 ({ \ 1797 WARN_ON_ONCE(pgd_present(*pgdp) && !pgd_same(*pgdp, pgd)); \ 1798 set_pgd(pgdp, pgd); \ 1799 }) 1800 #endif /* __ASSEMBLER__ */ 1801 1802 #endif /* _ASM_X86_PGTABLE_H */ 1803