1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _ASM_X86_PGTABLE_3LEVEL_H 3 #define _ASM_X86_PGTABLE_3LEVEL_H 4 5 /* 6 * Intel Physical Address Extension (PAE) Mode - three-level page 7 * tables on PPro+ CPUs. 8 * 9 * Copyright (C) 1999 Ingo Molnar <mingo@redhat.com> 10 */ 11 #define pxx_xchg64(_pxx, _ptr, _val) ({ \ 12 _pxx##val_t *_p = (_pxx##val_t *)_ptr; \ 13 _pxx##val_t _o = *_p; \ 14 do { } while (!try_cmpxchg64(_p, &_o, (_val))); \ 15 native_make_##_pxx(_o); \ 16 }) 17 18 /* 19 * Rules for using set_pte: the pte being assigned *must* be 20 * either not present or in a state where the hardware will 21 * not attempt to update the pte. In places where this is 22 * not possible, use pte_get_and_clear to obtain the old pte 23 * value and then use set_pte to update it. -ben 24 */ 25 static inline void native_set_pte(pte_t *ptep, pte_t pte) 26 { 27 WRITE_ONCE(ptep->pte_high, pte.pte_high); 28 smp_wmb(); 29 WRITE_ONCE(ptep->pte_low, pte.pte_low); 30 } 31 32 static inline void native_set_pte_atomic(pte_t *ptep, pte_t pte) 33 { 34 pxx_xchg64(pte, ptep, native_pte_val(pte)); 35 } 36 37 static inline void native_set_pmd(pmd_t *pmdp, pmd_t pmd) 38 { 39 pxx_xchg64(pmd, pmdp, native_pmd_val(pmd)); 40 } 41 42 static inline void native_set_pud(pud_t *pudp, pud_t pud) 43 { 44 #ifdef CONFIG_MITIGATION_PAGE_TABLE_ISOLATION 45 pud.p4d.pgd = pti_set_user_pgtbl(&pudp->p4d.pgd, pud.p4d.pgd); 46 #endif 47 pxx_xchg64(pud, pudp, native_pud_val(pud)); 48 } 49 50 /* 51 * For PTEs and PDEs, we must clear the P-bit first when clearing a page table 52 * entry, so clear the bottom half first and enforce ordering with a compiler 53 * barrier. 54 */ 55 static inline void native_pte_clear(struct mm_struct *mm, unsigned long addr, 56 pte_t *ptep) 57 { 58 WRITE_ONCE(ptep->pte_low, 0); 59 smp_wmb(); 60 WRITE_ONCE(ptep->pte_high, 0); 61 } 62 63 static inline void native_pmd_clear(pmd_t *pmdp) 64 { 65 WRITE_ONCE(pmdp->pmd_low, 0); 66 smp_wmb(); 67 WRITE_ONCE(pmdp->pmd_high, 0); 68 } 69 70 static inline void native_pud_clear(pud_t *pudp) 71 { 72 } 73 74 static inline void pud_clear(pud_t *pudp) 75 { 76 set_pud(pudp, __pud(0)); 77 78 /* 79 * According to Intel App note "TLBs, Paging-Structure Caches, 80 * and Their Invalidation", April 2007, document 317080-001, 81 * section 8.1: in PAE mode we explicitly have to flush the 82 * TLB via cr3 if the top-level pgd is changed... 83 * 84 * Currently all places where pud_clear() is called either have 85 * flush_tlb_mm() followed or don't need TLB flush (x86_64 code or 86 * pud_clear_bad()), so we don't need TLB flush here. 87 */ 88 } 89 90 91 #ifdef CONFIG_SMP 92 static inline pte_t native_ptep_get_and_clear(pte_t *ptep) 93 { 94 return pxx_xchg64(pte, ptep, 0ULL); 95 } 96 97 static inline pmd_t native_pmdp_get_and_clear(pmd_t *pmdp) 98 { 99 return pxx_xchg64(pmd, pmdp, 0ULL); 100 } 101 102 static inline pud_t native_pudp_get_and_clear(pud_t *pudp) 103 { 104 return pxx_xchg64(pud, pudp, 0ULL); 105 } 106 #else 107 #define native_ptep_get_and_clear(xp) native_local_ptep_get_and_clear(xp) 108 #define native_pmdp_get_and_clear(xp) native_local_pmdp_get_and_clear(xp) 109 #define native_pudp_get_and_clear(xp) native_local_pudp_get_and_clear(xp) 110 #endif 111 112 #ifndef pmdp_establish 113 #define pmdp_establish pmdp_establish 114 static inline pmd_t pmdp_establish(struct vm_area_struct *vma, 115 unsigned long address, pmd_t *pmdp, pmd_t pmd) 116 { 117 pmd_t old; 118 119 /* 120 * If pmd has present bit cleared we can get away without expensive 121 * cmpxchg64: we can update pmdp half-by-half without racing with 122 * anybody. 123 */ 124 if (!(pmd_val(pmd) & _PAGE_PRESENT)) { 125 /* xchg acts as a barrier before setting of the high bits */ 126 old.pmd_low = xchg(&pmdp->pmd_low, pmd.pmd_low); 127 old.pmd_high = READ_ONCE(pmdp->pmd_high); 128 WRITE_ONCE(pmdp->pmd_high, pmd.pmd_high); 129 130 return old; 131 } 132 133 return pxx_xchg64(pmd, pmdp, pmd.pmd); 134 } 135 #endif 136 137 /* 138 * Encode/decode swap entries and swap PTEs. Swap PTEs are all PTEs that 139 * are !pte_none() && !pte_present(). 140 * 141 * Format of swap PTEs: 142 * 143 * 6 6 6 6 5 5 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 144 * 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 145 * < type -> <---------------------- offset ---------------------- 146 * 147 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 148 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 149 * --------------------------------------------> 0 E 0 0 0 0 0 0 0 150 * 151 * E is the exclusive marker that is not stored in swap entries. 152 */ 153 #define SWP_TYPE_BITS 5 154 #define _SWP_TYPE_MASK ((1U << SWP_TYPE_BITS) - 1) 155 156 #define SWP_OFFSET_FIRST_BIT (_PAGE_BIT_PROTNONE + 1) 157 158 /* We always extract/encode the offset by shifting it all the way up, and then down again */ 159 #define SWP_OFFSET_SHIFT (SWP_OFFSET_FIRST_BIT + SWP_TYPE_BITS) 160 161 #define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > SWP_TYPE_BITS) 162 #define __swp_type(x) (((x).val) & _SWP_TYPE_MASK) 163 #define __swp_offset(x) ((x).val >> SWP_TYPE_BITS) 164 #define __swp_entry(type, offset) ((swp_entry_t){((type) & _SWP_TYPE_MASK) \ 165 | (offset) << SWP_TYPE_BITS}) 166 167 /* 168 * Normally, __swp_entry() converts from arch-independent swp_entry_t to 169 * arch-dependent swp_entry_t, and __swp_entry_to_pte() just stores the result 170 * to pte. But here we have 32bit swp_entry_t and 64bit pte, and need to use the 171 * whole 64 bits. Thus, we shift the "real" arch-dependent conversion to 172 * __swp_entry_to_pte() through the following helper macro based on 64bit 173 * __swp_entry(). 174 */ 175 #define __swp_pteval_entry(type, offset) ((pteval_t) { \ 176 (~(pteval_t)(offset) << SWP_OFFSET_SHIFT >> SWP_TYPE_BITS) \ 177 | ((pteval_t)(type) << (64 - SWP_TYPE_BITS)) }) 178 179 #define __swp_entry_to_pte(x) ((pte_t){ .pte = \ 180 __swp_pteval_entry(__swp_type(x), __swp_offset(x)) }) 181 /* 182 * Analogically, __pte_to_swp_entry() doesn't just extract the arch-dependent 183 * swp_entry_t, but also has to convert it from 64bit to the 32bit 184 * intermediate representation, using the following macros based on 64bit 185 * __swp_type() and __swp_offset(). 186 */ 187 #define __pteval_swp_type(x) ((unsigned long)((x).pte >> (64 - SWP_TYPE_BITS))) 188 #define __pteval_swp_offset(x) ((unsigned long)(~((x).pte) << SWP_TYPE_BITS >> SWP_OFFSET_SHIFT)) 189 190 #define __pte_to_swp_entry(pte) (__swp_entry(__pteval_swp_type(pte), \ 191 __pteval_swp_offset(pte))) 192 193 /* We borrow bit 7 to store the exclusive marker in swap PTEs. */ 194 #define _PAGE_SWP_EXCLUSIVE _PAGE_PSE 195 196 #include <asm/pgtable-invert.h> 197 198 #endif /* _ASM_X86_PGTABLE_3LEVEL_H */ 199