1a072738eSCyrill Gorcunov /* 20d2eb44fSLucas De Marchi * Netburst Performance Events (P4, old Xeon) 3a072738eSCyrill Gorcunov */ 4a072738eSCyrill Gorcunov 5a072738eSCyrill Gorcunov #ifndef PERF_EVENT_P4_H 6a072738eSCyrill Gorcunov #define PERF_EVENT_P4_H 7a072738eSCyrill Gorcunov 8a072738eSCyrill Gorcunov #include <linux/cpu.h> 9a072738eSCyrill Gorcunov #include <linux/bitops.h> 10a072738eSCyrill Gorcunov 11a072738eSCyrill Gorcunov /* 120d2eb44fSLucas De Marchi * NetBurst has performance MSRs shared between 13a072738eSCyrill Gorcunov * threads if HT is turned on, ie for both logical 14a072738eSCyrill Gorcunov * processors (mem: in turn in Atom with HT support 15a072738eSCyrill Gorcunov * perf-MSRs are not shared and every thread has its 16a072738eSCyrill Gorcunov * own perf-MSRs set) 17a072738eSCyrill Gorcunov */ 18a072738eSCyrill Gorcunov #define ARCH_P4_TOTAL_ESCR (46) 19a072738eSCyrill Gorcunov #define ARCH_P4_RESERVED_ESCR (2) /* IQ_ESCR(0,1) not always present */ 20a072738eSCyrill Gorcunov #define ARCH_P4_MAX_ESCR (ARCH_P4_TOTAL_ESCR - ARCH_P4_RESERVED_ESCR) 21a072738eSCyrill Gorcunov #define ARCH_P4_MAX_CCCR (18) 22a072738eSCyrill Gorcunov 23047a3772SCyrill Gorcunov #define ARCH_P4_CNTRVAL_BITS (40) 24047a3772SCyrill Gorcunov #define ARCH_P4_CNTRVAL_MASK ((1ULL << ARCH_P4_CNTRVAL_BITS) - 1) 257d44ec19SCyrill Gorcunov #define ARCH_P4_UNFLAGGED_BIT ((1ULL) << (ARCH_P4_CNTRVAL_BITS - 1)) 26047a3772SCyrill Gorcunov 27d814f301SCyrill Gorcunov #define P4_ESCR_EVENT_MASK 0x7e000000U 28d814f301SCyrill Gorcunov #define P4_ESCR_EVENT_SHIFT 25 29d814f301SCyrill Gorcunov #define P4_ESCR_EVENTMASK_MASK 0x01fffe00U 30d814f301SCyrill Gorcunov #define P4_ESCR_EVENTMASK_SHIFT 9 31d814f301SCyrill Gorcunov #define P4_ESCR_TAG_MASK 0x000001e0U 32d814f301SCyrill Gorcunov #define P4_ESCR_TAG_SHIFT 5 33d814f301SCyrill Gorcunov #define P4_ESCR_TAG_ENABLE 0x00000010U 34d814f301SCyrill Gorcunov #define P4_ESCR_T0_OS 0x00000008U 35d814f301SCyrill Gorcunov #define P4_ESCR_T0_USR 0x00000004U 36d814f301SCyrill Gorcunov #define P4_ESCR_T1_OS 0x00000002U 37d814f301SCyrill Gorcunov #define P4_ESCR_T1_USR 0x00000001U 38d814f301SCyrill Gorcunov 39d814f301SCyrill Gorcunov #define P4_ESCR_EVENT(v) ((v) << P4_ESCR_EVENT_SHIFT) 40d814f301SCyrill Gorcunov #define P4_ESCR_EMASK(v) ((v) << P4_ESCR_EVENTMASK_SHIFT) 41d814f301SCyrill Gorcunov #define P4_ESCR_TAG(v) ((v) << P4_ESCR_TAG_SHIFT) 42a072738eSCyrill Gorcunov 43a072738eSCyrill Gorcunov #define P4_CCCR_OVF 0x80000000U 44a072738eSCyrill Gorcunov #define P4_CCCR_CASCADE 0x40000000U 45a072738eSCyrill Gorcunov #define P4_CCCR_OVF_PMI_T0 0x04000000U 46a072738eSCyrill Gorcunov #define P4_CCCR_OVF_PMI_T1 0x08000000U 47a072738eSCyrill Gorcunov #define P4_CCCR_FORCE_OVF 0x02000000U 48a072738eSCyrill Gorcunov #define P4_CCCR_EDGE 0x01000000U 49a072738eSCyrill Gorcunov #define P4_CCCR_THRESHOLD_MASK 0x00f00000U 50a072738eSCyrill Gorcunov #define P4_CCCR_THRESHOLD_SHIFT 20 51a072738eSCyrill Gorcunov #define P4_CCCR_COMPLEMENT 0x00080000U 52a072738eSCyrill Gorcunov #define P4_CCCR_COMPARE 0x00040000U 53a072738eSCyrill Gorcunov #define P4_CCCR_ESCR_SELECT_MASK 0x0000e000U 54a072738eSCyrill Gorcunov #define P4_CCCR_ESCR_SELECT_SHIFT 13 55a072738eSCyrill Gorcunov #define P4_CCCR_ENABLE 0x00001000U 56a072738eSCyrill Gorcunov #define P4_CCCR_THREAD_SINGLE 0x00010000U 57a072738eSCyrill Gorcunov #define P4_CCCR_THREAD_BOTH 0x00020000U 58a072738eSCyrill Gorcunov #define P4_CCCR_THREAD_ANY 0x00030000U 59f34edbc1SLin Ming #define P4_CCCR_RESERVED 0x00000fffU 60a072738eSCyrill Gorcunov 61d814f301SCyrill Gorcunov #define P4_CCCR_THRESHOLD(v) ((v) << P4_CCCR_THRESHOLD_SHIFT) 62d814f301SCyrill Gorcunov #define P4_CCCR_ESEL(v) ((v) << P4_CCCR_ESCR_SELECT_SHIFT) 63d814f301SCyrill Gorcunov 64d814f301SCyrill Gorcunov #define P4_GEN_ESCR_EMASK(class, name, bit) \ 65d814f301SCyrill Gorcunov class##__##name = ((1 << bit) << P4_ESCR_EVENTMASK_SHIFT) 66d814f301SCyrill Gorcunov #define P4_ESCR_EMASK_BIT(class, name) class##__##name 67a072738eSCyrill Gorcunov 68a072738eSCyrill Gorcunov /* 69a072738eSCyrill Gorcunov * config field is 64bit width and consists of 70a072738eSCyrill Gorcunov * HT << 63 | ESCR << 32 | CCCR 71a072738eSCyrill Gorcunov * where HT is HyperThreading bit (since ESCR 72a072738eSCyrill Gorcunov * has it reserved we may use it for own purpose) 73a072738eSCyrill Gorcunov * 74a072738eSCyrill Gorcunov * note that this is NOT the addresses of respective 75a072738eSCyrill Gorcunov * ESCR and CCCR but rather an only packed value should 76a072738eSCyrill Gorcunov * be unpacked and written to a proper addresses 77a072738eSCyrill Gorcunov * 7839ef13a4SCyrill Gorcunov * the base idea is to pack as much info as possible 79a072738eSCyrill Gorcunov */ 80a072738eSCyrill Gorcunov #define p4_config_pack_escr(v) (((u64)(v)) << 32) 81a072738eSCyrill Gorcunov #define p4_config_pack_cccr(v) (((u64)(v)) & 0xffffffffULL) 82a072738eSCyrill Gorcunov #define p4_config_unpack_escr(v) (((u64)(v)) >> 32) 83d814f301SCyrill Gorcunov #define p4_config_unpack_cccr(v) (((u64)(v)) & 0xffffffffULL) 84a072738eSCyrill Gorcunov 85a072738eSCyrill Gorcunov #define p4_config_unpack_emask(v) \ 86a072738eSCyrill Gorcunov ({ \ 87a072738eSCyrill Gorcunov u32 t = p4_config_unpack_escr((v)); \ 88d814f301SCyrill Gorcunov t = t & P4_ESCR_EVENTMASK_MASK; \ 89d814f301SCyrill Gorcunov t = t >> P4_ESCR_EVENTMASK_SHIFT; \ 90a072738eSCyrill Gorcunov t; \ 91a072738eSCyrill Gorcunov }) 92a072738eSCyrill Gorcunov 93d814f301SCyrill Gorcunov #define p4_config_unpack_event(v) \ 94d814f301SCyrill Gorcunov ({ \ 95d814f301SCyrill Gorcunov u32 t = p4_config_unpack_escr((v)); \ 96d814f301SCyrill Gorcunov t = t & P4_ESCR_EVENT_MASK; \ 97d814f301SCyrill Gorcunov t = t >> P4_ESCR_EVENT_SHIFT; \ 98d814f301SCyrill Gorcunov t; \ 99d814f301SCyrill Gorcunov }) 100d814f301SCyrill Gorcunov 101a072738eSCyrill Gorcunov #define P4_CONFIG_HT_SHIFT 63 102a072738eSCyrill Gorcunov #define P4_CONFIG_HT (1ULL << P4_CONFIG_HT_SHIFT) 103a072738eSCyrill Gorcunov 104c9cf4a01SCyrill Gorcunov /* 105*f9129870SCyrill Gorcunov * If an event has alias it should be marked 106*f9129870SCyrill Gorcunov * with a special bit. (Don't forget to check 107*f9129870SCyrill Gorcunov * P4_PEBS_CONFIG_MASK and related bits on 108*f9129870SCyrill Gorcunov * modification.) 109*f9129870SCyrill Gorcunov */ 110*f9129870SCyrill Gorcunov #define P4_CONFIG_ALIASABLE (1 << 9) 111*f9129870SCyrill Gorcunov 112*f9129870SCyrill Gorcunov /* 113c9cf4a01SCyrill Gorcunov * The bits we allow to pass for RAW events 114c9cf4a01SCyrill Gorcunov */ 115c9cf4a01SCyrill Gorcunov #define P4_CONFIG_MASK_ESCR \ 116c9cf4a01SCyrill Gorcunov P4_ESCR_EVENT_MASK | \ 117c9cf4a01SCyrill Gorcunov P4_ESCR_EVENTMASK_MASK | \ 118c9cf4a01SCyrill Gorcunov P4_ESCR_TAG_MASK | \ 119c9cf4a01SCyrill Gorcunov P4_ESCR_TAG_ENABLE 120c9cf4a01SCyrill Gorcunov 121c9cf4a01SCyrill Gorcunov #define P4_CONFIG_MASK_CCCR \ 122c9cf4a01SCyrill Gorcunov P4_CCCR_EDGE | \ 123c9cf4a01SCyrill Gorcunov P4_CCCR_THRESHOLD_MASK | \ 124c9cf4a01SCyrill Gorcunov P4_CCCR_COMPLEMENT | \ 125c9cf4a01SCyrill Gorcunov P4_CCCR_COMPARE | \ 126c9cf4a01SCyrill Gorcunov P4_CCCR_THREAD_ANY | \ 127c9cf4a01SCyrill Gorcunov P4_CCCR_RESERVED 128c9cf4a01SCyrill Gorcunov 129c9cf4a01SCyrill Gorcunov /* some dangerous bits are reserved for kernel internals */ 130c9cf4a01SCyrill Gorcunov #define P4_CONFIG_MASK \ 131c9cf4a01SCyrill Gorcunov (p4_config_pack_escr(P4_CONFIG_MASK_ESCR)) | \ 132c9cf4a01SCyrill Gorcunov (p4_config_pack_cccr(P4_CONFIG_MASK_CCCR)) 133c9cf4a01SCyrill Gorcunov 134*f9129870SCyrill Gorcunov /* 135*f9129870SCyrill Gorcunov * In case of event aliasing we need to preserve some 136*f9129870SCyrill Gorcunov * caller bits otherwise the mapping won't be complete. 137*f9129870SCyrill Gorcunov */ 138*f9129870SCyrill Gorcunov #define P4_CONFIG_EVENT_ALIAS_MASK \ 139*f9129870SCyrill Gorcunov (p4_config_pack_escr(P4_CONFIG_MASK_ESCR) | \ 140*f9129870SCyrill Gorcunov p4_config_pack_cccr(P4_CCCR_EDGE | \ 141*f9129870SCyrill Gorcunov P4_CCCR_THRESHOLD_MASK | \ 142*f9129870SCyrill Gorcunov P4_CCCR_COMPLEMENT | \ 143*f9129870SCyrill Gorcunov P4_CCCR_COMPARE)) 144*f9129870SCyrill Gorcunov 145*f9129870SCyrill Gorcunov #define P4_CONFIG_EVENT_ALIAS_IMMUTABLE_BITS \ 146*f9129870SCyrill Gorcunov ((P4_CONFIG_HT) | \ 147*f9129870SCyrill Gorcunov p4_config_pack_escr(P4_ESCR_T0_OS | \ 148*f9129870SCyrill Gorcunov P4_ESCR_T0_USR | \ 149*f9129870SCyrill Gorcunov P4_ESCR_T1_OS | \ 150*f9129870SCyrill Gorcunov P4_ESCR_T1_USR) | \ 151*f9129870SCyrill Gorcunov p4_config_pack_cccr(P4_CCCR_OVF | \ 152*f9129870SCyrill Gorcunov P4_CCCR_CASCADE | \ 153*f9129870SCyrill Gorcunov P4_CCCR_FORCE_OVF | \ 154*f9129870SCyrill Gorcunov P4_CCCR_THREAD_ANY | \ 155*f9129870SCyrill Gorcunov P4_CCCR_OVF_PMI_T0 | \ 156*f9129870SCyrill Gorcunov P4_CCCR_OVF_PMI_T1 | \ 157*f9129870SCyrill Gorcunov P4_CONFIG_ALIASABLE)) 158*f9129870SCyrill Gorcunov 159a072738eSCyrill Gorcunov static inline bool p4_is_event_cascaded(u64 config) 160a072738eSCyrill Gorcunov { 161a072738eSCyrill Gorcunov u32 cccr = p4_config_unpack_cccr(config); 162a072738eSCyrill Gorcunov return !!(cccr & P4_CCCR_CASCADE); 163a072738eSCyrill Gorcunov } 164a072738eSCyrill Gorcunov 165a072738eSCyrill Gorcunov static inline int p4_ht_config_thread(u64 config) 166a072738eSCyrill Gorcunov { 167a072738eSCyrill Gorcunov return !!(config & P4_CONFIG_HT); 168a072738eSCyrill Gorcunov } 169a072738eSCyrill Gorcunov 170a072738eSCyrill Gorcunov static inline u64 p4_set_ht_bit(u64 config) 171a072738eSCyrill Gorcunov { 172a072738eSCyrill Gorcunov return config | P4_CONFIG_HT; 173a072738eSCyrill Gorcunov } 174a072738eSCyrill Gorcunov 175a072738eSCyrill Gorcunov static inline u64 p4_clear_ht_bit(u64 config) 176a072738eSCyrill Gorcunov { 177a072738eSCyrill Gorcunov return config & ~P4_CONFIG_HT; 178a072738eSCyrill Gorcunov } 179a072738eSCyrill Gorcunov 180a072738eSCyrill Gorcunov static inline int p4_ht_active(void) 181a072738eSCyrill Gorcunov { 182a072738eSCyrill Gorcunov #ifdef CONFIG_SMP 183a072738eSCyrill Gorcunov return smp_num_siblings > 1; 184a072738eSCyrill Gorcunov #endif 185a072738eSCyrill Gorcunov return 0; 186a072738eSCyrill Gorcunov } 187a072738eSCyrill Gorcunov 188a072738eSCyrill Gorcunov static inline int p4_ht_thread(int cpu) 189a072738eSCyrill Gorcunov { 190a072738eSCyrill Gorcunov #ifdef CONFIG_SMP 191a072738eSCyrill Gorcunov if (smp_num_siblings == 2) 192a072738eSCyrill Gorcunov return cpu != cpumask_first(__get_cpu_var(cpu_sibling_map)); 193a072738eSCyrill Gorcunov #endif 194a072738eSCyrill Gorcunov return 0; 195a072738eSCyrill Gorcunov } 196a072738eSCyrill Gorcunov 197a072738eSCyrill Gorcunov static inline int p4_should_swap_ts(u64 config, int cpu) 198a072738eSCyrill Gorcunov { 199a072738eSCyrill Gorcunov return p4_ht_config_thread(config) ^ p4_ht_thread(cpu); 200a072738eSCyrill Gorcunov } 201a072738eSCyrill Gorcunov 202a072738eSCyrill Gorcunov static inline u32 p4_default_cccr_conf(int cpu) 203a072738eSCyrill Gorcunov { 204a072738eSCyrill Gorcunov /* 205a072738eSCyrill Gorcunov * Note that P4_CCCR_THREAD_ANY is "required" on 206a072738eSCyrill Gorcunov * non-HT machines (on HT machines we count TS events 207a072738eSCyrill Gorcunov * regardless the state of second logical processor 208a072738eSCyrill Gorcunov */ 209a072738eSCyrill Gorcunov u32 cccr = P4_CCCR_THREAD_ANY; 210a072738eSCyrill Gorcunov 211a072738eSCyrill Gorcunov if (!p4_ht_thread(cpu)) 212a072738eSCyrill Gorcunov cccr |= P4_CCCR_OVF_PMI_T0; 213a072738eSCyrill Gorcunov else 214a072738eSCyrill Gorcunov cccr |= P4_CCCR_OVF_PMI_T1; 215a072738eSCyrill Gorcunov 216a072738eSCyrill Gorcunov return cccr; 217a072738eSCyrill Gorcunov } 218a072738eSCyrill Gorcunov 219a072738eSCyrill Gorcunov static inline u32 p4_default_escr_conf(int cpu, int exclude_os, int exclude_usr) 220a072738eSCyrill Gorcunov { 221a072738eSCyrill Gorcunov u32 escr = 0; 222a072738eSCyrill Gorcunov 223a072738eSCyrill Gorcunov if (!p4_ht_thread(cpu)) { 224a072738eSCyrill Gorcunov if (!exclude_os) 225d814f301SCyrill Gorcunov escr |= P4_ESCR_T0_OS; 226a072738eSCyrill Gorcunov if (!exclude_usr) 227d814f301SCyrill Gorcunov escr |= P4_ESCR_T0_USR; 228a072738eSCyrill Gorcunov } else { 229a072738eSCyrill Gorcunov if (!exclude_os) 230d814f301SCyrill Gorcunov escr |= P4_ESCR_T1_OS; 231a072738eSCyrill Gorcunov if (!exclude_usr) 232d814f301SCyrill Gorcunov escr |= P4_ESCR_T1_USR; 233a072738eSCyrill Gorcunov } 234a072738eSCyrill Gorcunov 235a072738eSCyrill Gorcunov return escr; 236a072738eSCyrill Gorcunov } 237a072738eSCyrill Gorcunov 23839ef13a4SCyrill Gorcunov /* 23939ef13a4SCyrill Gorcunov * This are the events which should be used in "Event Select" 24039ef13a4SCyrill Gorcunov * field of ESCR register, they are like unique keys which allow 24139ef13a4SCyrill Gorcunov * the kernel to determinate which CCCR and COUNTER should be 24239ef13a4SCyrill Gorcunov * used to track an event 24339ef13a4SCyrill Gorcunov */ 244d814f301SCyrill Gorcunov enum P4_EVENTS { 245d814f301SCyrill Gorcunov P4_EVENT_TC_DELIVER_MODE, 246d814f301SCyrill Gorcunov P4_EVENT_BPU_FETCH_REQUEST, 247d814f301SCyrill Gorcunov P4_EVENT_ITLB_REFERENCE, 248d814f301SCyrill Gorcunov P4_EVENT_MEMORY_CANCEL, 249d814f301SCyrill Gorcunov P4_EVENT_MEMORY_COMPLETE, 250d814f301SCyrill Gorcunov P4_EVENT_LOAD_PORT_REPLAY, 251d814f301SCyrill Gorcunov P4_EVENT_STORE_PORT_REPLAY, 252d814f301SCyrill Gorcunov P4_EVENT_MOB_LOAD_REPLAY, 253d814f301SCyrill Gorcunov P4_EVENT_PAGE_WALK_TYPE, 254d814f301SCyrill Gorcunov P4_EVENT_BSQ_CACHE_REFERENCE, 255d814f301SCyrill Gorcunov P4_EVENT_IOQ_ALLOCATION, 256d814f301SCyrill Gorcunov P4_EVENT_IOQ_ACTIVE_ENTRIES, 257d814f301SCyrill Gorcunov P4_EVENT_FSB_DATA_ACTIVITY, 258d814f301SCyrill Gorcunov P4_EVENT_BSQ_ALLOCATION, 259d814f301SCyrill Gorcunov P4_EVENT_BSQ_ACTIVE_ENTRIES, 260d814f301SCyrill Gorcunov P4_EVENT_SSE_INPUT_ASSIST, 261d814f301SCyrill Gorcunov P4_EVENT_PACKED_SP_UOP, 262d814f301SCyrill Gorcunov P4_EVENT_PACKED_DP_UOP, 263d814f301SCyrill Gorcunov P4_EVENT_SCALAR_SP_UOP, 264d814f301SCyrill Gorcunov P4_EVENT_SCALAR_DP_UOP, 265d814f301SCyrill Gorcunov P4_EVENT_64BIT_MMX_UOP, 266d814f301SCyrill Gorcunov P4_EVENT_128BIT_MMX_UOP, 267d814f301SCyrill Gorcunov P4_EVENT_X87_FP_UOP, 268d814f301SCyrill Gorcunov P4_EVENT_TC_MISC, 269d814f301SCyrill Gorcunov P4_EVENT_GLOBAL_POWER_EVENTS, 270d814f301SCyrill Gorcunov P4_EVENT_TC_MS_XFER, 271d814f301SCyrill Gorcunov P4_EVENT_UOP_QUEUE_WRITES, 272d814f301SCyrill Gorcunov P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE, 273d814f301SCyrill Gorcunov P4_EVENT_RETIRED_BRANCH_TYPE, 274d814f301SCyrill Gorcunov P4_EVENT_RESOURCE_STALL, 275d814f301SCyrill Gorcunov P4_EVENT_WC_BUFFER, 276d814f301SCyrill Gorcunov P4_EVENT_B2B_CYCLES, 277d814f301SCyrill Gorcunov P4_EVENT_BNR, 278d814f301SCyrill Gorcunov P4_EVENT_SNOOP, 279d814f301SCyrill Gorcunov P4_EVENT_RESPONSE, 280d814f301SCyrill Gorcunov P4_EVENT_FRONT_END_EVENT, 281d814f301SCyrill Gorcunov P4_EVENT_EXECUTION_EVENT, 282d814f301SCyrill Gorcunov P4_EVENT_REPLAY_EVENT, 283d814f301SCyrill Gorcunov P4_EVENT_INSTR_RETIRED, 284d814f301SCyrill Gorcunov P4_EVENT_UOPS_RETIRED, 285d814f301SCyrill Gorcunov P4_EVENT_UOP_TYPE, 286d814f301SCyrill Gorcunov P4_EVENT_BRANCH_RETIRED, 287d814f301SCyrill Gorcunov P4_EVENT_MISPRED_BRANCH_RETIRED, 288d814f301SCyrill Gorcunov P4_EVENT_X87_ASSIST, 289d814f301SCyrill Gorcunov P4_EVENT_MACHINE_CLEAR, 290d814f301SCyrill Gorcunov P4_EVENT_INSTR_COMPLETED, 291d814f301SCyrill Gorcunov }; 292d814f301SCyrill Gorcunov 293d814f301SCyrill Gorcunov #define P4_OPCODE(event) event##_OPCODE 294d814f301SCyrill Gorcunov #define P4_OPCODE_ESEL(opcode) ((opcode & 0x00ff) >> 0) 295d814f301SCyrill Gorcunov #define P4_OPCODE_EVNT(opcode) ((opcode & 0xff00) >> 8) 296d814f301SCyrill Gorcunov #define P4_OPCODE_PACK(event, sel) (((event) << 8) | sel) 297d814f301SCyrill Gorcunov 298a072738eSCyrill Gorcunov /* 299a072738eSCyrill Gorcunov * Comments below the event represent ESCR restriction 300a072738eSCyrill Gorcunov * for this event and counter index per ESCR 301a072738eSCyrill Gorcunov * 302a072738eSCyrill Gorcunov * MSR_P4_IQ_ESCR0 and MSR_P4_IQ_ESCR1 are available only on early 303a072738eSCyrill Gorcunov * processor builds (family 0FH, models 01H-02H). These MSRs 304a072738eSCyrill Gorcunov * are not available on later versions, so that we don't use 305a072738eSCyrill Gorcunov * them completely 306a072738eSCyrill Gorcunov * 307a072738eSCyrill Gorcunov * Also note that CCCR1 do not have P4_CCCR_ENABLE bit properly 308a072738eSCyrill Gorcunov * working so that we should not use this CCCR and respective 309a072738eSCyrill Gorcunov * counter as result 310a072738eSCyrill Gorcunov */ 311d814f301SCyrill Gorcunov enum P4_EVENT_OPCODES { 312d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_TC_DELIVER_MODE) = P4_OPCODE_PACK(0x01, 0x01), 313a072738eSCyrill Gorcunov /* 314a072738eSCyrill Gorcunov * MSR_P4_TC_ESCR0: 4, 5 315a072738eSCyrill Gorcunov * MSR_P4_TC_ESCR1: 6, 7 316a072738eSCyrill Gorcunov */ 317a072738eSCyrill Gorcunov 318d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_BPU_FETCH_REQUEST) = P4_OPCODE_PACK(0x03, 0x00), 319a072738eSCyrill Gorcunov /* 320a072738eSCyrill Gorcunov * MSR_P4_BPU_ESCR0: 0, 1 321a072738eSCyrill Gorcunov * MSR_P4_BPU_ESCR1: 2, 3 322a072738eSCyrill Gorcunov */ 323a072738eSCyrill Gorcunov 324d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_ITLB_REFERENCE) = P4_OPCODE_PACK(0x18, 0x03), 325a072738eSCyrill Gorcunov /* 326a072738eSCyrill Gorcunov * MSR_P4_ITLB_ESCR0: 0, 1 327a072738eSCyrill Gorcunov * MSR_P4_ITLB_ESCR1: 2, 3 328a072738eSCyrill Gorcunov */ 329a072738eSCyrill Gorcunov 330d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_MEMORY_CANCEL) = P4_OPCODE_PACK(0x02, 0x05), 331a072738eSCyrill Gorcunov /* 332a072738eSCyrill Gorcunov * MSR_P4_DAC_ESCR0: 8, 9 333a072738eSCyrill Gorcunov * MSR_P4_DAC_ESCR1: 10, 11 334a072738eSCyrill Gorcunov */ 335a072738eSCyrill Gorcunov 336d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_MEMORY_COMPLETE) = P4_OPCODE_PACK(0x08, 0x02), 337a072738eSCyrill Gorcunov /* 338a072738eSCyrill Gorcunov * MSR_P4_SAAT_ESCR0: 8, 9 339a072738eSCyrill Gorcunov * MSR_P4_SAAT_ESCR1: 10, 11 340a072738eSCyrill Gorcunov */ 341a072738eSCyrill Gorcunov 342d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_LOAD_PORT_REPLAY) = P4_OPCODE_PACK(0x04, 0x02), 343a072738eSCyrill Gorcunov /* 344a072738eSCyrill Gorcunov * MSR_P4_SAAT_ESCR0: 8, 9 345a072738eSCyrill Gorcunov * MSR_P4_SAAT_ESCR1: 10, 11 346a072738eSCyrill Gorcunov */ 347a072738eSCyrill Gorcunov 348d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_STORE_PORT_REPLAY) = P4_OPCODE_PACK(0x05, 0x02), 349a072738eSCyrill Gorcunov /* 350a072738eSCyrill Gorcunov * MSR_P4_SAAT_ESCR0: 8, 9 351a072738eSCyrill Gorcunov * MSR_P4_SAAT_ESCR1: 10, 11 352a072738eSCyrill Gorcunov */ 353a072738eSCyrill Gorcunov 354d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_MOB_LOAD_REPLAY) = P4_OPCODE_PACK(0x03, 0x02), 355a072738eSCyrill Gorcunov /* 356a072738eSCyrill Gorcunov * MSR_P4_MOB_ESCR0: 0, 1 357a072738eSCyrill Gorcunov * MSR_P4_MOB_ESCR1: 2, 3 358a072738eSCyrill Gorcunov */ 359a072738eSCyrill Gorcunov 360d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_PAGE_WALK_TYPE) = P4_OPCODE_PACK(0x01, 0x04), 361a072738eSCyrill Gorcunov /* 362a072738eSCyrill Gorcunov * MSR_P4_PMH_ESCR0: 0, 1 363a072738eSCyrill Gorcunov * MSR_P4_PMH_ESCR1: 2, 3 364a072738eSCyrill Gorcunov */ 365a072738eSCyrill Gorcunov 366d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_BSQ_CACHE_REFERENCE) = P4_OPCODE_PACK(0x0c, 0x07), 367a072738eSCyrill Gorcunov /* 368a072738eSCyrill Gorcunov * MSR_P4_BSU_ESCR0: 0, 1 369a072738eSCyrill Gorcunov * MSR_P4_BSU_ESCR1: 2, 3 370a072738eSCyrill Gorcunov */ 371a072738eSCyrill Gorcunov 372d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_IOQ_ALLOCATION) = P4_OPCODE_PACK(0x03, 0x06), 373a072738eSCyrill Gorcunov /* 374a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR0: 0, 1 375a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR1: 2, 3 376a072738eSCyrill Gorcunov */ 377a072738eSCyrill Gorcunov 378d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_IOQ_ACTIVE_ENTRIES) = P4_OPCODE_PACK(0x1a, 0x06), 379a072738eSCyrill Gorcunov /* 380a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR1: 2, 3 381a072738eSCyrill Gorcunov */ 382a072738eSCyrill Gorcunov 383d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_FSB_DATA_ACTIVITY) = P4_OPCODE_PACK(0x17, 0x06), 384a072738eSCyrill Gorcunov /* 385a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR0: 0, 1 386a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR1: 2, 3 387a072738eSCyrill Gorcunov */ 388a072738eSCyrill Gorcunov 389d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_BSQ_ALLOCATION) = P4_OPCODE_PACK(0x05, 0x07), 390a072738eSCyrill Gorcunov /* 391a072738eSCyrill Gorcunov * MSR_P4_BSU_ESCR0: 0, 1 392a072738eSCyrill Gorcunov */ 393a072738eSCyrill Gorcunov 394d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_BSQ_ACTIVE_ENTRIES) = P4_OPCODE_PACK(0x06, 0x07), 395a072738eSCyrill Gorcunov /* 3968ea7f544SLin Ming * NOTE: no ESCR name in docs, it's guessed 397a072738eSCyrill Gorcunov * MSR_P4_BSU_ESCR1: 2, 3 398a072738eSCyrill Gorcunov */ 399a072738eSCyrill Gorcunov 400d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_SSE_INPUT_ASSIST) = P4_OPCODE_PACK(0x34, 0x01), 401a072738eSCyrill Gorcunov /* 402e4495262SCyrill Gorcunov * MSR_P4_FIRM_ESCR0: 8, 9 403e4495262SCyrill Gorcunov * MSR_P4_FIRM_ESCR1: 10, 11 404a072738eSCyrill Gorcunov */ 405a072738eSCyrill Gorcunov 406d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_PACKED_SP_UOP) = P4_OPCODE_PACK(0x08, 0x01), 407a072738eSCyrill Gorcunov /* 408a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR0: 8, 9 409a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR1: 10, 11 410a072738eSCyrill Gorcunov */ 411a072738eSCyrill Gorcunov 412d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_PACKED_DP_UOP) = P4_OPCODE_PACK(0x0c, 0x01), 413a072738eSCyrill Gorcunov /* 414a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR0: 8, 9 415a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR1: 10, 11 416a072738eSCyrill Gorcunov */ 417a072738eSCyrill Gorcunov 418d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_SCALAR_SP_UOP) = P4_OPCODE_PACK(0x0a, 0x01), 419a072738eSCyrill Gorcunov /* 420a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR0: 8, 9 421a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR1: 10, 11 422a072738eSCyrill Gorcunov */ 423a072738eSCyrill Gorcunov 424d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_SCALAR_DP_UOP) = P4_OPCODE_PACK(0x0e, 0x01), 425a072738eSCyrill Gorcunov /* 426a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR0: 8, 9 427a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR1: 10, 11 428a072738eSCyrill Gorcunov */ 429a072738eSCyrill Gorcunov 430d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_64BIT_MMX_UOP) = P4_OPCODE_PACK(0x02, 0x01), 431a072738eSCyrill Gorcunov /* 432a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR0: 8, 9 433a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR1: 10, 11 434a072738eSCyrill Gorcunov */ 435a072738eSCyrill Gorcunov 436d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_128BIT_MMX_UOP) = P4_OPCODE_PACK(0x1a, 0x01), 437a072738eSCyrill Gorcunov /* 438a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR0: 8, 9 439a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR1: 10, 11 440a072738eSCyrill Gorcunov */ 441a072738eSCyrill Gorcunov 442d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_X87_FP_UOP) = P4_OPCODE_PACK(0x04, 0x01), 443a072738eSCyrill Gorcunov /* 444a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR0: 8, 9 445a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR1: 10, 11 446a072738eSCyrill Gorcunov */ 447a072738eSCyrill Gorcunov 448d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_TC_MISC) = P4_OPCODE_PACK(0x06, 0x01), 449a072738eSCyrill Gorcunov /* 450a072738eSCyrill Gorcunov * MSR_P4_TC_ESCR0: 4, 5 451a072738eSCyrill Gorcunov * MSR_P4_TC_ESCR1: 6, 7 452a072738eSCyrill Gorcunov */ 453a072738eSCyrill Gorcunov 454d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_GLOBAL_POWER_EVENTS) = P4_OPCODE_PACK(0x13, 0x06), 455a072738eSCyrill Gorcunov /* 456a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR0: 0, 1 457a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR1: 2, 3 458a072738eSCyrill Gorcunov */ 459a072738eSCyrill Gorcunov 460d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_TC_MS_XFER) = P4_OPCODE_PACK(0x05, 0x00), 461a072738eSCyrill Gorcunov /* 462a072738eSCyrill Gorcunov * MSR_P4_MS_ESCR0: 4, 5 463a072738eSCyrill Gorcunov * MSR_P4_MS_ESCR1: 6, 7 464a072738eSCyrill Gorcunov */ 465a072738eSCyrill Gorcunov 466d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_UOP_QUEUE_WRITES) = P4_OPCODE_PACK(0x09, 0x00), 467a072738eSCyrill Gorcunov /* 468a072738eSCyrill Gorcunov * MSR_P4_MS_ESCR0: 4, 5 469a072738eSCyrill Gorcunov * MSR_P4_MS_ESCR1: 6, 7 470a072738eSCyrill Gorcunov */ 471a072738eSCyrill Gorcunov 472d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE) = P4_OPCODE_PACK(0x05, 0x02), 473a072738eSCyrill Gorcunov /* 474a072738eSCyrill Gorcunov * MSR_P4_TBPU_ESCR0: 4, 5 4759c8c6badSCyrill Gorcunov * MSR_P4_TBPU_ESCR1: 6, 7 476a072738eSCyrill Gorcunov */ 477a072738eSCyrill Gorcunov 478d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_RETIRED_BRANCH_TYPE) = P4_OPCODE_PACK(0x04, 0x02), 479a072738eSCyrill Gorcunov /* 480a072738eSCyrill Gorcunov * MSR_P4_TBPU_ESCR0: 4, 5 4819c8c6badSCyrill Gorcunov * MSR_P4_TBPU_ESCR1: 6, 7 482a072738eSCyrill Gorcunov */ 483a072738eSCyrill Gorcunov 484d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_RESOURCE_STALL) = P4_OPCODE_PACK(0x01, 0x01), 485a072738eSCyrill Gorcunov /* 486a072738eSCyrill Gorcunov * MSR_P4_ALF_ESCR0: 12, 13, 16 487a072738eSCyrill Gorcunov * MSR_P4_ALF_ESCR1: 14, 15, 17 488a072738eSCyrill Gorcunov */ 489a072738eSCyrill Gorcunov 490d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_WC_BUFFER) = P4_OPCODE_PACK(0x05, 0x05), 491a072738eSCyrill Gorcunov /* 492a072738eSCyrill Gorcunov * MSR_P4_DAC_ESCR0: 8, 9 493a072738eSCyrill Gorcunov * MSR_P4_DAC_ESCR1: 10, 11 494a072738eSCyrill Gorcunov */ 495a072738eSCyrill Gorcunov 496d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_B2B_CYCLES) = P4_OPCODE_PACK(0x16, 0x03), 497a072738eSCyrill Gorcunov /* 498a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR0: 0, 1 499a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR1: 2, 3 500a072738eSCyrill Gorcunov */ 501a072738eSCyrill Gorcunov 502d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_BNR) = P4_OPCODE_PACK(0x08, 0x03), 503a072738eSCyrill Gorcunov /* 504a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR0: 0, 1 505a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR1: 2, 3 506a072738eSCyrill Gorcunov */ 507a072738eSCyrill Gorcunov 508d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_SNOOP) = P4_OPCODE_PACK(0x06, 0x03), 509a072738eSCyrill Gorcunov /* 510a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR0: 0, 1 511a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR1: 2, 3 512a072738eSCyrill Gorcunov */ 513a072738eSCyrill Gorcunov 514d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_RESPONSE) = P4_OPCODE_PACK(0x04, 0x03), 515a072738eSCyrill Gorcunov /* 516a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR0: 0, 1 517a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR1: 2, 3 518a072738eSCyrill Gorcunov */ 519a072738eSCyrill Gorcunov 520d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_FRONT_END_EVENT) = P4_OPCODE_PACK(0x08, 0x05), 521a072738eSCyrill Gorcunov /* 522a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR2: 12, 13, 16 523a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR3: 14, 15, 17 524a072738eSCyrill Gorcunov */ 525a072738eSCyrill Gorcunov 526d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_EXECUTION_EVENT) = P4_OPCODE_PACK(0x0c, 0x05), 527a072738eSCyrill Gorcunov /* 528a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR2: 12, 13, 16 529a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR3: 14, 15, 17 530a072738eSCyrill Gorcunov */ 531a072738eSCyrill Gorcunov 532d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_REPLAY_EVENT) = P4_OPCODE_PACK(0x09, 0x05), 533a072738eSCyrill Gorcunov /* 534a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR2: 12, 13, 16 535a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR3: 14, 15, 17 536a072738eSCyrill Gorcunov */ 537a072738eSCyrill Gorcunov 538d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_INSTR_RETIRED) = P4_OPCODE_PACK(0x02, 0x04), 539a072738eSCyrill Gorcunov /* 540e4495262SCyrill Gorcunov * MSR_P4_CRU_ESCR0: 12, 13, 16 541e4495262SCyrill Gorcunov * MSR_P4_CRU_ESCR1: 14, 15, 17 542a072738eSCyrill Gorcunov */ 543a072738eSCyrill Gorcunov 544d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_UOPS_RETIRED) = P4_OPCODE_PACK(0x01, 0x04), 545a072738eSCyrill Gorcunov /* 5468ea7f544SLin Ming * MSR_P4_CRU_ESCR0: 12, 13, 16 5478ea7f544SLin Ming * MSR_P4_CRU_ESCR1: 14, 15, 17 548a072738eSCyrill Gorcunov */ 549a072738eSCyrill Gorcunov 550d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_UOP_TYPE) = P4_OPCODE_PACK(0x02, 0x02), 551a072738eSCyrill Gorcunov /* 552a072738eSCyrill Gorcunov * MSR_P4_RAT_ESCR0: 12, 13, 16 553a072738eSCyrill Gorcunov * MSR_P4_RAT_ESCR1: 14, 15, 17 554a072738eSCyrill Gorcunov */ 555a072738eSCyrill Gorcunov 556d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_BRANCH_RETIRED) = P4_OPCODE_PACK(0x06, 0x05), 557a072738eSCyrill Gorcunov /* 558a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR2: 12, 13, 16 559a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR3: 14, 15, 17 560a072738eSCyrill Gorcunov */ 561a072738eSCyrill Gorcunov 562d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_MISPRED_BRANCH_RETIRED) = P4_OPCODE_PACK(0x03, 0x04), 563a072738eSCyrill Gorcunov /* 564a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR0: 12, 13, 16 565a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR1: 14, 15, 17 566a072738eSCyrill Gorcunov */ 567a072738eSCyrill Gorcunov 568d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_X87_ASSIST) = P4_OPCODE_PACK(0x03, 0x05), 569a072738eSCyrill Gorcunov /* 570a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR2: 12, 13, 16 571a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR3: 14, 15, 17 572a072738eSCyrill Gorcunov */ 573a072738eSCyrill Gorcunov 574d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_MACHINE_CLEAR) = P4_OPCODE_PACK(0x02, 0x05), 575a072738eSCyrill Gorcunov /* 576a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR2: 12, 13, 16 577a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR3: 14, 15, 17 578a072738eSCyrill Gorcunov */ 579a072738eSCyrill Gorcunov 580d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_INSTR_COMPLETED) = P4_OPCODE_PACK(0x07, 0x04), 581a072738eSCyrill Gorcunov /* 582a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR0: 12, 13, 16 583a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR1: 14, 15, 17 584a072738eSCyrill Gorcunov */ 585a072738eSCyrill Gorcunov }; 586a072738eSCyrill Gorcunov 587d814f301SCyrill Gorcunov /* 588d814f301SCyrill Gorcunov * a caller should use P4_ESCR_EMASK_NAME helper to 589d814f301SCyrill Gorcunov * pick the EventMask needed, for example 590d814f301SCyrill Gorcunov * 59139ef13a4SCyrill Gorcunov * P4_ESCR_EMASK_BIT(P4_EVENT_TC_DELIVER_MODE, DD) 592d814f301SCyrill Gorcunov */ 593d814f301SCyrill Gorcunov enum P4_ESCR_EMASKS { 594d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, DD, 0), 595d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, DB, 1), 596d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, DI, 2), 597d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, BD, 3), 598d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, BB, 4), 599d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, BI, 5), 600d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, ID, 6), 601d814f301SCyrill Gorcunov 602d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BPU_FETCH_REQUEST, TCMISS, 0), 603d814f301SCyrill Gorcunov 604d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_ITLB_REFERENCE, HIT, 0), 605d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_ITLB_REFERENCE, MISS, 1), 606d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_ITLB_REFERENCE, HIT_UK, 2), 607d814f301SCyrill Gorcunov 608d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_MEMORY_CANCEL, ST_RB_FULL, 2), 609d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_MEMORY_CANCEL, 64K_CONF, 3), 610d814f301SCyrill Gorcunov 611d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_MEMORY_COMPLETE, LSC, 0), 612d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_MEMORY_COMPLETE, SSC, 1), 613d814f301SCyrill Gorcunov 614d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_LOAD_PORT_REPLAY, SPLIT_LD, 1), 615d814f301SCyrill Gorcunov 616d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_STORE_PORT_REPLAY, SPLIT_ST, 1), 617d814f301SCyrill Gorcunov 618d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_MOB_LOAD_REPLAY, NO_STA, 1), 619d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_MOB_LOAD_REPLAY, NO_STD, 3), 620d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_MOB_LOAD_REPLAY, PARTIAL_DATA, 4), 621d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_MOB_LOAD_REPLAY, UNALGN_ADDR, 5), 622d814f301SCyrill Gorcunov 623d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_PAGE_WALK_TYPE, DTMISS, 0), 624d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_PAGE_WALK_TYPE, ITMISS, 1), 625d814f301SCyrill Gorcunov 626d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_HITS, 0), 627d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_HITE, 1), 628d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_HITM, 2), 629d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_HITS, 3), 630d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_HITE, 4), 631d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_HITM, 5), 632d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_MISS, 8), 633d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_MISS, 9), 634d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, WR_2ndL_MISS, 10), 635d814f301SCyrill Gorcunov 636d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, DEFAULT, 0), 637d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, ALL_READ, 5), 638d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, ALL_WRITE, 6), 639d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, MEM_UC, 7), 640d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, MEM_WC, 8), 641d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, MEM_WT, 9), 642d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, MEM_WP, 10), 643d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, MEM_WB, 11), 644d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, OWN, 13), 645d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, OTHER, 14), 646d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, PREFETCH, 15), 647d814f301SCyrill Gorcunov 648d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, DEFAULT, 0), 649d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, ALL_READ, 5), 650d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, ALL_WRITE, 6), 651d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, MEM_UC, 7), 652d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, MEM_WC, 8), 653d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, MEM_WT, 9), 654d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, MEM_WP, 10), 655d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, MEM_WB, 11), 656d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, OWN, 13), 657d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, OTHER, 14), 658d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, PREFETCH, 15), 659d814f301SCyrill Gorcunov 660d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_FSB_DATA_ACTIVITY, DRDY_DRV, 0), 661d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_FSB_DATA_ACTIVITY, DRDY_OWN, 1), 662d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_FSB_DATA_ACTIVITY, DRDY_OTHER, 2), 663d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_FSB_DATA_ACTIVITY, DBSY_DRV, 3), 664d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_FSB_DATA_ACTIVITY, DBSY_OWN, 4), 665d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_FSB_DATA_ACTIVITY, DBSY_OTHER, 5), 666d814f301SCyrill Gorcunov 667d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_TYPE0, 0), 668d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_TYPE1, 1), 669d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_LEN0, 2), 670d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_LEN1, 3), 671d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_IO_TYPE, 5), 672d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_LOCK_TYPE, 6), 673d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_CACHE_TYPE, 7), 674d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_SPLIT_TYPE, 8), 675d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_DEM_TYPE, 9), 676d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_ORD_TYPE, 10), 677d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, MEM_TYPE0, 11), 678d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, MEM_TYPE1, 12), 679d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, MEM_TYPE2, 13), 680d814f301SCyrill Gorcunov 681d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_TYPE0, 0), 682d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_TYPE1, 1), 683d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_LEN0, 2), 684d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_LEN1, 3), 685d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_IO_TYPE, 5), 686d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_LOCK_TYPE, 6), 687d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_CACHE_TYPE, 7), 688d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_SPLIT_TYPE, 8), 689d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_DEM_TYPE, 9), 690d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_ORD_TYPE, 10), 691d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, MEM_TYPE0, 11), 692d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, MEM_TYPE1, 12), 693d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, MEM_TYPE2, 13), 694d814f301SCyrill Gorcunov 695d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_SSE_INPUT_ASSIST, ALL, 15), 696d814f301SCyrill Gorcunov 697d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_PACKED_SP_UOP, ALL, 15), 698d814f301SCyrill Gorcunov 699d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_PACKED_DP_UOP, ALL, 15), 700d814f301SCyrill Gorcunov 701d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_SCALAR_SP_UOP, ALL, 15), 702d814f301SCyrill Gorcunov 703d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_SCALAR_DP_UOP, ALL, 15), 704d814f301SCyrill Gorcunov 705d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_64BIT_MMX_UOP, ALL, 15), 706d814f301SCyrill Gorcunov 707d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_128BIT_MMX_UOP, ALL, 15), 708d814f301SCyrill Gorcunov 709d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_X87_FP_UOP, ALL, 15), 710d814f301SCyrill Gorcunov 711d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_TC_MISC, FLUSH, 4), 712d814f301SCyrill Gorcunov 713d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_GLOBAL_POWER_EVENTS, RUNNING, 0), 714d814f301SCyrill Gorcunov 715d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_TC_MS_XFER, CISC, 0), 716d814f301SCyrill Gorcunov 717d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_UOP_QUEUE_WRITES, FROM_TC_BUILD, 0), 718d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_UOP_QUEUE_WRITES, FROM_TC_DELIVER, 1), 719d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_UOP_QUEUE_WRITES, FROM_ROM, 2), 720d814f301SCyrill Gorcunov 721d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE, CONDITIONAL, 1), 722d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE, CALL, 2), 723d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE, RETURN, 3), 724d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE, INDIRECT, 4), 725d814f301SCyrill Gorcunov 726d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_BRANCH_TYPE, CONDITIONAL, 1), 727d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_BRANCH_TYPE, CALL, 2), 728d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_BRANCH_TYPE, RETURN, 3), 729d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_BRANCH_TYPE, INDIRECT, 4), 730d814f301SCyrill Gorcunov 731d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_RESOURCE_STALL, SBFULL, 5), 732d814f301SCyrill Gorcunov 733d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_WC_BUFFER, WCB_EVICTS, 0), 734d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_WC_BUFFER, WCB_FULL_EVICTS, 1), 735d814f301SCyrill Gorcunov 736d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_FRONT_END_EVENT, NBOGUS, 0), 737d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_FRONT_END_EVENT, BOGUS, 1), 738d814f301SCyrill Gorcunov 739d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, NBOGUS0, 0), 740d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, NBOGUS1, 1), 741d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, NBOGUS2, 2), 742d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, NBOGUS3, 3), 743d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, BOGUS0, 4), 744d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, BOGUS1, 5), 745d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, BOGUS2, 6), 746d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, BOGUS3, 7), 747d814f301SCyrill Gorcunov 748d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_REPLAY_EVENT, NBOGUS, 0), 749d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_REPLAY_EVENT, BOGUS, 1), 750d814f301SCyrill Gorcunov 751d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_INSTR_RETIRED, NBOGUSNTAG, 0), 752d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_INSTR_RETIRED, NBOGUSTAG, 1), 753d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_INSTR_RETIRED, BOGUSNTAG, 2), 754d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_INSTR_RETIRED, BOGUSTAG, 3), 755d814f301SCyrill Gorcunov 756d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_UOPS_RETIRED, NBOGUS, 0), 757d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_UOPS_RETIRED, BOGUS, 1), 758d814f301SCyrill Gorcunov 759d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_UOP_TYPE, TAGLOADS, 1), 760d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_UOP_TYPE, TAGSTORES, 2), 761d814f301SCyrill Gorcunov 762d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BRANCH_RETIRED, MMNP, 0), 763d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BRANCH_RETIRED, MMNM, 1), 764d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BRANCH_RETIRED, MMTP, 2), 765d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BRANCH_RETIRED, MMTM, 3), 766d814f301SCyrill Gorcunov 767d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_MISPRED_BRANCH_RETIRED, NBOGUS, 0), 768d814f301SCyrill Gorcunov 769d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_X87_ASSIST, FPSU, 0), 770d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_X87_ASSIST, FPSO, 1), 771d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_X87_ASSIST, POAO, 2), 772d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_X87_ASSIST, POAU, 3), 773d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_X87_ASSIST, PREA, 4), 774d814f301SCyrill Gorcunov 775d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_MACHINE_CLEAR, CLEAR, 0), 776d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_MACHINE_CLEAR, MOCLEAR, 1), 777d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_MACHINE_CLEAR, SMCLEAR, 2), 778d814f301SCyrill Gorcunov 779d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_INSTR_COMPLETED, NBOGUS, 0), 780d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_INSTR_COMPLETED, BOGUS, 1), 781d814f301SCyrill Gorcunov }; 782d814f301SCyrill Gorcunov 78339ef13a4SCyrill Gorcunov /* 78439ef13a4SCyrill Gorcunov * Note we have UOP and PEBS bits reserved for now 78539ef13a4SCyrill Gorcunov * just in case if we will need them once 78639ef13a4SCyrill Gorcunov */ 78739ef13a4SCyrill Gorcunov #define P4_PEBS_CONFIG_ENABLE (1 << 7) 78839ef13a4SCyrill Gorcunov #define P4_PEBS_CONFIG_UOP_TAG (1 << 8) 78939ef13a4SCyrill Gorcunov #define P4_PEBS_CONFIG_METRIC_MASK 0x3f 79039ef13a4SCyrill Gorcunov #define P4_PEBS_CONFIG_MASK 0xff 79139ef13a4SCyrill Gorcunov 79239ef13a4SCyrill Gorcunov /* 79339ef13a4SCyrill Gorcunov * mem: Only counters MSR_IQ_COUNTER4 (16) and 79439ef13a4SCyrill Gorcunov * MSR_IQ_COUNTER5 (17) are allowed for PEBS sampling 79539ef13a4SCyrill Gorcunov */ 796d814f301SCyrill Gorcunov #define P4_PEBS_ENABLE 0x02000000U 79739ef13a4SCyrill Gorcunov #define P4_PEBS_ENABLE_UOP_TAG 0x01000000U 798d814f301SCyrill Gorcunov 79939ef13a4SCyrill Gorcunov #define p4_config_unpack_metric(v) (((u64)(v)) & P4_PEBS_CONFIG_METRIC_MASK) 80039ef13a4SCyrill Gorcunov #define p4_config_unpack_pebs(v) (((u64)(v)) & P4_PEBS_CONFIG_MASK) 801d814f301SCyrill Gorcunov 80239ef13a4SCyrill Gorcunov #define p4_config_pebs_has(v, mask) (p4_config_unpack_pebs(v) & (mask)) 803d814f301SCyrill Gorcunov 80439ef13a4SCyrill Gorcunov enum P4_PEBS_METRIC { 80539ef13a4SCyrill Gorcunov P4_PEBS_METRIC__none, 806d814f301SCyrill Gorcunov 80739ef13a4SCyrill Gorcunov P4_PEBS_METRIC__1stl_cache_load_miss_retired, 80839ef13a4SCyrill Gorcunov P4_PEBS_METRIC__2ndl_cache_load_miss_retired, 80939ef13a4SCyrill Gorcunov P4_PEBS_METRIC__dtlb_load_miss_retired, 81039ef13a4SCyrill Gorcunov P4_PEBS_METRIC__dtlb_store_miss_retired, 81139ef13a4SCyrill Gorcunov P4_PEBS_METRIC__dtlb_all_miss_retired, 81239ef13a4SCyrill Gorcunov P4_PEBS_METRIC__tagged_mispred_branch, 81339ef13a4SCyrill Gorcunov P4_PEBS_METRIC__mob_load_replay_retired, 81439ef13a4SCyrill Gorcunov P4_PEBS_METRIC__split_load_retired, 81539ef13a4SCyrill Gorcunov P4_PEBS_METRIC__split_store_retired, 816d814f301SCyrill Gorcunov 81739ef13a4SCyrill Gorcunov P4_PEBS_METRIC__max 818cb7d6b50SLin Ming }; 819cb7d6b50SLin Ming 820af86da53SCyrill Gorcunov /* 821af86da53SCyrill Gorcunov * Notes on internal configuration of ESCR+CCCR tuples 822af86da53SCyrill Gorcunov * 823af86da53SCyrill Gorcunov * Since P4 has quite the different architecture of 824af86da53SCyrill Gorcunov * performance registers in compare with "architectural" 825af86da53SCyrill Gorcunov * once and we have on 64 bits to keep configuration 826af86da53SCyrill Gorcunov * of performance event, the following trick is used. 827af86da53SCyrill Gorcunov * 828af86da53SCyrill Gorcunov * 1) Since both ESCR and CCCR registers have only low 829af86da53SCyrill Gorcunov * 32 bits valuable, we pack them into a single 64 bit 830af86da53SCyrill Gorcunov * configuration. Low 32 bits of such config correspond 831af86da53SCyrill Gorcunov * to low 32 bits of CCCR register and high 32 bits 832af86da53SCyrill Gorcunov * correspond to low 32 bits of ESCR register. 833af86da53SCyrill Gorcunov * 834af86da53SCyrill Gorcunov * 2) The meaning of every bit of such config field can 835af86da53SCyrill Gorcunov * be found in Intel SDM but it should be noted that 836af86da53SCyrill Gorcunov * we "borrow" some reserved bits for own usage and 837af86da53SCyrill Gorcunov * clean them or set to a proper value when we do 838af86da53SCyrill Gorcunov * a real write to hardware registers. 839af86da53SCyrill Gorcunov * 840af86da53SCyrill Gorcunov * 3) The format of bits of config is the following 841af86da53SCyrill Gorcunov * and should be either 0 or set to some predefined 842af86da53SCyrill Gorcunov * values: 843af86da53SCyrill Gorcunov * 844af86da53SCyrill Gorcunov * Low 32 bits 845af86da53SCyrill Gorcunov * ----------- 846af86da53SCyrill Gorcunov * 0-6: P4_PEBS_METRIC enum 847af86da53SCyrill Gorcunov * 7-11: reserved 848af86da53SCyrill Gorcunov * 12: reserved (Enable) 849af86da53SCyrill Gorcunov * 13-15: reserved (ESCR select) 850af86da53SCyrill Gorcunov * 16-17: Active Thread 851af86da53SCyrill Gorcunov * 18: Compare 852af86da53SCyrill Gorcunov * 19: Complement 853af86da53SCyrill Gorcunov * 20-23: Threshold 854af86da53SCyrill Gorcunov * 24: Edge 855af86da53SCyrill Gorcunov * 25: reserved (FORCE_OVF) 856af86da53SCyrill Gorcunov * 26: reserved (OVF_PMI_T0) 857af86da53SCyrill Gorcunov * 27: reserved (OVF_PMI_T1) 858af86da53SCyrill Gorcunov * 28-29: reserved 859af86da53SCyrill Gorcunov * 30: reserved (Cascade) 860af86da53SCyrill Gorcunov * 31: reserved (OVF) 861af86da53SCyrill Gorcunov * 862af86da53SCyrill Gorcunov * High 32 bits 863af86da53SCyrill Gorcunov * ------------ 864af86da53SCyrill Gorcunov * 0: reserved (T1_USR) 865af86da53SCyrill Gorcunov * 1: reserved (T1_OS) 866af86da53SCyrill Gorcunov * 2: reserved (T0_USR) 867af86da53SCyrill Gorcunov * 3: reserved (T0_OS) 868af86da53SCyrill Gorcunov * 4: Tag Enable 869af86da53SCyrill Gorcunov * 5-8: Tag Value 870af86da53SCyrill Gorcunov * 9-24: Event Mask (may use P4_ESCR_EMASK_BIT helper) 871af86da53SCyrill Gorcunov * 25-30: enum P4_EVENTS 872af86da53SCyrill Gorcunov * 31: reserved (HT thread) 873af86da53SCyrill Gorcunov */ 874af86da53SCyrill Gorcunov 875a072738eSCyrill Gorcunov #endif /* PERF_EVENT_P4_H */ 87639ef13a4SCyrill Gorcunov 877