1a072738eSCyrill Gorcunov /* 2a072738eSCyrill Gorcunov * Netburst Perfomance Events (P4, old Xeon) 3a072738eSCyrill Gorcunov */ 4a072738eSCyrill Gorcunov 5a072738eSCyrill Gorcunov #ifndef PERF_EVENT_P4_H 6a072738eSCyrill Gorcunov #define PERF_EVENT_P4_H 7a072738eSCyrill Gorcunov 8a072738eSCyrill Gorcunov #include <linux/cpu.h> 9a072738eSCyrill Gorcunov #include <linux/bitops.h> 10a072738eSCyrill Gorcunov 11a072738eSCyrill Gorcunov /* 12a072738eSCyrill Gorcunov * NetBurst has perfomance MSRs shared between 13a072738eSCyrill Gorcunov * threads if HT is turned on, ie for both logical 14a072738eSCyrill Gorcunov * processors (mem: in turn in Atom with HT support 15a072738eSCyrill Gorcunov * perf-MSRs are not shared and every thread has its 16a072738eSCyrill Gorcunov * own perf-MSRs set) 17a072738eSCyrill Gorcunov */ 18a072738eSCyrill Gorcunov #define ARCH_P4_TOTAL_ESCR (46) 19a072738eSCyrill Gorcunov #define ARCH_P4_RESERVED_ESCR (2) /* IQ_ESCR(0,1) not always present */ 20a072738eSCyrill Gorcunov #define ARCH_P4_MAX_ESCR (ARCH_P4_TOTAL_ESCR - ARCH_P4_RESERVED_ESCR) 21a072738eSCyrill Gorcunov #define ARCH_P4_MAX_CCCR (18) 22a072738eSCyrill Gorcunov #define ARCH_P4_MAX_COUNTER (ARCH_P4_MAX_CCCR / 2) 23a072738eSCyrill Gorcunov 24*d814f301SCyrill Gorcunov #define P4_ESCR_EVENT_MASK 0x7e000000U 25*d814f301SCyrill Gorcunov #define P4_ESCR_EVENT_SHIFT 25 26*d814f301SCyrill Gorcunov #define P4_ESCR_EVENTMASK_MASK 0x01fffe00U 27*d814f301SCyrill Gorcunov #define P4_ESCR_EVENTMASK_SHIFT 9 28*d814f301SCyrill Gorcunov #define P4_ESCR_TAG_MASK 0x000001e0U 29*d814f301SCyrill Gorcunov #define P4_ESCR_TAG_SHIFT 5 30*d814f301SCyrill Gorcunov #define P4_ESCR_TAG_ENABLE 0x00000010U 31*d814f301SCyrill Gorcunov #define P4_ESCR_T0_OS 0x00000008U 32*d814f301SCyrill Gorcunov #define P4_ESCR_T0_USR 0x00000004U 33*d814f301SCyrill Gorcunov #define P4_ESCR_T1_OS 0x00000002U 34*d814f301SCyrill Gorcunov #define P4_ESCR_T1_USR 0x00000001U 35*d814f301SCyrill Gorcunov 36*d814f301SCyrill Gorcunov #define P4_ESCR_EVENT(v) ((v) << P4_ESCR_EVENT_SHIFT) 37*d814f301SCyrill Gorcunov #define P4_ESCR_EMASK(v) ((v) << P4_ESCR_EVENTMASK_SHIFT) 38*d814f301SCyrill Gorcunov #define P4_ESCR_TAG(v) ((v) << P4_ESCR_TAG_SHIFT) 39a072738eSCyrill Gorcunov 40a072738eSCyrill Gorcunov /* Non HT mask */ 41*d814f301SCyrill Gorcunov #define P4_ESCR_MASK \ 42*d814f301SCyrill Gorcunov (P4_ESCR_EVENT_MASK | \ 43*d814f301SCyrill Gorcunov P4_ESCR_EVENTMASK_MASK | \ 44*d814f301SCyrill Gorcunov P4_ESCR_TAG_MASK | \ 45*d814f301SCyrill Gorcunov P4_ESCR_TAG_ENABLE | \ 46*d814f301SCyrill Gorcunov P4_ESCR_T0_OS | \ 47*d814f301SCyrill Gorcunov P4_ESCR_T0_USR) 48a072738eSCyrill Gorcunov 49a072738eSCyrill Gorcunov /* HT mask */ 50*d814f301SCyrill Gorcunov #define P4_ESCR_MASK_HT \ 51*d814f301SCyrill Gorcunov (P4_ESCR_MASK | P4_ESCR_T1_OS | P4_ESCR_T1_USR) 52a072738eSCyrill Gorcunov 53a072738eSCyrill Gorcunov #define P4_CCCR_OVF 0x80000000U 54a072738eSCyrill Gorcunov #define P4_CCCR_CASCADE 0x40000000U 55a072738eSCyrill Gorcunov #define P4_CCCR_OVF_PMI_T0 0x04000000U 56a072738eSCyrill Gorcunov #define P4_CCCR_OVF_PMI_T1 0x08000000U 57a072738eSCyrill Gorcunov #define P4_CCCR_FORCE_OVF 0x02000000U 58a072738eSCyrill Gorcunov #define P4_CCCR_EDGE 0x01000000U 59a072738eSCyrill Gorcunov #define P4_CCCR_THRESHOLD_MASK 0x00f00000U 60a072738eSCyrill Gorcunov #define P4_CCCR_THRESHOLD_SHIFT 20 61a072738eSCyrill Gorcunov #define P4_CCCR_COMPLEMENT 0x00080000U 62a072738eSCyrill Gorcunov #define P4_CCCR_COMPARE 0x00040000U 63a072738eSCyrill Gorcunov #define P4_CCCR_ESCR_SELECT_MASK 0x0000e000U 64a072738eSCyrill Gorcunov #define P4_CCCR_ESCR_SELECT_SHIFT 13 65a072738eSCyrill Gorcunov #define P4_CCCR_ENABLE 0x00001000U 66a072738eSCyrill Gorcunov #define P4_CCCR_THREAD_SINGLE 0x00010000U 67a072738eSCyrill Gorcunov #define P4_CCCR_THREAD_BOTH 0x00020000U 68a072738eSCyrill Gorcunov #define P4_CCCR_THREAD_ANY 0x00030000U 69f34edbc1SLin Ming #define P4_CCCR_RESERVED 0x00000fffU 70a072738eSCyrill Gorcunov 71*d814f301SCyrill Gorcunov #define P4_CCCR_THRESHOLD(v) ((v) << P4_CCCR_THRESHOLD_SHIFT) 72*d814f301SCyrill Gorcunov #define P4_CCCR_ESEL(v) ((v) << P4_CCCR_ESCR_SELECT_SHIFT) 73*d814f301SCyrill Gorcunov 74*d814f301SCyrill Gorcunov /* Custom bits in reerved CCCR area */ 75*d814f301SCyrill Gorcunov #define P4_CCCR_CACHE_OPS_MASK 0x0000003fU 76*d814f301SCyrill Gorcunov 77*d814f301SCyrill Gorcunov 78a072738eSCyrill Gorcunov /* Non HT mask */ 79a072738eSCyrill Gorcunov #define P4_CCCR_MASK \ 80a072738eSCyrill Gorcunov (P4_CCCR_OVF | \ 81a072738eSCyrill Gorcunov P4_CCCR_CASCADE | \ 82a072738eSCyrill Gorcunov P4_CCCR_OVF_PMI_T0 | \ 83a072738eSCyrill Gorcunov P4_CCCR_FORCE_OVF | \ 84a072738eSCyrill Gorcunov P4_CCCR_EDGE | \ 85a072738eSCyrill Gorcunov P4_CCCR_THRESHOLD_MASK | \ 86a072738eSCyrill Gorcunov P4_CCCR_COMPLEMENT | \ 87a072738eSCyrill Gorcunov P4_CCCR_COMPARE | \ 88a072738eSCyrill Gorcunov P4_CCCR_ESCR_SELECT_MASK | \ 89a072738eSCyrill Gorcunov P4_CCCR_ENABLE) 90a072738eSCyrill Gorcunov 91a072738eSCyrill Gorcunov /* HT mask */ 92*d814f301SCyrill Gorcunov #define P4_CCCR_MASK_HT (P4_CCCR_MASK | P4_CCCR_THREAD_ANY) 93a072738eSCyrill Gorcunov 94*d814f301SCyrill Gorcunov #define P4_GEN_ESCR_EMASK(class, name, bit) \ 95*d814f301SCyrill Gorcunov class##__##name = ((1 << bit) << P4_ESCR_EVENTMASK_SHIFT) 96*d814f301SCyrill Gorcunov #define P4_ESCR_EMASK_BIT(class, name) class##__##name 97a072738eSCyrill Gorcunov 98a072738eSCyrill Gorcunov /* 99a072738eSCyrill Gorcunov * config field is 64bit width and consists of 100a072738eSCyrill Gorcunov * HT << 63 | ESCR << 32 | CCCR 101a072738eSCyrill Gorcunov * where HT is HyperThreading bit (since ESCR 102a072738eSCyrill Gorcunov * has it reserved we may use it for own purpose) 103a072738eSCyrill Gorcunov * 104a072738eSCyrill Gorcunov * note that this is NOT the addresses of respective 105a072738eSCyrill Gorcunov * ESCR and CCCR but rather an only packed value should 106a072738eSCyrill Gorcunov * be unpacked and written to a proper addresses 107a072738eSCyrill Gorcunov * 108a072738eSCyrill Gorcunov * the base idea is to pack as much info as 109a072738eSCyrill Gorcunov * possible 110a072738eSCyrill Gorcunov */ 111a072738eSCyrill Gorcunov #define p4_config_pack_escr(v) (((u64)(v)) << 32) 112a072738eSCyrill Gorcunov #define p4_config_pack_cccr(v) (((u64)(v)) & 0xffffffffULL) 113a072738eSCyrill Gorcunov #define p4_config_unpack_escr(v) (((u64)(v)) >> 32) 114*d814f301SCyrill Gorcunov #define p4_config_unpack_cccr(v) (((u64)(v)) & 0xffffffffULL) 115a072738eSCyrill Gorcunov 116a072738eSCyrill Gorcunov #define p4_config_unpack_emask(v) \ 117a072738eSCyrill Gorcunov ({ \ 118a072738eSCyrill Gorcunov u32 t = p4_config_unpack_escr((v)); \ 119*d814f301SCyrill Gorcunov t = t & P4_ESCR_EVENTMASK_MASK; \ 120*d814f301SCyrill Gorcunov t = t >> P4_ESCR_EVENTMASK_SHIFT; \ 121a072738eSCyrill Gorcunov t; \ 122a072738eSCyrill Gorcunov }) 123a072738eSCyrill Gorcunov 124*d814f301SCyrill Gorcunov #define p4_config_unpack_event(v) \ 125*d814f301SCyrill Gorcunov ({ \ 126*d814f301SCyrill Gorcunov u32 t = p4_config_unpack_escr((v)); \ 127*d814f301SCyrill Gorcunov t = t & P4_ESCR_EVENT_MASK; \ 128*d814f301SCyrill Gorcunov t = t >> P4_ESCR_EVENT_SHIFT; \ 129*d814f301SCyrill Gorcunov t; \ 130*d814f301SCyrill Gorcunov }) 131*d814f301SCyrill Gorcunov 132*d814f301SCyrill Gorcunov #define p4_config_unpack_cache_event(v) (((u64)(v)) & P4_CCCR_CACHE_OPS_MASK) 133f34edbc1SLin Ming 134a072738eSCyrill Gorcunov #define P4_CONFIG_HT_SHIFT 63 135a072738eSCyrill Gorcunov #define P4_CONFIG_HT (1ULL << P4_CONFIG_HT_SHIFT) 136a072738eSCyrill Gorcunov 137a072738eSCyrill Gorcunov static inline bool p4_is_event_cascaded(u64 config) 138a072738eSCyrill Gorcunov { 139a072738eSCyrill Gorcunov u32 cccr = p4_config_unpack_cccr(config); 140a072738eSCyrill Gorcunov return !!(cccr & P4_CCCR_CASCADE); 141a072738eSCyrill Gorcunov } 142a072738eSCyrill Gorcunov 143a072738eSCyrill Gorcunov static inline int p4_ht_config_thread(u64 config) 144a072738eSCyrill Gorcunov { 145a072738eSCyrill Gorcunov return !!(config & P4_CONFIG_HT); 146a072738eSCyrill Gorcunov } 147a072738eSCyrill Gorcunov 148a072738eSCyrill Gorcunov static inline u64 p4_set_ht_bit(u64 config) 149a072738eSCyrill Gorcunov { 150a072738eSCyrill Gorcunov return config | P4_CONFIG_HT; 151a072738eSCyrill Gorcunov } 152a072738eSCyrill Gorcunov 153a072738eSCyrill Gorcunov static inline u64 p4_clear_ht_bit(u64 config) 154a072738eSCyrill Gorcunov { 155a072738eSCyrill Gorcunov return config & ~P4_CONFIG_HT; 156a072738eSCyrill Gorcunov } 157a072738eSCyrill Gorcunov 158a072738eSCyrill Gorcunov static inline int p4_ht_active(void) 159a072738eSCyrill Gorcunov { 160a072738eSCyrill Gorcunov #ifdef CONFIG_SMP 161a072738eSCyrill Gorcunov return smp_num_siblings > 1; 162a072738eSCyrill Gorcunov #endif 163a072738eSCyrill Gorcunov return 0; 164a072738eSCyrill Gorcunov } 165a072738eSCyrill Gorcunov 166a072738eSCyrill Gorcunov static inline int p4_ht_thread(int cpu) 167a072738eSCyrill Gorcunov { 168a072738eSCyrill Gorcunov #ifdef CONFIG_SMP 169a072738eSCyrill Gorcunov if (smp_num_siblings == 2) 170a072738eSCyrill Gorcunov return cpu != cpumask_first(__get_cpu_var(cpu_sibling_map)); 171a072738eSCyrill Gorcunov #endif 172a072738eSCyrill Gorcunov return 0; 173a072738eSCyrill Gorcunov } 174a072738eSCyrill Gorcunov 175a072738eSCyrill Gorcunov static inline int p4_should_swap_ts(u64 config, int cpu) 176a072738eSCyrill Gorcunov { 177a072738eSCyrill Gorcunov return p4_ht_config_thread(config) ^ p4_ht_thread(cpu); 178a072738eSCyrill Gorcunov } 179a072738eSCyrill Gorcunov 180a072738eSCyrill Gorcunov static inline u32 p4_default_cccr_conf(int cpu) 181a072738eSCyrill Gorcunov { 182a072738eSCyrill Gorcunov /* 183a072738eSCyrill Gorcunov * Note that P4_CCCR_THREAD_ANY is "required" on 184a072738eSCyrill Gorcunov * non-HT machines (on HT machines we count TS events 185a072738eSCyrill Gorcunov * regardless the state of second logical processor 186a072738eSCyrill Gorcunov */ 187a072738eSCyrill Gorcunov u32 cccr = P4_CCCR_THREAD_ANY; 188a072738eSCyrill Gorcunov 189a072738eSCyrill Gorcunov if (!p4_ht_thread(cpu)) 190a072738eSCyrill Gorcunov cccr |= P4_CCCR_OVF_PMI_T0; 191a072738eSCyrill Gorcunov else 192a072738eSCyrill Gorcunov cccr |= P4_CCCR_OVF_PMI_T1; 193a072738eSCyrill Gorcunov 194a072738eSCyrill Gorcunov return cccr; 195a072738eSCyrill Gorcunov } 196a072738eSCyrill Gorcunov 197a072738eSCyrill Gorcunov static inline u32 p4_default_escr_conf(int cpu, int exclude_os, int exclude_usr) 198a072738eSCyrill Gorcunov { 199a072738eSCyrill Gorcunov u32 escr = 0; 200a072738eSCyrill Gorcunov 201a072738eSCyrill Gorcunov if (!p4_ht_thread(cpu)) { 202a072738eSCyrill Gorcunov if (!exclude_os) 203*d814f301SCyrill Gorcunov escr |= P4_ESCR_T0_OS; 204a072738eSCyrill Gorcunov if (!exclude_usr) 205*d814f301SCyrill Gorcunov escr |= P4_ESCR_T0_USR; 206a072738eSCyrill Gorcunov } else { 207a072738eSCyrill Gorcunov if (!exclude_os) 208*d814f301SCyrill Gorcunov escr |= P4_ESCR_T1_OS; 209a072738eSCyrill Gorcunov if (!exclude_usr) 210*d814f301SCyrill Gorcunov escr |= P4_ESCR_T1_USR; 211a072738eSCyrill Gorcunov } 212a072738eSCyrill Gorcunov 213a072738eSCyrill Gorcunov return escr; 214a072738eSCyrill Gorcunov } 215a072738eSCyrill Gorcunov 216*d814f301SCyrill Gorcunov enum P4_EVENTS { 217*d814f301SCyrill Gorcunov P4_EVENT_TC_DELIVER_MODE, 218*d814f301SCyrill Gorcunov P4_EVENT_BPU_FETCH_REQUEST, 219*d814f301SCyrill Gorcunov P4_EVENT_ITLB_REFERENCE, 220*d814f301SCyrill Gorcunov P4_EVENT_MEMORY_CANCEL, 221*d814f301SCyrill Gorcunov P4_EVENT_MEMORY_COMPLETE, 222*d814f301SCyrill Gorcunov P4_EVENT_LOAD_PORT_REPLAY, 223*d814f301SCyrill Gorcunov P4_EVENT_STORE_PORT_REPLAY, 224*d814f301SCyrill Gorcunov P4_EVENT_MOB_LOAD_REPLAY, 225*d814f301SCyrill Gorcunov P4_EVENT_PAGE_WALK_TYPE, 226*d814f301SCyrill Gorcunov P4_EVENT_BSQ_CACHE_REFERENCE, 227*d814f301SCyrill Gorcunov P4_EVENT_IOQ_ALLOCATION, 228*d814f301SCyrill Gorcunov P4_EVENT_IOQ_ACTIVE_ENTRIES, 229*d814f301SCyrill Gorcunov P4_EVENT_FSB_DATA_ACTIVITY, 230*d814f301SCyrill Gorcunov P4_EVENT_BSQ_ALLOCATION, 231*d814f301SCyrill Gorcunov P4_EVENT_BSQ_ACTIVE_ENTRIES, 232*d814f301SCyrill Gorcunov P4_EVENT_SSE_INPUT_ASSIST, 233*d814f301SCyrill Gorcunov P4_EVENT_PACKED_SP_UOP, 234*d814f301SCyrill Gorcunov P4_EVENT_PACKED_DP_UOP, 235*d814f301SCyrill Gorcunov P4_EVENT_SCALAR_SP_UOP, 236*d814f301SCyrill Gorcunov P4_EVENT_SCALAR_DP_UOP, 237*d814f301SCyrill Gorcunov P4_EVENT_64BIT_MMX_UOP, 238*d814f301SCyrill Gorcunov P4_EVENT_128BIT_MMX_UOP, 239*d814f301SCyrill Gorcunov P4_EVENT_X87_FP_UOP, 240*d814f301SCyrill Gorcunov P4_EVENT_TC_MISC, 241*d814f301SCyrill Gorcunov P4_EVENT_GLOBAL_POWER_EVENTS, 242*d814f301SCyrill Gorcunov P4_EVENT_TC_MS_XFER, 243*d814f301SCyrill Gorcunov P4_EVENT_UOP_QUEUE_WRITES, 244*d814f301SCyrill Gorcunov P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE, 245*d814f301SCyrill Gorcunov P4_EVENT_RETIRED_BRANCH_TYPE, 246*d814f301SCyrill Gorcunov P4_EVENT_RESOURCE_STALL, 247*d814f301SCyrill Gorcunov P4_EVENT_WC_BUFFER, 248*d814f301SCyrill Gorcunov P4_EVENT_B2B_CYCLES, 249*d814f301SCyrill Gorcunov P4_EVENT_BNR, 250*d814f301SCyrill Gorcunov P4_EVENT_SNOOP, 251*d814f301SCyrill Gorcunov P4_EVENT_RESPONSE, 252*d814f301SCyrill Gorcunov P4_EVENT_FRONT_END_EVENT, 253*d814f301SCyrill Gorcunov P4_EVENT_EXECUTION_EVENT, 254*d814f301SCyrill Gorcunov P4_EVENT_REPLAY_EVENT, 255*d814f301SCyrill Gorcunov P4_EVENT_INSTR_RETIRED, 256*d814f301SCyrill Gorcunov P4_EVENT_UOPS_RETIRED, 257*d814f301SCyrill Gorcunov P4_EVENT_UOP_TYPE, 258*d814f301SCyrill Gorcunov P4_EVENT_BRANCH_RETIRED, 259*d814f301SCyrill Gorcunov P4_EVENT_MISPRED_BRANCH_RETIRED, 260*d814f301SCyrill Gorcunov P4_EVENT_X87_ASSIST, 261*d814f301SCyrill Gorcunov P4_EVENT_MACHINE_CLEAR, 262*d814f301SCyrill Gorcunov P4_EVENT_INSTR_COMPLETED, 263*d814f301SCyrill Gorcunov }; 264*d814f301SCyrill Gorcunov 265*d814f301SCyrill Gorcunov #define P4_OPCODE(event) event##_OPCODE 266*d814f301SCyrill Gorcunov #define P4_OPCODE_ESEL(opcode) ((opcode & 0x00ff) >> 0) 267*d814f301SCyrill Gorcunov #define P4_OPCODE_EVNT(opcode) ((opcode & 0xff00) >> 8) 268*d814f301SCyrill Gorcunov #define P4_OPCODE_PACK(event, sel) (((event) << 8) | sel) 269*d814f301SCyrill Gorcunov 270a072738eSCyrill Gorcunov /* 271a072738eSCyrill Gorcunov * Comments below the event represent ESCR restriction 272a072738eSCyrill Gorcunov * for this event and counter index per ESCR 273a072738eSCyrill Gorcunov * 274a072738eSCyrill Gorcunov * MSR_P4_IQ_ESCR0 and MSR_P4_IQ_ESCR1 are available only on early 275a072738eSCyrill Gorcunov * processor builds (family 0FH, models 01H-02H). These MSRs 276a072738eSCyrill Gorcunov * are not available on later versions, so that we don't use 277a072738eSCyrill Gorcunov * them completely 278a072738eSCyrill Gorcunov * 279a072738eSCyrill Gorcunov * Also note that CCCR1 do not have P4_CCCR_ENABLE bit properly 280a072738eSCyrill Gorcunov * working so that we should not use this CCCR and respective 281a072738eSCyrill Gorcunov * counter as result 282a072738eSCyrill Gorcunov */ 283*d814f301SCyrill Gorcunov enum P4_EVENT_OPCODES { 284*d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_TC_DELIVER_MODE) = P4_OPCODE_PACK(0x01, 0x01), 285a072738eSCyrill Gorcunov /* 286a072738eSCyrill Gorcunov * MSR_P4_TC_ESCR0: 4, 5 287a072738eSCyrill Gorcunov * MSR_P4_TC_ESCR1: 6, 7 288a072738eSCyrill Gorcunov */ 289a072738eSCyrill Gorcunov 290*d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_BPU_FETCH_REQUEST) = P4_OPCODE_PACK(0x03, 0x00), 291a072738eSCyrill Gorcunov /* 292a072738eSCyrill Gorcunov * MSR_P4_BPU_ESCR0: 0, 1 293a072738eSCyrill Gorcunov * MSR_P4_BPU_ESCR1: 2, 3 294a072738eSCyrill Gorcunov */ 295a072738eSCyrill Gorcunov 296*d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_ITLB_REFERENCE) = P4_OPCODE_PACK(0x18, 0x03), 297a072738eSCyrill Gorcunov /* 298a072738eSCyrill Gorcunov * MSR_P4_ITLB_ESCR0: 0, 1 299a072738eSCyrill Gorcunov * MSR_P4_ITLB_ESCR1: 2, 3 300a072738eSCyrill Gorcunov */ 301a072738eSCyrill Gorcunov 302*d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_MEMORY_CANCEL) = P4_OPCODE_PACK(0x02, 0x05), 303a072738eSCyrill Gorcunov /* 304a072738eSCyrill Gorcunov * MSR_P4_DAC_ESCR0: 8, 9 305a072738eSCyrill Gorcunov * MSR_P4_DAC_ESCR1: 10, 11 306a072738eSCyrill Gorcunov */ 307a072738eSCyrill Gorcunov 308*d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_MEMORY_COMPLETE) = P4_OPCODE_PACK(0x08, 0x02), 309a072738eSCyrill Gorcunov /* 310a072738eSCyrill Gorcunov * MSR_P4_SAAT_ESCR0: 8, 9 311a072738eSCyrill Gorcunov * MSR_P4_SAAT_ESCR1: 10, 11 312a072738eSCyrill Gorcunov */ 313a072738eSCyrill Gorcunov 314*d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_LOAD_PORT_REPLAY) = P4_OPCODE_PACK(0x04, 0x02), 315a072738eSCyrill Gorcunov /* 316a072738eSCyrill Gorcunov * MSR_P4_SAAT_ESCR0: 8, 9 317a072738eSCyrill Gorcunov * MSR_P4_SAAT_ESCR1: 10, 11 318a072738eSCyrill Gorcunov */ 319a072738eSCyrill Gorcunov 320*d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_STORE_PORT_REPLAY) = P4_OPCODE_PACK(0x05, 0x02), 321a072738eSCyrill Gorcunov /* 322a072738eSCyrill Gorcunov * MSR_P4_SAAT_ESCR0: 8, 9 323a072738eSCyrill Gorcunov * MSR_P4_SAAT_ESCR1: 10, 11 324a072738eSCyrill Gorcunov */ 325a072738eSCyrill Gorcunov 326*d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_MOB_LOAD_REPLAY) = P4_OPCODE_PACK(0x03, 0x02), 327a072738eSCyrill Gorcunov /* 328a072738eSCyrill Gorcunov * MSR_P4_MOB_ESCR0: 0, 1 329a072738eSCyrill Gorcunov * MSR_P4_MOB_ESCR1: 2, 3 330a072738eSCyrill Gorcunov */ 331a072738eSCyrill Gorcunov 332*d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_PAGE_WALK_TYPE) = P4_OPCODE_PACK(0x01, 0x04), 333a072738eSCyrill Gorcunov /* 334a072738eSCyrill Gorcunov * MSR_P4_PMH_ESCR0: 0, 1 335a072738eSCyrill Gorcunov * MSR_P4_PMH_ESCR1: 2, 3 336a072738eSCyrill Gorcunov */ 337a072738eSCyrill Gorcunov 338*d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_BSQ_CACHE_REFERENCE) = P4_OPCODE_PACK(0x0c, 0x07), 339a072738eSCyrill Gorcunov /* 340a072738eSCyrill Gorcunov * MSR_P4_BSU_ESCR0: 0, 1 341a072738eSCyrill Gorcunov * MSR_P4_BSU_ESCR1: 2, 3 342a072738eSCyrill Gorcunov */ 343a072738eSCyrill Gorcunov 344*d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_IOQ_ALLOCATION) = P4_OPCODE_PACK(0x03, 0x06), 345a072738eSCyrill Gorcunov /* 346a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR0: 0, 1 347a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR1: 2, 3 348a072738eSCyrill Gorcunov */ 349a072738eSCyrill Gorcunov 350*d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_IOQ_ACTIVE_ENTRIES) = P4_OPCODE_PACK(0x1a, 0x06), 351a072738eSCyrill Gorcunov /* 352a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR1: 2, 3 353a072738eSCyrill Gorcunov */ 354a072738eSCyrill Gorcunov 355*d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_FSB_DATA_ACTIVITY) = P4_OPCODE_PACK(0x17, 0x06), 356a072738eSCyrill Gorcunov /* 357a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR0: 0, 1 358a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR1: 2, 3 359a072738eSCyrill Gorcunov */ 360a072738eSCyrill Gorcunov 361*d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_BSQ_ALLOCATION) = P4_OPCODE_PACK(0x05, 0x07), 362a072738eSCyrill Gorcunov /* 363a072738eSCyrill Gorcunov * MSR_P4_BSU_ESCR0: 0, 1 364a072738eSCyrill Gorcunov */ 365a072738eSCyrill Gorcunov 366*d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_BSQ_ACTIVE_ENTRIES) = P4_OPCODE_PACK(0x06, 0x07), 367a072738eSCyrill Gorcunov /* 3688ea7f544SLin Ming * NOTE: no ESCR name in docs, it's guessed 369a072738eSCyrill Gorcunov * MSR_P4_BSU_ESCR1: 2, 3 370a072738eSCyrill Gorcunov */ 371a072738eSCyrill Gorcunov 372*d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_SSE_INPUT_ASSIST) = P4_OPCODE_PACK(0x34, 0x01), 373a072738eSCyrill Gorcunov /* 374e4495262SCyrill Gorcunov * MSR_P4_FIRM_ESCR0: 8, 9 375e4495262SCyrill Gorcunov * MSR_P4_FIRM_ESCR1: 10, 11 376a072738eSCyrill Gorcunov */ 377a072738eSCyrill Gorcunov 378*d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_PACKED_SP_UOP) = P4_OPCODE_PACK(0x08, 0x01), 379a072738eSCyrill Gorcunov /* 380a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR0: 8, 9 381a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR1: 10, 11 382a072738eSCyrill Gorcunov */ 383a072738eSCyrill Gorcunov 384*d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_PACKED_DP_UOP) = P4_OPCODE_PACK(0x0c, 0x01), 385a072738eSCyrill Gorcunov /* 386a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR0: 8, 9 387a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR1: 10, 11 388a072738eSCyrill Gorcunov */ 389a072738eSCyrill Gorcunov 390*d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_SCALAR_SP_UOP) = P4_OPCODE_PACK(0x0a, 0x01), 391a072738eSCyrill Gorcunov /* 392a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR0: 8, 9 393a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR1: 10, 11 394a072738eSCyrill Gorcunov */ 395a072738eSCyrill Gorcunov 396*d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_SCALAR_DP_UOP) = P4_OPCODE_PACK(0x0e, 0x01), 397a072738eSCyrill Gorcunov /* 398a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR0: 8, 9 399a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR1: 10, 11 400a072738eSCyrill Gorcunov */ 401a072738eSCyrill Gorcunov 402*d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_64BIT_MMX_UOP) = P4_OPCODE_PACK(0x02, 0x01), 403a072738eSCyrill Gorcunov /* 404a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR0: 8, 9 405a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR1: 10, 11 406a072738eSCyrill Gorcunov */ 407a072738eSCyrill Gorcunov 408*d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_128BIT_MMX_UOP) = P4_OPCODE_PACK(0x1a, 0x01), 409a072738eSCyrill Gorcunov /* 410a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR0: 8, 9 411a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR1: 10, 11 412a072738eSCyrill Gorcunov */ 413a072738eSCyrill Gorcunov 414*d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_X87_FP_UOP) = P4_OPCODE_PACK(0x04, 0x01), 415a072738eSCyrill Gorcunov /* 416a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR0: 8, 9 417a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR1: 10, 11 418a072738eSCyrill Gorcunov */ 419a072738eSCyrill Gorcunov 420*d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_TC_MISC) = P4_OPCODE_PACK(0x06, 0x01), 421a072738eSCyrill Gorcunov /* 422a072738eSCyrill Gorcunov * MSR_P4_TC_ESCR0: 4, 5 423a072738eSCyrill Gorcunov * MSR_P4_TC_ESCR1: 6, 7 424a072738eSCyrill Gorcunov */ 425a072738eSCyrill Gorcunov 426*d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_GLOBAL_POWER_EVENTS) = P4_OPCODE_PACK(0x13, 0x06), 427a072738eSCyrill Gorcunov /* 428a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR0: 0, 1 429a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR1: 2, 3 430a072738eSCyrill Gorcunov */ 431a072738eSCyrill Gorcunov 432*d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_TC_MS_XFER) = P4_OPCODE_PACK(0x05, 0x00), 433a072738eSCyrill Gorcunov /* 434a072738eSCyrill Gorcunov * MSR_P4_MS_ESCR0: 4, 5 435a072738eSCyrill Gorcunov * MSR_P4_MS_ESCR1: 6, 7 436a072738eSCyrill Gorcunov */ 437a072738eSCyrill Gorcunov 438*d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_UOP_QUEUE_WRITES) = P4_OPCODE_PACK(0x09, 0x00), 439a072738eSCyrill Gorcunov /* 440a072738eSCyrill Gorcunov * MSR_P4_MS_ESCR0: 4, 5 441a072738eSCyrill Gorcunov * MSR_P4_MS_ESCR1: 6, 7 442a072738eSCyrill Gorcunov */ 443a072738eSCyrill Gorcunov 444*d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE) = P4_OPCODE_PACK(0x05, 0x02), 445a072738eSCyrill Gorcunov /* 446a072738eSCyrill Gorcunov * MSR_P4_TBPU_ESCR0: 4, 5 4479c8c6badSCyrill Gorcunov * MSR_P4_TBPU_ESCR1: 6, 7 448a072738eSCyrill Gorcunov */ 449a072738eSCyrill Gorcunov 450*d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_RETIRED_BRANCH_TYPE) = P4_OPCODE_PACK(0x04, 0x02), 451a072738eSCyrill Gorcunov /* 452a072738eSCyrill Gorcunov * MSR_P4_TBPU_ESCR0: 4, 5 4539c8c6badSCyrill Gorcunov * MSR_P4_TBPU_ESCR1: 6, 7 454a072738eSCyrill Gorcunov */ 455a072738eSCyrill Gorcunov 456*d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_RESOURCE_STALL) = P4_OPCODE_PACK(0x01, 0x01), 457a072738eSCyrill Gorcunov /* 458a072738eSCyrill Gorcunov * MSR_P4_ALF_ESCR0: 12, 13, 16 459a072738eSCyrill Gorcunov * MSR_P4_ALF_ESCR1: 14, 15, 17 460a072738eSCyrill Gorcunov */ 461a072738eSCyrill Gorcunov 462*d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_WC_BUFFER) = P4_OPCODE_PACK(0x05, 0x05), 463a072738eSCyrill Gorcunov /* 464a072738eSCyrill Gorcunov * MSR_P4_DAC_ESCR0: 8, 9 465a072738eSCyrill Gorcunov * MSR_P4_DAC_ESCR1: 10, 11 466a072738eSCyrill Gorcunov */ 467a072738eSCyrill Gorcunov 468*d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_B2B_CYCLES) = P4_OPCODE_PACK(0x16, 0x03), 469a072738eSCyrill Gorcunov /* 470a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR0: 0, 1 471a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR1: 2, 3 472a072738eSCyrill Gorcunov */ 473a072738eSCyrill Gorcunov 474*d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_BNR) = P4_OPCODE_PACK(0x08, 0x03), 475a072738eSCyrill Gorcunov /* 476a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR0: 0, 1 477a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR1: 2, 3 478a072738eSCyrill Gorcunov */ 479a072738eSCyrill Gorcunov 480*d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_SNOOP) = P4_OPCODE_PACK(0x06, 0x03), 481a072738eSCyrill Gorcunov /* 482a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR0: 0, 1 483a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR1: 2, 3 484a072738eSCyrill Gorcunov */ 485a072738eSCyrill Gorcunov 486*d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_RESPONSE) = P4_OPCODE_PACK(0x04, 0x03), 487a072738eSCyrill Gorcunov /* 488a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR0: 0, 1 489a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR1: 2, 3 490a072738eSCyrill Gorcunov */ 491a072738eSCyrill Gorcunov 492*d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_FRONT_END_EVENT) = P4_OPCODE_PACK(0x08, 0x05), 493a072738eSCyrill Gorcunov /* 494a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR2: 12, 13, 16 495a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR3: 14, 15, 17 496a072738eSCyrill Gorcunov */ 497a072738eSCyrill Gorcunov 498*d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_EXECUTION_EVENT) = P4_OPCODE_PACK(0x0c, 0x05), 499a072738eSCyrill Gorcunov /* 500a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR2: 12, 13, 16 501a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR3: 14, 15, 17 502a072738eSCyrill Gorcunov */ 503a072738eSCyrill Gorcunov 504*d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_REPLAY_EVENT) = P4_OPCODE_PACK(0x09, 0x05), 505a072738eSCyrill Gorcunov /* 506a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR2: 12, 13, 16 507a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR3: 14, 15, 17 508a072738eSCyrill Gorcunov */ 509a072738eSCyrill Gorcunov 510*d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_INSTR_RETIRED) = P4_OPCODE_PACK(0x02, 0x04), 511a072738eSCyrill Gorcunov /* 512e4495262SCyrill Gorcunov * MSR_P4_CRU_ESCR0: 12, 13, 16 513e4495262SCyrill Gorcunov * MSR_P4_CRU_ESCR1: 14, 15, 17 514a072738eSCyrill Gorcunov */ 515a072738eSCyrill Gorcunov 516*d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_UOPS_RETIRED) = P4_OPCODE_PACK(0x01, 0x04), 517a072738eSCyrill Gorcunov /* 5188ea7f544SLin Ming * MSR_P4_CRU_ESCR0: 12, 13, 16 5198ea7f544SLin Ming * MSR_P4_CRU_ESCR1: 14, 15, 17 520a072738eSCyrill Gorcunov */ 521a072738eSCyrill Gorcunov 522*d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_UOP_TYPE) = P4_OPCODE_PACK(0x02, 0x02), 523a072738eSCyrill Gorcunov /* 524a072738eSCyrill Gorcunov * MSR_P4_RAT_ESCR0: 12, 13, 16 525a072738eSCyrill Gorcunov * MSR_P4_RAT_ESCR1: 14, 15, 17 526a072738eSCyrill Gorcunov */ 527a072738eSCyrill Gorcunov 528*d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_BRANCH_RETIRED) = P4_OPCODE_PACK(0x06, 0x05), 529a072738eSCyrill Gorcunov /* 530a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR2: 12, 13, 16 531a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR3: 14, 15, 17 532a072738eSCyrill Gorcunov */ 533a072738eSCyrill Gorcunov 534*d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_MISPRED_BRANCH_RETIRED) = P4_OPCODE_PACK(0x03, 0x04), 535a072738eSCyrill Gorcunov /* 536a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR0: 12, 13, 16 537a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR1: 14, 15, 17 538a072738eSCyrill Gorcunov */ 539a072738eSCyrill Gorcunov 540*d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_X87_ASSIST) = P4_OPCODE_PACK(0x03, 0x05), 541a072738eSCyrill Gorcunov /* 542a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR2: 12, 13, 16 543a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR3: 14, 15, 17 544a072738eSCyrill Gorcunov */ 545a072738eSCyrill Gorcunov 546*d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_MACHINE_CLEAR) = P4_OPCODE_PACK(0x02, 0x05), 547a072738eSCyrill Gorcunov /* 548a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR2: 12, 13, 16 549a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR3: 14, 15, 17 550a072738eSCyrill Gorcunov */ 551a072738eSCyrill Gorcunov 552*d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_INSTR_COMPLETED) = P4_OPCODE_PACK(0x07, 0x04), 553a072738eSCyrill Gorcunov /* 554a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR0: 12, 13, 16 555a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR1: 14, 15, 17 556a072738eSCyrill Gorcunov */ 557a072738eSCyrill Gorcunov }; 558a072738eSCyrill Gorcunov 559*d814f301SCyrill Gorcunov /* 560*d814f301SCyrill Gorcunov * a caller should use P4_ESCR_EMASK_NAME helper to 561*d814f301SCyrill Gorcunov * pick the EventMask needed, for example 562*d814f301SCyrill Gorcunov * 563*d814f301SCyrill Gorcunov * P4_ESCR_EMASK_NAME(P4_EVENT_TC_DELIVER_MODE, DD) 564*d814f301SCyrill Gorcunov */ 565*d814f301SCyrill Gorcunov enum P4_ESCR_EMASKS { 566*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, DD, 0), 567*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, DB, 1), 568*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, DI, 2), 569*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, BD, 3), 570*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, BB, 4), 571*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, BI, 5), 572*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, ID, 6), 573*d814f301SCyrill Gorcunov 574*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BPU_FETCH_REQUEST, TCMISS, 0), 575*d814f301SCyrill Gorcunov 576*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_ITLB_REFERENCE, HIT, 0), 577*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_ITLB_REFERENCE, MISS, 1), 578*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_ITLB_REFERENCE, HIT_UK, 2), 579*d814f301SCyrill Gorcunov 580*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_MEMORY_CANCEL, ST_RB_FULL, 2), 581*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_MEMORY_CANCEL, 64K_CONF, 3), 582*d814f301SCyrill Gorcunov 583*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_MEMORY_COMPLETE, LSC, 0), 584*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_MEMORY_COMPLETE, SSC, 1), 585*d814f301SCyrill Gorcunov 586*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_LOAD_PORT_REPLAY, SPLIT_LD, 1), 587*d814f301SCyrill Gorcunov 588*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_STORE_PORT_REPLAY, SPLIT_ST, 1), 589*d814f301SCyrill Gorcunov 590*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_MOB_LOAD_REPLAY, NO_STA, 1), 591*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_MOB_LOAD_REPLAY, NO_STD, 3), 592*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_MOB_LOAD_REPLAY, PARTIAL_DATA, 4), 593*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_MOB_LOAD_REPLAY, UNALGN_ADDR, 5), 594*d814f301SCyrill Gorcunov 595*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_PAGE_WALK_TYPE, DTMISS, 0), 596*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_PAGE_WALK_TYPE, ITMISS, 1), 597*d814f301SCyrill Gorcunov 598*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_HITS, 0), 599*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_HITE, 1), 600*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_HITM, 2), 601*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_HITS, 3), 602*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_HITE, 4), 603*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_HITM, 5), 604*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_MISS, 8), 605*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_MISS, 9), 606*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, WR_2ndL_MISS, 10), 607*d814f301SCyrill Gorcunov 608*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, DEFAULT, 0), 609*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, ALL_READ, 5), 610*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, ALL_WRITE, 6), 611*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, MEM_UC, 7), 612*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, MEM_WC, 8), 613*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, MEM_WT, 9), 614*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, MEM_WP, 10), 615*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, MEM_WB, 11), 616*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, OWN, 13), 617*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, OTHER, 14), 618*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, PREFETCH, 15), 619*d814f301SCyrill Gorcunov 620*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, DEFAULT, 0), 621*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, ALL_READ, 5), 622*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, ALL_WRITE, 6), 623*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, MEM_UC, 7), 624*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, MEM_WC, 8), 625*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, MEM_WT, 9), 626*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, MEM_WP, 10), 627*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, MEM_WB, 11), 628*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, OWN, 13), 629*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, OTHER, 14), 630*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, PREFETCH, 15), 631*d814f301SCyrill Gorcunov 632*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_FSB_DATA_ACTIVITY, DRDY_DRV, 0), 633*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_FSB_DATA_ACTIVITY, DRDY_OWN, 1), 634*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_FSB_DATA_ACTIVITY, DRDY_OTHER, 2), 635*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_FSB_DATA_ACTIVITY, DBSY_DRV, 3), 636*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_FSB_DATA_ACTIVITY, DBSY_OWN, 4), 637*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_FSB_DATA_ACTIVITY, DBSY_OTHER, 5), 638*d814f301SCyrill Gorcunov 639*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_TYPE0, 0), 640*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_TYPE1, 1), 641*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_LEN0, 2), 642*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_LEN1, 3), 643*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_IO_TYPE, 5), 644*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_LOCK_TYPE, 6), 645*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_CACHE_TYPE, 7), 646*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_SPLIT_TYPE, 8), 647*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_DEM_TYPE, 9), 648*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_ORD_TYPE, 10), 649*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, MEM_TYPE0, 11), 650*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, MEM_TYPE1, 12), 651*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, MEM_TYPE2, 13), 652*d814f301SCyrill Gorcunov 653*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_TYPE0, 0), 654*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_TYPE1, 1), 655*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_LEN0, 2), 656*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_LEN1, 3), 657*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_IO_TYPE, 5), 658*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_LOCK_TYPE, 6), 659*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_CACHE_TYPE, 7), 660*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_SPLIT_TYPE, 8), 661*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_DEM_TYPE, 9), 662*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_ORD_TYPE, 10), 663*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, MEM_TYPE0, 11), 664*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, MEM_TYPE1, 12), 665*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, MEM_TYPE2, 13), 666*d814f301SCyrill Gorcunov 667*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_SSE_INPUT_ASSIST, ALL, 15), 668*d814f301SCyrill Gorcunov 669*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_PACKED_SP_UOP, ALL, 15), 670*d814f301SCyrill Gorcunov 671*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_PACKED_DP_UOP, ALL, 15), 672*d814f301SCyrill Gorcunov 673*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_SCALAR_SP_UOP, ALL, 15), 674*d814f301SCyrill Gorcunov 675*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_SCALAR_DP_UOP, ALL, 15), 676*d814f301SCyrill Gorcunov 677*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_64BIT_MMX_UOP, ALL, 15), 678*d814f301SCyrill Gorcunov 679*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_128BIT_MMX_UOP, ALL, 15), 680*d814f301SCyrill Gorcunov 681*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_X87_FP_UOP, ALL, 15), 682*d814f301SCyrill Gorcunov 683*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_TC_MISC, FLUSH, 4), 684*d814f301SCyrill Gorcunov 685*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_GLOBAL_POWER_EVENTS, RUNNING, 0), 686*d814f301SCyrill Gorcunov 687*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_TC_MS_XFER, CISC, 0), 688*d814f301SCyrill Gorcunov 689*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_UOP_QUEUE_WRITES, FROM_TC_BUILD, 0), 690*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_UOP_QUEUE_WRITES, FROM_TC_DELIVER, 1), 691*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_UOP_QUEUE_WRITES, FROM_ROM, 2), 692*d814f301SCyrill Gorcunov 693*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE, CONDITIONAL, 1), 694*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE, CALL, 2), 695*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE, RETURN, 3), 696*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE, INDIRECT, 4), 697*d814f301SCyrill Gorcunov 698*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_BRANCH_TYPE, CONDITIONAL, 1), 699*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_BRANCH_TYPE, CALL, 2), 700*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_BRANCH_TYPE, RETURN, 3), 701*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_BRANCH_TYPE, INDIRECT, 4), 702*d814f301SCyrill Gorcunov 703*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_RESOURCE_STALL, SBFULL, 5), 704*d814f301SCyrill Gorcunov 705*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_WC_BUFFER, WCB_EVICTS, 0), 706*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_WC_BUFFER, WCB_FULL_EVICTS, 1), 707*d814f301SCyrill Gorcunov 708*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_FRONT_END_EVENT, NBOGUS, 0), 709*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_FRONT_END_EVENT, BOGUS, 1), 710*d814f301SCyrill Gorcunov 711*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, NBOGUS0, 0), 712*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, NBOGUS1, 1), 713*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, NBOGUS2, 2), 714*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, NBOGUS3, 3), 715*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, BOGUS0, 4), 716*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, BOGUS1, 5), 717*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, BOGUS2, 6), 718*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, BOGUS3, 7), 719*d814f301SCyrill Gorcunov 720*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_REPLAY_EVENT, NBOGUS, 0), 721*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_REPLAY_EVENT, BOGUS, 1), 722*d814f301SCyrill Gorcunov 723*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_INSTR_RETIRED, NBOGUSNTAG, 0), 724*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_INSTR_RETIRED, NBOGUSTAG, 1), 725*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_INSTR_RETIRED, BOGUSNTAG, 2), 726*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_INSTR_RETIRED, BOGUSTAG, 3), 727*d814f301SCyrill Gorcunov 728*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_UOPS_RETIRED, NBOGUS, 0), 729*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_UOPS_RETIRED, BOGUS, 1), 730*d814f301SCyrill Gorcunov 731*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_UOP_TYPE, TAGLOADS, 1), 732*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_UOP_TYPE, TAGSTORES, 2), 733*d814f301SCyrill Gorcunov 734*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BRANCH_RETIRED, MMNP, 0), 735*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BRANCH_RETIRED, MMNM, 1), 736*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BRANCH_RETIRED, MMTP, 2), 737*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BRANCH_RETIRED, MMTM, 3), 738*d814f301SCyrill Gorcunov 739*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_MISPRED_BRANCH_RETIRED, NBOGUS, 0), 740*d814f301SCyrill Gorcunov 741*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_X87_ASSIST, FPSU, 0), 742*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_X87_ASSIST, FPSO, 1), 743*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_X87_ASSIST, POAO, 2), 744*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_X87_ASSIST, POAU, 3), 745*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_X87_ASSIST, PREA, 4), 746*d814f301SCyrill Gorcunov 747*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_MACHINE_CLEAR, CLEAR, 0), 748*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_MACHINE_CLEAR, MOCLEAR, 1), 749*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_MACHINE_CLEAR, SMCLEAR, 2), 750*d814f301SCyrill Gorcunov 751*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_INSTR_COMPLETED, NBOGUS, 0), 752*d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_INSTR_COMPLETED, BOGUS, 1), 753*d814f301SCyrill Gorcunov }; 754*d814f301SCyrill Gorcunov 755*d814f301SCyrill Gorcunov /* P4 PEBS: stale for a while */ 756*d814f301SCyrill Gorcunov #define P4_PEBS_METRIC_MASK 0x00001fffU 757*d814f301SCyrill Gorcunov #define P4_PEBS_UOB_TAG 0x01000000U 758*d814f301SCyrill Gorcunov #define P4_PEBS_ENABLE 0x02000000U 759*d814f301SCyrill Gorcunov 760*d814f301SCyrill Gorcunov /* Replay metrics for MSR_IA32_PEBS_ENABLE and MSR_P4_PEBS_MATRIX_VERT */ 761*d814f301SCyrill Gorcunov #define P4_PEBS__1stl_cache_load_miss_retired 0x3000001 762*d814f301SCyrill Gorcunov #define P4_PEBS__2ndl_cache_load_miss_retired 0x3000002 763*d814f301SCyrill Gorcunov #define P4_PEBS__dtlb_load_miss_retired 0x3000004 764*d814f301SCyrill Gorcunov #define P4_PEBS__dtlb_store_miss_retired 0x3000004 765*d814f301SCyrill Gorcunov #define P4_PEBS__dtlb_all_miss_retired 0x3000004 766*d814f301SCyrill Gorcunov #define P4_PEBS__tagged_mispred_branch 0x3018000 767*d814f301SCyrill Gorcunov #define P4_PEBS__mob_load_replay_retired 0x3000200 768*d814f301SCyrill Gorcunov #define P4_PEBS__split_load_retired 0x3000400 769*d814f301SCyrill Gorcunov #define P4_PEBS__split_store_retired 0x3000400 770*d814f301SCyrill Gorcunov 771*d814f301SCyrill Gorcunov #define P4_VERT__1stl_cache_load_miss_retired 0x0000001 772*d814f301SCyrill Gorcunov #define P4_VERT__2ndl_cache_load_miss_retired 0x0000001 773*d814f301SCyrill Gorcunov #define P4_VERT__dtlb_load_miss_retired 0x0000001 774*d814f301SCyrill Gorcunov #define P4_VERT__dtlb_store_miss_retired 0x0000002 775*d814f301SCyrill Gorcunov #define P4_VERT__dtlb_all_miss_retired 0x0000003 776*d814f301SCyrill Gorcunov #define P4_VERT__tagged_mispred_branch 0x0000010 777*d814f301SCyrill Gorcunov #define P4_VERT__mob_load_replay_retired 0x0000001 778*d814f301SCyrill Gorcunov #define P4_VERT__split_load_retired 0x0000001 779*d814f301SCyrill Gorcunov #define P4_VERT__split_store_retired 0x0000002 780*d814f301SCyrill Gorcunov 781*d814f301SCyrill Gorcunov enum P4_CACHE_EVENTS { 782*d814f301SCyrill Gorcunov P4_CACHE__NONE, 783*d814f301SCyrill Gorcunov 784*d814f301SCyrill Gorcunov P4_CACHE__1stl_cache_load_miss_retired, 785*d814f301SCyrill Gorcunov P4_CACHE__2ndl_cache_load_miss_retired, 786*d814f301SCyrill Gorcunov P4_CACHE__dtlb_load_miss_retired, 787*d814f301SCyrill Gorcunov P4_CACHE__dtlb_store_miss_retired, 788*d814f301SCyrill Gorcunov P4_CACHE__itlb_reference_hit, 789*d814f301SCyrill Gorcunov P4_CACHE__itlb_reference_miss, 790*d814f301SCyrill Gorcunov 791*d814f301SCyrill Gorcunov P4_CACHE__MAX 792cb7d6b50SLin Ming }; 793cb7d6b50SLin Ming 794a072738eSCyrill Gorcunov #endif /* PERF_EVENT_P4_H */ 795