1a072738eSCyrill Gorcunov /* 2a072738eSCyrill Gorcunov * Netburst Perfomance Events (P4, old Xeon) 3a072738eSCyrill Gorcunov */ 4a072738eSCyrill Gorcunov 5a072738eSCyrill Gorcunov #ifndef PERF_EVENT_P4_H 6a072738eSCyrill Gorcunov #define PERF_EVENT_P4_H 7a072738eSCyrill Gorcunov 8a072738eSCyrill Gorcunov #include <linux/cpu.h> 9a072738eSCyrill Gorcunov #include <linux/bitops.h> 10a072738eSCyrill Gorcunov 11a072738eSCyrill Gorcunov /* 12a072738eSCyrill Gorcunov * NetBurst has perfomance MSRs shared between 13a072738eSCyrill Gorcunov * threads if HT is turned on, ie for both logical 14a072738eSCyrill Gorcunov * processors (mem: in turn in Atom with HT support 15a072738eSCyrill Gorcunov * perf-MSRs are not shared and every thread has its 16a072738eSCyrill Gorcunov * own perf-MSRs set) 17a072738eSCyrill Gorcunov */ 18a072738eSCyrill Gorcunov #define ARCH_P4_TOTAL_ESCR (46) 19a072738eSCyrill Gorcunov #define ARCH_P4_RESERVED_ESCR (2) /* IQ_ESCR(0,1) not always present */ 20a072738eSCyrill Gorcunov #define ARCH_P4_MAX_ESCR (ARCH_P4_TOTAL_ESCR - ARCH_P4_RESERVED_ESCR) 21a072738eSCyrill Gorcunov #define ARCH_P4_MAX_CCCR (18) 22a072738eSCyrill Gorcunov #define ARCH_P4_MAX_COUNTER (ARCH_P4_MAX_CCCR / 2) 23a072738eSCyrill Gorcunov 24a072738eSCyrill Gorcunov #define P4_EVNTSEL_EVENT_MASK 0x7e000000U 25a072738eSCyrill Gorcunov #define P4_EVNTSEL_EVENT_SHIFT 25 26a072738eSCyrill Gorcunov #define P4_EVNTSEL_EVENTMASK_MASK 0x01fffe00U 27a072738eSCyrill Gorcunov #define P4_EVNTSEL_EVENTMASK_SHIFT 9 28a072738eSCyrill Gorcunov #define P4_EVNTSEL_TAG_MASK 0x000001e0U 29a072738eSCyrill Gorcunov #define P4_EVNTSEL_TAG_SHIFT 5 30a072738eSCyrill Gorcunov #define P4_EVNTSEL_TAG_ENABLE 0x00000010U 31a072738eSCyrill Gorcunov #define P4_EVNTSEL_T0_OS 0x00000008U 32a072738eSCyrill Gorcunov #define P4_EVNTSEL_T0_USR 0x00000004U 33a072738eSCyrill Gorcunov #define P4_EVNTSEL_T1_OS 0x00000002U 34a072738eSCyrill Gorcunov #define P4_EVNTSEL_T1_USR 0x00000001U 35a072738eSCyrill Gorcunov 36a072738eSCyrill Gorcunov /* Non HT mask */ 37a072738eSCyrill Gorcunov #define P4_EVNTSEL_MASK \ 38a072738eSCyrill Gorcunov (P4_EVNTSEL_EVENT_MASK | \ 39a072738eSCyrill Gorcunov P4_EVNTSEL_EVENTMASK_MASK | \ 40a072738eSCyrill Gorcunov P4_EVNTSEL_TAG_MASK | \ 41a072738eSCyrill Gorcunov P4_EVNTSEL_TAG_ENABLE | \ 42a072738eSCyrill Gorcunov P4_EVNTSEL_T0_OS | \ 43a072738eSCyrill Gorcunov P4_EVNTSEL_T0_USR) 44a072738eSCyrill Gorcunov 45a072738eSCyrill Gorcunov /* HT mask */ 46a072738eSCyrill Gorcunov #define P4_EVNTSEL_MASK_HT \ 47a072738eSCyrill Gorcunov (P4_EVNTSEL_MASK | \ 48a072738eSCyrill Gorcunov P4_EVNTSEL_T1_OS | \ 49a072738eSCyrill Gorcunov P4_EVNTSEL_T1_USR) 50a072738eSCyrill Gorcunov 51a072738eSCyrill Gorcunov #define P4_CCCR_OVF 0x80000000U 52a072738eSCyrill Gorcunov #define P4_CCCR_CASCADE 0x40000000U 53a072738eSCyrill Gorcunov #define P4_CCCR_OVF_PMI_T0 0x04000000U 54a072738eSCyrill Gorcunov #define P4_CCCR_OVF_PMI_T1 0x08000000U 55a072738eSCyrill Gorcunov #define P4_CCCR_FORCE_OVF 0x02000000U 56a072738eSCyrill Gorcunov #define P4_CCCR_EDGE 0x01000000U 57a072738eSCyrill Gorcunov #define P4_CCCR_THRESHOLD_MASK 0x00f00000U 58a072738eSCyrill Gorcunov #define P4_CCCR_THRESHOLD_SHIFT 20 59a072738eSCyrill Gorcunov #define P4_CCCR_THRESHOLD(v) ((v) << P4_CCCR_THRESHOLD_SHIFT) 60a072738eSCyrill Gorcunov #define P4_CCCR_COMPLEMENT 0x00080000U 61a072738eSCyrill Gorcunov #define P4_CCCR_COMPARE 0x00040000U 62a072738eSCyrill Gorcunov #define P4_CCCR_ESCR_SELECT_MASK 0x0000e000U 63a072738eSCyrill Gorcunov #define P4_CCCR_ESCR_SELECT_SHIFT 13 64a072738eSCyrill Gorcunov #define P4_CCCR_ENABLE 0x00001000U 65a072738eSCyrill Gorcunov #define P4_CCCR_THREAD_SINGLE 0x00010000U 66a072738eSCyrill Gorcunov #define P4_CCCR_THREAD_BOTH 0x00020000U 67a072738eSCyrill Gorcunov #define P4_CCCR_THREAD_ANY 0x00030000U 68f34edbc1SLin Ming #define P4_CCCR_RESERVED 0x00000fffU 69a072738eSCyrill Gorcunov 70a072738eSCyrill Gorcunov /* Non HT mask */ 71a072738eSCyrill Gorcunov #define P4_CCCR_MASK \ 72a072738eSCyrill Gorcunov (P4_CCCR_OVF | \ 73a072738eSCyrill Gorcunov P4_CCCR_CASCADE | \ 74a072738eSCyrill Gorcunov P4_CCCR_OVF_PMI_T0 | \ 75a072738eSCyrill Gorcunov P4_CCCR_FORCE_OVF | \ 76a072738eSCyrill Gorcunov P4_CCCR_EDGE | \ 77a072738eSCyrill Gorcunov P4_CCCR_THRESHOLD_MASK | \ 78a072738eSCyrill Gorcunov P4_CCCR_COMPLEMENT | \ 79a072738eSCyrill Gorcunov P4_CCCR_COMPARE | \ 80a072738eSCyrill Gorcunov P4_CCCR_ESCR_SELECT_MASK | \ 81a072738eSCyrill Gorcunov P4_CCCR_ENABLE) 82a072738eSCyrill Gorcunov 83a072738eSCyrill Gorcunov /* HT mask */ 84a072738eSCyrill Gorcunov #define P4_CCCR_MASK_HT \ 85a072738eSCyrill Gorcunov (P4_CCCR_MASK | \ 86a072738eSCyrill Gorcunov P4_CCCR_THREAD_ANY) 87a072738eSCyrill Gorcunov 88a072738eSCyrill Gorcunov /* 89a072738eSCyrill Gorcunov * format is 32 bit: ee ss aa aa 90a072738eSCyrill Gorcunov * where 91a072738eSCyrill Gorcunov * ee - 8 bit event 92a072738eSCyrill Gorcunov * ss - 8 bit selector 93a072738eSCyrill Gorcunov * aa aa - 16 bits reserved for tags/attributes 94a072738eSCyrill Gorcunov */ 95a072738eSCyrill Gorcunov #define P4_EVENT_PACK(event, selector) (((event) << 24) | ((selector) << 16)) 96a072738eSCyrill Gorcunov #define P4_EVENT_UNPACK_EVENT(packed) (((packed) >> 24) & 0xff) 97a072738eSCyrill Gorcunov #define P4_EVENT_UNPACK_SELECTOR(packed) (((packed) >> 16) & 0xff) 98a072738eSCyrill Gorcunov #define P4_EVENT_PACK_ATTR(attr) ((attr)) 99a072738eSCyrill Gorcunov #define P4_EVENT_UNPACK_ATTR(packed) ((packed) & 0xffff) 100a072738eSCyrill Gorcunov #define P4_MAKE_EVENT_ATTR(class, name, bit) class##_##name = (1 << bit) 101a072738eSCyrill Gorcunov #define P4_EVENT_ATTR(class, name) class##_##name 102a072738eSCyrill Gorcunov #define P4_EVENT_ATTR_STR(class, name) __stringify(class##_##name) 103a072738eSCyrill Gorcunov 104a072738eSCyrill Gorcunov /* 105a072738eSCyrill Gorcunov * config field is 64bit width and consists of 106a072738eSCyrill Gorcunov * HT << 63 | ESCR << 32 | CCCR 107a072738eSCyrill Gorcunov * where HT is HyperThreading bit (since ESCR 108a072738eSCyrill Gorcunov * has it reserved we may use it for own purpose) 109a072738eSCyrill Gorcunov * 110a072738eSCyrill Gorcunov * note that this is NOT the addresses of respective 111a072738eSCyrill Gorcunov * ESCR and CCCR but rather an only packed value should 112a072738eSCyrill Gorcunov * be unpacked and written to a proper addresses 113a072738eSCyrill Gorcunov * 114a072738eSCyrill Gorcunov * the base idea is to pack as much info as 115a072738eSCyrill Gorcunov * possible 116a072738eSCyrill Gorcunov */ 117a072738eSCyrill Gorcunov #define p4_config_pack_escr(v) (((u64)(v)) << 32) 118a072738eSCyrill Gorcunov #define p4_config_pack_cccr(v) (((u64)(v)) & 0xffffffffULL) 119a072738eSCyrill Gorcunov #define p4_config_unpack_escr(v) (((u64)(v)) >> 32) 120f34edbc1SLin Ming #define p4_config_unpack_cccr(v) (((u64)(v)) & 0xfffff000ULL) 121a072738eSCyrill Gorcunov 122a072738eSCyrill Gorcunov #define p4_config_unpack_emask(v) \ 123a072738eSCyrill Gorcunov ({ \ 124a072738eSCyrill Gorcunov u32 t = p4_config_unpack_escr((v)); \ 125a072738eSCyrill Gorcunov t &= P4_EVNTSEL_EVENTMASK_MASK; \ 126a072738eSCyrill Gorcunov t >>= P4_EVNTSEL_EVENTMASK_SHIFT; \ 127a072738eSCyrill Gorcunov t; \ 128a072738eSCyrill Gorcunov }) 129a072738eSCyrill Gorcunov 130f34edbc1SLin Ming #define p4_config_unpack_key(v) (((u64)(v)) & P4_CCCR_RESERVED) 131f34edbc1SLin Ming 132a072738eSCyrill Gorcunov #define P4_CONFIG_HT_SHIFT 63 133a072738eSCyrill Gorcunov #define P4_CONFIG_HT (1ULL << P4_CONFIG_HT_SHIFT) 134a072738eSCyrill Gorcunov 135a072738eSCyrill Gorcunov static inline u32 p4_config_unpack_opcode(u64 config) 136a072738eSCyrill Gorcunov { 137a072738eSCyrill Gorcunov u32 e, s; 138a072738eSCyrill Gorcunov 139a072738eSCyrill Gorcunov /* 140a072738eSCyrill Gorcunov * we don't care about HT presence here since 141a072738eSCyrill Gorcunov * event opcode doesn't depend on it 142a072738eSCyrill Gorcunov */ 143a072738eSCyrill Gorcunov e = (p4_config_unpack_escr(config) & P4_EVNTSEL_EVENT_MASK) >> P4_EVNTSEL_EVENT_SHIFT; 144a072738eSCyrill Gorcunov s = (p4_config_unpack_cccr(config) & P4_CCCR_ESCR_SELECT_MASK) >> P4_CCCR_ESCR_SELECT_SHIFT; 145a072738eSCyrill Gorcunov 146a072738eSCyrill Gorcunov return P4_EVENT_PACK(e, s); 147a072738eSCyrill Gorcunov } 148a072738eSCyrill Gorcunov 149a072738eSCyrill Gorcunov static inline bool p4_is_event_cascaded(u64 config) 150a072738eSCyrill Gorcunov { 151a072738eSCyrill Gorcunov u32 cccr = p4_config_unpack_cccr(config); 152a072738eSCyrill Gorcunov return !!(cccr & P4_CCCR_CASCADE); 153a072738eSCyrill Gorcunov } 154a072738eSCyrill Gorcunov 155a072738eSCyrill Gorcunov static inline int p4_ht_config_thread(u64 config) 156a072738eSCyrill Gorcunov { 157a072738eSCyrill Gorcunov return !!(config & P4_CONFIG_HT); 158a072738eSCyrill Gorcunov } 159a072738eSCyrill Gorcunov 160a072738eSCyrill Gorcunov static inline u64 p4_set_ht_bit(u64 config) 161a072738eSCyrill Gorcunov { 162a072738eSCyrill Gorcunov return config | P4_CONFIG_HT; 163a072738eSCyrill Gorcunov } 164a072738eSCyrill Gorcunov 165a072738eSCyrill Gorcunov static inline u64 p4_clear_ht_bit(u64 config) 166a072738eSCyrill Gorcunov { 167a072738eSCyrill Gorcunov return config & ~P4_CONFIG_HT; 168a072738eSCyrill Gorcunov } 169a072738eSCyrill Gorcunov 170a072738eSCyrill Gorcunov static inline int p4_ht_active(void) 171a072738eSCyrill Gorcunov { 172a072738eSCyrill Gorcunov #ifdef CONFIG_SMP 173a072738eSCyrill Gorcunov return smp_num_siblings > 1; 174a072738eSCyrill Gorcunov #endif 175a072738eSCyrill Gorcunov return 0; 176a072738eSCyrill Gorcunov } 177a072738eSCyrill Gorcunov 178a072738eSCyrill Gorcunov static inline int p4_ht_thread(int cpu) 179a072738eSCyrill Gorcunov { 180a072738eSCyrill Gorcunov #ifdef CONFIG_SMP 181a072738eSCyrill Gorcunov if (smp_num_siblings == 2) 182a072738eSCyrill Gorcunov return cpu != cpumask_first(__get_cpu_var(cpu_sibling_map)); 183a072738eSCyrill Gorcunov #endif 184a072738eSCyrill Gorcunov return 0; 185a072738eSCyrill Gorcunov } 186a072738eSCyrill Gorcunov 187a072738eSCyrill Gorcunov static inline int p4_should_swap_ts(u64 config, int cpu) 188a072738eSCyrill Gorcunov { 189a072738eSCyrill Gorcunov return p4_ht_config_thread(config) ^ p4_ht_thread(cpu); 190a072738eSCyrill Gorcunov } 191a072738eSCyrill Gorcunov 192a072738eSCyrill Gorcunov static inline u32 p4_default_cccr_conf(int cpu) 193a072738eSCyrill Gorcunov { 194a072738eSCyrill Gorcunov /* 195a072738eSCyrill Gorcunov * Note that P4_CCCR_THREAD_ANY is "required" on 196a072738eSCyrill Gorcunov * non-HT machines (on HT machines we count TS events 197a072738eSCyrill Gorcunov * regardless the state of second logical processor 198a072738eSCyrill Gorcunov */ 199a072738eSCyrill Gorcunov u32 cccr = P4_CCCR_THREAD_ANY; 200a072738eSCyrill Gorcunov 201a072738eSCyrill Gorcunov if (!p4_ht_thread(cpu)) 202a072738eSCyrill Gorcunov cccr |= P4_CCCR_OVF_PMI_T0; 203a072738eSCyrill Gorcunov else 204a072738eSCyrill Gorcunov cccr |= P4_CCCR_OVF_PMI_T1; 205a072738eSCyrill Gorcunov 206a072738eSCyrill Gorcunov return cccr; 207a072738eSCyrill Gorcunov } 208a072738eSCyrill Gorcunov 209a072738eSCyrill Gorcunov static inline u32 p4_default_escr_conf(int cpu, int exclude_os, int exclude_usr) 210a072738eSCyrill Gorcunov { 211a072738eSCyrill Gorcunov u32 escr = 0; 212a072738eSCyrill Gorcunov 213a072738eSCyrill Gorcunov if (!p4_ht_thread(cpu)) { 214a072738eSCyrill Gorcunov if (!exclude_os) 215a072738eSCyrill Gorcunov escr |= P4_EVNTSEL_T0_OS; 216a072738eSCyrill Gorcunov if (!exclude_usr) 217a072738eSCyrill Gorcunov escr |= P4_EVNTSEL_T0_USR; 218a072738eSCyrill Gorcunov } else { 219a072738eSCyrill Gorcunov if (!exclude_os) 220a072738eSCyrill Gorcunov escr |= P4_EVNTSEL_T1_OS; 221a072738eSCyrill Gorcunov if (!exclude_usr) 222a072738eSCyrill Gorcunov escr |= P4_EVNTSEL_T1_USR; 223a072738eSCyrill Gorcunov } 224a072738eSCyrill Gorcunov 225a072738eSCyrill Gorcunov return escr; 226a072738eSCyrill Gorcunov } 227a072738eSCyrill Gorcunov 228a072738eSCyrill Gorcunov /* 229a072738eSCyrill Gorcunov * Comments below the event represent ESCR restriction 230a072738eSCyrill Gorcunov * for this event and counter index per ESCR 231a072738eSCyrill Gorcunov * 232a072738eSCyrill Gorcunov * MSR_P4_IQ_ESCR0 and MSR_P4_IQ_ESCR1 are available only on early 233a072738eSCyrill Gorcunov * processor builds (family 0FH, models 01H-02H). These MSRs 234a072738eSCyrill Gorcunov * are not available on later versions, so that we don't use 235a072738eSCyrill Gorcunov * them completely 236a072738eSCyrill Gorcunov * 237a072738eSCyrill Gorcunov * Also note that CCCR1 do not have P4_CCCR_ENABLE bit properly 238a072738eSCyrill Gorcunov * working so that we should not use this CCCR and respective 239a072738eSCyrill Gorcunov * counter as result 240a072738eSCyrill Gorcunov */ 241a072738eSCyrill Gorcunov #define P4_TC_DELIVER_MODE P4_EVENT_PACK(0x01, 0x01) 242a072738eSCyrill Gorcunov /* 243a072738eSCyrill Gorcunov * MSR_P4_TC_ESCR0: 4, 5 244a072738eSCyrill Gorcunov * MSR_P4_TC_ESCR1: 6, 7 245a072738eSCyrill Gorcunov */ 246a072738eSCyrill Gorcunov 247a072738eSCyrill Gorcunov #define P4_BPU_FETCH_REQUEST P4_EVENT_PACK(0x03, 0x00) 248a072738eSCyrill Gorcunov /* 249a072738eSCyrill Gorcunov * MSR_P4_BPU_ESCR0: 0, 1 250a072738eSCyrill Gorcunov * MSR_P4_BPU_ESCR1: 2, 3 251a072738eSCyrill Gorcunov */ 252a072738eSCyrill Gorcunov 253a072738eSCyrill Gorcunov #define P4_ITLB_REFERENCE P4_EVENT_PACK(0x18, 0x03) 254a072738eSCyrill Gorcunov /* 255a072738eSCyrill Gorcunov * MSR_P4_ITLB_ESCR0: 0, 1 256a072738eSCyrill Gorcunov * MSR_P4_ITLB_ESCR1: 2, 3 257a072738eSCyrill Gorcunov */ 258a072738eSCyrill Gorcunov 259a072738eSCyrill Gorcunov #define P4_MEMORY_CANCEL P4_EVENT_PACK(0x02, 0x05) 260a072738eSCyrill Gorcunov /* 261a072738eSCyrill Gorcunov * MSR_P4_DAC_ESCR0: 8, 9 262a072738eSCyrill Gorcunov * MSR_P4_DAC_ESCR1: 10, 11 263a072738eSCyrill Gorcunov */ 264a072738eSCyrill Gorcunov 265a072738eSCyrill Gorcunov #define P4_MEMORY_COMPLETE P4_EVENT_PACK(0x08, 0x02) 266a072738eSCyrill Gorcunov /* 267a072738eSCyrill Gorcunov * MSR_P4_SAAT_ESCR0: 8, 9 268a072738eSCyrill Gorcunov * MSR_P4_SAAT_ESCR1: 10, 11 269a072738eSCyrill Gorcunov */ 270a072738eSCyrill Gorcunov 271a072738eSCyrill Gorcunov #define P4_LOAD_PORT_REPLAY P4_EVENT_PACK(0x04, 0x02) 272a072738eSCyrill Gorcunov /* 273a072738eSCyrill Gorcunov * MSR_P4_SAAT_ESCR0: 8, 9 274a072738eSCyrill Gorcunov * MSR_P4_SAAT_ESCR1: 10, 11 275a072738eSCyrill Gorcunov */ 276a072738eSCyrill Gorcunov 277a072738eSCyrill Gorcunov #define P4_STORE_PORT_REPLAY P4_EVENT_PACK(0x05, 0x02) 278a072738eSCyrill Gorcunov /* 279a072738eSCyrill Gorcunov * MSR_P4_SAAT_ESCR0: 8, 9 280a072738eSCyrill Gorcunov * MSR_P4_SAAT_ESCR1: 10, 11 281a072738eSCyrill Gorcunov */ 282a072738eSCyrill Gorcunov 283a072738eSCyrill Gorcunov #define P4_MOB_LOAD_REPLAY P4_EVENT_PACK(0x03, 0x02) 284a072738eSCyrill Gorcunov /* 285a072738eSCyrill Gorcunov * MSR_P4_MOB_ESCR0: 0, 1 286a072738eSCyrill Gorcunov * MSR_P4_MOB_ESCR1: 2, 3 287a072738eSCyrill Gorcunov */ 288a072738eSCyrill Gorcunov 289a072738eSCyrill Gorcunov #define P4_PAGE_WALK_TYPE P4_EVENT_PACK(0x01, 0x04) 290a072738eSCyrill Gorcunov /* 291a072738eSCyrill Gorcunov * MSR_P4_PMH_ESCR0: 0, 1 292a072738eSCyrill Gorcunov * MSR_P4_PMH_ESCR1: 2, 3 293a072738eSCyrill Gorcunov */ 294a072738eSCyrill Gorcunov 295a072738eSCyrill Gorcunov #define P4_BSQ_CACHE_REFERENCE P4_EVENT_PACK(0x0c, 0x07) 296a072738eSCyrill Gorcunov /* 297a072738eSCyrill Gorcunov * MSR_P4_BSU_ESCR0: 0, 1 298a072738eSCyrill Gorcunov * MSR_P4_BSU_ESCR1: 2, 3 299a072738eSCyrill Gorcunov */ 300a072738eSCyrill Gorcunov 301a072738eSCyrill Gorcunov #define P4_IOQ_ALLOCATION P4_EVENT_PACK(0x03, 0x06) 302a072738eSCyrill Gorcunov /* 303a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR0: 0, 1 304a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR1: 2, 3 305a072738eSCyrill Gorcunov */ 306a072738eSCyrill Gorcunov 307a072738eSCyrill Gorcunov #define P4_IOQ_ACTIVE_ENTRIES P4_EVENT_PACK(0x1a, 0x06) 308a072738eSCyrill Gorcunov /* 309a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR1: 2, 3 310a072738eSCyrill Gorcunov */ 311a072738eSCyrill Gorcunov 312a072738eSCyrill Gorcunov #define P4_FSB_DATA_ACTIVITY P4_EVENT_PACK(0x17, 0x06) 313a072738eSCyrill Gorcunov /* 314a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR0: 0, 1 315a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR1: 2, 3 316a072738eSCyrill Gorcunov */ 317a072738eSCyrill Gorcunov 318a072738eSCyrill Gorcunov #define P4_BSQ_ALLOCATION P4_EVENT_PACK(0x05, 0x07) 319a072738eSCyrill Gorcunov /* 320a072738eSCyrill Gorcunov * MSR_P4_BSU_ESCR0: 0, 1 321a072738eSCyrill Gorcunov */ 322a072738eSCyrill Gorcunov 323a072738eSCyrill Gorcunov #define P4_BSQ_ACTIVE_ENTRIES P4_EVENT_PACK(0x06, 0x07) 324a072738eSCyrill Gorcunov /* 3258ea7f544SLin Ming * NOTE: no ESCR name in docs, it's guessed 326a072738eSCyrill Gorcunov * MSR_P4_BSU_ESCR1: 2, 3 327a072738eSCyrill Gorcunov */ 328a072738eSCyrill Gorcunov 329a072738eSCyrill Gorcunov #define P4_SSE_INPUT_ASSIST P4_EVENT_PACK(0x34, 0x01) 330a072738eSCyrill Gorcunov /* 331e4495262SCyrill Gorcunov * MSR_P4_FIRM_ESCR0: 8, 9 332e4495262SCyrill Gorcunov * MSR_P4_FIRM_ESCR1: 10, 11 333a072738eSCyrill Gorcunov */ 334a072738eSCyrill Gorcunov 335a072738eSCyrill Gorcunov #define P4_PACKED_SP_UOP P4_EVENT_PACK(0x08, 0x01) 336a072738eSCyrill Gorcunov /* 337a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR0: 8, 9 338a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR1: 10, 11 339a072738eSCyrill Gorcunov */ 340a072738eSCyrill Gorcunov 341a072738eSCyrill Gorcunov #define P4_PACKED_DP_UOP P4_EVENT_PACK(0x0c, 0x01) 342a072738eSCyrill Gorcunov /* 343a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR0: 8, 9 344a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR1: 10, 11 345a072738eSCyrill Gorcunov */ 346a072738eSCyrill Gorcunov 347a072738eSCyrill Gorcunov #define P4_SCALAR_SP_UOP P4_EVENT_PACK(0x0a, 0x01) 348a072738eSCyrill Gorcunov /* 349a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR0: 8, 9 350a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR1: 10, 11 351a072738eSCyrill Gorcunov */ 352a072738eSCyrill Gorcunov 353a072738eSCyrill Gorcunov #define P4_SCALAR_DP_UOP P4_EVENT_PACK(0x0e, 0x01) 354a072738eSCyrill Gorcunov /* 355a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR0: 8, 9 356a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR1: 10, 11 357a072738eSCyrill Gorcunov */ 358a072738eSCyrill Gorcunov 359a072738eSCyrill Gorcunov #define P4_64BIT_MMX_UOP P4_EVENT_PACK(0x02, 0x01) 360a072738eSCyrill Gorcunov /* 361a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR0: 8, 9 362a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR1: 10, 11 363a072738eSCyrill Gorcunov */ 364a072738eSCyrill Gorcunov 365a072738eSCyrill Gorcunov #define P4_128BIT_MMX_UOP P4_EVENT_PACK(0x1a, 0x01) 366a072738eSCyrill Gorcunov /* 367a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR0: 8, 9 368a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR1: 10, 11 369a072738eSCyrill Gorcunov */ 370a072738eSCyrill Gorcunov 371a072738eSCyrill Gorcunov #define P4_X87_FP_UOP P4_EVENT_PACK(0x04, 0x01) 372a072738eSCyrill Gorcunov /* 373a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR0: 8, 9 374a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR1: 10, 11 375a072738eSCyrill Gorcunov */ 376a072738eSCyrill Gorcunov 377a072738eSCyrill Gorcunov #define P4_TC_MISC P4_EVENT_PACK(0x06, 0x01) 378a072738eSCyrill Gorcunov /* 379a072738eSCyrill Gorcunov * MSR_P4_TC_ESCR0: 4, 5 380a072738eSCyrill Gorcunov * MSR_P4_TC_ESCR1: 6, 7 381a072738eSCyrill Gorcunov */ 382a072738eSCyrill Gorcunov 383a072738eSCyrill Gorcunov #define P4_GLOBAL_POWER_EVENTS P4_EVENT_PACK(0x13, 0x06) 384a072738eSCyrill Gorcunov /* 385a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR0: 0, 1 386a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR1: 2, 3 387a072738eSCyrill Gorcunov */ 388a072738eSCyrill Gorcunov 389a072738eSCyrill Gorcunov #define P4_TC_MS_XFER P4_EVENT_PACK(0x05, 0x00) 390a072738eSCyrill Gorcunov /* 391a072738eSCyrill Gorcunov * MSR_P4_MS_ESCR0: 4, 5 392a072738eSCyrill Gorcunov * MSR_P4_MS_ESCR1: 6, 7 393a072738eSCyrill Gorcunov */ 394a072738eSCyrill Gorcunov 395a072738eSCyrill Gorcunov #define P4_UOP_QUEUE_WRITES P4_EVENT_PACK(0x09, 0x00) 396a072738eSCyrill Gorcunov /* 397a072738eSCyrill Gorcunov * MSR_P4_MS_ESCR0: 4, 5 398a072738eSCyrill Gorcunov * MSR_P4_MS_ESCR1: 6, 7 399a072738eSCyrill Gorcunov */ 400a072738eSCyrill Gorcunov 401a072738eSCyrill Gorcunov #define P4_RETIRED_MISPRED_BRANCH_TYPE P4_EVENT_PACK(0x05, 0x02) 402a072738eSCyrill Gorcunov /* 403a072738eSCyrill Gorcunov * MSR_P4_TBPU_ESCR0: 4, 5 404a072738eSCyrill Gorcunov * MSR_P4_TBPU_ESCR0: 6, 7 405a072738eSCyrill Gorcunov */ 406a072738eSCyrill Gorcunov 407a072738eSCyrill Gorcunov #define P4_RETIRED_BRANCH_TYPE P4_EVENT_PACK(0x04, 0x02) 408a072738eSCyrill Gorcunov /* 409a072738eSCyrill Gorcunov * MSR_P4_TBPU_ESCR0: 4, 5 410a072738eSCyrill Gorcunov * MSR_P4_TBPU_ESCR0: 6, 7 411a072738eSCyrill Gorcunov */ 412a072738eSCyrill Gorcunov 413a072738eSCyrill Gorcunov #define P4_RESOURCE_STALL P4_EVENT_PACK(0x01, 0x01) 414a072738eSCyrill Gorcunov /* 415a072738eSCyrill Gorcunov * MSR_P4_ALF_ESCR0: 12, 13, 16 416a072738eSCyrill Gorcunov * MSR_P4_ALF_ESCR1: 14, 15, 17 417a072738eSCyrill Gorcunov */ 418a072738eSCyrill Gorcunov 419a072738eSCyrill Gorcunov #define P4_WC_BUFFER P4_EVENT_PACK(0x05, 0x05) 420a072738eSCyrill Gorcunov /* 421a072738eSCyrill Gorcunov * MSR_P4_DAC_ESCR0: 8, 9 422a072738eSCyrill Gorcunov * MSR_P4_DAC_ESCR1: 10, 11 423a072738eSCyrill Gorcunov */ 424a072738eSCyrill Gorcunov 425a072738eSCyrill Gorcunov #define P4_B2B_CYCLES P4_EVENT_PACK(0x16, 0x03) 426a072738eSCyrill Gorcunov /* 427a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR0: 0, 1 428a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR1: 2, 3 429a072738eSCyrill Gorcunov */ 430a072738eSCyrill Gorcunov 431a072738eSCyrill Gorcunov #define P4_BNR P4_EVENT_PACK(0x08, 0x03) 432a072738eSCyrill Gorcunov /* 433a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR0: 0, 1 434a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR1: 2, 3 435a072738eSCyrill Gorcunov */ 436a072738eSCyrill Gorcunov 437a072738eSCyrill Gorcunov #define P4_SNOOP P4_EVENT_PACK(0x06, 0x03) 438a072738eSCyrill Gorcunov /* 439a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR0: 0, 1 440a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR1: 2, 3 441a072738eSCyrill Gorcunov */ 442a072738eSCyrill Gorcunov 443a072738eSCyrill Gorcunov #define P4_RESPONSE P4_EVENT_PACK(0x04, 0x03) 444a072738eSCyrill Gorcunov /* 445a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR0: 0, 1 446a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR1: 2, 3 447a072738eSCyrill Gorcunov */ 448a072738eSCyrill Gorcunov 449a072738eSCyrill Gorcunov #define P4_FRONT_END_EVENT P4_EVENT_PACK(0x08, 0x05) 450a072738eSCyrill Gorcunov /* 451a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR2: 12, 13, 16 452a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR3: 14, 15, 17 453a072738eSCyrill Gorcunov */ 454a072738eSCyrill Gorcunov 455a072738eSCyrill Gorcunov #define P4_EXECUTION_EVENT P4_EVENT_PACK(0x0c, 0x05) 456a072738eSCyrill Gorcunov /* 457a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR2: 12, 13, 16 458a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR3: 14, 15, 17 459a072738eSCyrill Gorcunov */ 460a072738eSCyrill Gorcunov 461a072738eSCyrill Gorcunov #define P4_REPLAY_EVENT P4_EVENT_PACK(0x09, 0x05) 462a072738eSCyrill Gorcunov /* 463a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR2: 12, 13, 16 464a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR3: 14, 15, 17 465a072738eSCyrill Gorcunov */ 466a072738eSCyrill Gorcunov 467a072738eSCyrill Gorcunov #define P4_INSTR_RETIRED P4_EVENT_PACK(0x02, 0x04) 468a072738eSCyrill Gorcunov /* 469e4495262SCyrill Gorcunov * MSR_P4_CRU_ESCR0: 12, 13, 16 470e4495262SCyrill Gorcunov * MSR_P4_CRU_ESCR1: 14, 15, 17 471a072738eSCyrill Gorcunov */ 472a072738eSCyrill Gorcunov 473a072738eSCyrill Gorcunov #define P4_UOPS_RETIRED P4_EVENT_PACK(0x01, 0x04) 474a072738eSCyrill Gorcunov /* 4758ea7f544SLin Ming * MSR_P4_CRU_ESCR0: 12, 13, 16 4768ea7f544SLin Ming * MSR_P4_CRU_ESCR1: 14, 15, 17 477a072738eSCyrill Gorcunov */ 478a072738eSCyrill Gorcunov 479a072738eSCyrill Gorcunov #define P4_UOP_TYPE P4_EVENT_PACK(0x02, 0x02) 480a072738eSCyrill Gorcunov /* 481a072738eSCyrill Gorcunov * MSR_P4_RAT_ESCR0: 12, 13, 16 482a072738eSCyrill Gorcunov * MSR_P4_RAT_ESCR1: 14, 15, 17 483a072738eSCyrill Gorcunov */ 484a072738eSCyrill Gorcunov 485a072738eSCyrill Gorcunov #define P4_BRANCH_RETIRED P4_EVENT_PACK(0x06, 0x05) 486a072738eSCyrill Gorcunov /* 487a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR2: 12, 13, 16 488a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR3: 14, 15, 17 489a072738eSCyrill Gorcunov */ 490a072738eSCyrill Gorcunov 491a072738eSCyrill Gorcunov #define P4_MISPRED_BRANCH_RETIRED P4_EVENT_PACK(0x03, 0x04) 492a072738eSCyrill Gorcunov /* 493a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR0: 12, 13, 16 494a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR1: 14, 15, 17 495a072738eSCyrill Gorcunov */ 496a072738eSCyrill Gorcunov 497a072738eSCyrill Gorcunov #define P4_X87_ASSIST P4_EVENT_PACK(0x03, 0x05) 498a072738eSCyrill Gorcunov /* 499a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR2: 12, 13, 16 500a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR3: 14, 15, 17 501a072738eSCyrill Gorcunov */ 502a072738eSCyrill Gorcunov 503a072738eSCyrill Gorcunov #define P4_MACHINE_CLEAR P4_EVENT_PACK(0x02, 0x05) 504a072738eSCyrill Gorcunov /* 505a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR2: 12, 13, 16 506a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR3: 14, 15, 17 507a072738eSCyrill Gorcunov */ 508a072738eSCyrill Gorcunov 509a072738eSCyrill Gorcunov #define P4_INSTR_COMPLETED P4_EVENT_PACK(0x07, 0x04) 510a072738eSCyrill Gorcunov /* 511a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR0: 12, 13, 16 512a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR1: 14, 15, 17 513a072738eSCyrill Gorcunov */ 514a072738eSCyrill Gorcunov 515a072738eSCyrill Gorcunov /* 516a072738eSCyrill Gorcunov * a caller should use P4_EVENT_ATTR helper to 517a072738eSCyrill Gorcunov * pick the attribute needed, for example 518a072738eSCyrill Gorcunov * 519a072738eSCyrill Gorcunov * P4_EVENT_ATTR(P4_TC_DELIVER_MODE, DD) 520a072738eSCyrill Gorcunov */ 521a072738eSCyrill Gorcunov enum P4_EVENTS_ATTR { 522a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_TC_DELIVER_MODE, DD, 0), 523a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_TC_DELIVER_MODE, DB, 1), 524a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_TC_DELIVER_MODE, DI, 2), 525a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_TC_DELIVER_MODE, BD, 3), 526a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_TC_DELIVER_MODE, BB, 4), 527a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_TC_DELIVER_MODE, BI, 5), 528a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_TC_DELIVER_MODE, ID, 6), 529a072738eSCyrill Gorcunov 530a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_BPU_FETCH_REQUEST, TCMISS, 0), 531a072738eSCyrill Gorcunov 532a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_ITLB_REFERENCE, HIT, 0), 533a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_ITLB_REFERENCE, MISS, 1), 534a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_ITLB_REFERENCE, HIT_UK, 2), 535a072738eSCyrill Gorcunov 536a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_MEMORY_CANCEL, ST_RB_FULL, 2), 537a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_MEMORY_CANCEL, 64K_CONF, 3), 538a072738eSCyrill Gorcunov 539a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_MEMORY_COMPLETE, LSC, 0), 540a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_MEMORY_COMPLETE, SSC, 1), 541a072738eSCyrill Gorcunov 542a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_LOAD_PORT_REPLAY, SPLIT_LD, 1), 543a072738eSCyrill Gorcunov 544a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_STORE_PORT_REPLAY, SPLIT_ST, 1), 545a072738eSCyrill Gorcunov 546a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_MOB_LOAD_REPLAY, NO_STA, 1), 547a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_MOB_LOAD_REPLAY, NO_STD, 3), 548a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_MOB_LOAD_REPLAY, PARTIAL_DATA, 4), 549a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_MOB_LOAD_REPLAY, UNALGN_ADDR, 5), 550a072738eSCyrill Gorcunov 551a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_PAGE_WALK_TYPE, DTMISS, 0), 552a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_PAGE_WALK_TYPE, ITMISS, 1), 553a072738eSCyrill Gorcunov 554a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_BSQ_CACHE_REFERENCE, RD_2ndL_HITS, 0), 555a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_BSQ_CACHE_REFERENCE, RD_2ndL_HITE, 1), 556a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_BSQ_CACHE_REFERENCE, RD_2ndL_HITM, 2), 557a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_BSQ_CACHE_REFERENCE, RD_3rdL_HITS, 3), 558a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_BSQ_CACHE_REFERENCE, RD_3rdL_HITE, 4), 559a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_BSQ_CACHE_REFERENCE, RD_3rdL_HITM, 5), 560a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_BSQ_CACHE_REFERENCE, RD_2ndL_MISS, 8), 561a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_BSQ_CACHE_REFERENCE, RD_3rdL_MISS, 9), 562a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_BSQ_CACHE_REFERENCE, WR_2ndL_MISS, 10), 563a072738eSCyrill Gorcunov 564a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_IOQ_ALLOCATION, DEFAULT, 0), 565a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_IOQ_ALLOCATION, ALL_READ, 5), 566a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_IOQ_ALLOCATION, ALL_WRITE, 6), 567a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_IOQ_ALLOCATION, MEM_UC, 7), 568a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_IOQ_ALLOCATION, MEM_WC, 8), 569a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_IOQ_ALLOCATION, MEM_WT, 9), 570a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_IOQ_ALLOCATION, MEM_WP, 10), 571a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_IOQ_ALLOCATION, MEM_WB, 11), 572a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_IOQ_ALLOCATION, OWN, 13), 573a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_IOQ_ALLOCATION, OTHER, 14), 574a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_IOQ_ALLOCATION, PREFETCH, 15), 575a072738eSCyrill Gorcunov 576a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_IOQ_ACTIVE_ENTRIES, DEFAULT, 0), 577a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_IOQ_ACTIVE_ENTRIES, ALL_READ, 5), 578a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_IOQ_ACTIVE_ENTRIES, ALL_WRITE, 6), 579a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_IOQ_ACTIVE_ENTRIES, MEM_UC, 7), 580a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_IOQ_ACTIVE_ENTRIES, MEM_WC, 8), 581a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_IOQ_ACTIVE_ENTRIES, MEM_WT, 9), 582a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_IOQ_ACTIVE_ENTRIES, MEM_WP, 10), 583a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_IOQ_ACTIVE_ENTRIES, MEM_WB, 11), 584a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_IOQ_ACTIVE_ENTRIES, OWN, 13), 585a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_IOQ_ACTIVE_ENTRIES, OTHER, 14), 586a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_IOQ_ACTIVE_ENTRIES, PREFETCH, 15), 587a072738eSCyrill Gorcunov 588a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_FSB_DATA_ACTIVITY, DRDY_DRV, 0), 589a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_FSB_DATA_ACTIVITY, DRDY_OWN, 1), 590a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_FSB_DATA_ACTIVITY, DRDY_OTHER, 2), 591a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_FSB_DATA_ACTIVITY, DBSY_DRV, 3), 592a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_FSB_DATA_ACTIVITY, DBSY_OWN, 4), 593a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_FSB_DATA_ACTIVITY, DBSY_OTHER, 5), 594a072738eSCyrill Gorcunov 595a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_BSQ_ALLOCATION, REQ_TYPE0, 0), 596a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_BSQ_ALLOCATION, REQ_TYPE1, 1), 597a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_BSQ_ALLOCATION, REQ_LEN0, 2), 598a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_BSQ_ALLOCATION, REQ_LEN1, 3), 599a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_BSQ_ALLOCATION, REQ_IO_TYPE, 5), 600a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_BSQ_ALLOCATION, REQ_LOCK_TYPE, 6), 601a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_BSQ_ALLOCATION, REQ_CACHE_TYPE, 7), 602a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_BSQ_ALLOCATION, REQ_SPLIT_TYPE, 8), 603a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_BSQ_ALLOCATION, REQ_DEM_TYPE, 9), 604a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_BSQ_ALLOCATION, REQ_ORD_TYPE, 10), 605a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_BSQ_ALLOCATION, MEM_TYPE0, 11), 606a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_BSQ_ALLOCATION, MEM_TYPE1, 12), 607a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_BSQ_ALLOCATION, MEM_TYPE2, 13), 608a072738eSCyrill Gorcunov 609a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_BSQ_ACTIVE_ENTRIES, REQ_TYPE0, 0), 610a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_BSQ_ACTIVE_ENTRIES, REQ_TYPE1, 1), 611a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_BSQ_ACTIVE_ENTRIES, REQ_LEN0, 2), 612a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_BSQ_ACTIVE_ENTRIES, REQ_LEN1, 3), 613a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_BSQ_ACTIVE_ENTRIES, REQ_IO_TYPE, 5), 614a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_BSQ_ACTIVE_ENTRIES, REQ_LOCK_TYPE, 6), 615a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_BSQ_ACTIVE_ENTRIES, REQ_CACHE_TYPE, 7), 616a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_BSQ_ACTIVE_ENTRIES, REQ_SPLIT_TYPE, 8), 617a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_BSQ_ACTIVE_ENTRIES, REQ_DEM_TYPE, 9), 618a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_BSQ_ACTIVE_ENTRIES, REQ_ORD_TYPE, 10), 619a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_BSQ_ACTIVE_ENTRIES, MEM_TYPE0, 11), 620a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_BSQ_ACTIVE_ENTRIES, MEM_TYPE1, 12), 621a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_BSQ_ACTIVE_ENTRIES, MEM_TYPE2, 13), 622a072738eSCyrill Gorcunov 623a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_SSE_INPUT_ASSIST, ALL, 15), 624a072738eSCyrill Gorcunov 625a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_PACKED_SP_UOP, ALL, 15), 626a072738eSCyrill Gorcunov 627a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_PACKED_DP_UOP, ALL, 15), 628a072738eSCyrill Gorcunov 629a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_SCALAR_SP_UOP, ALL, 15), 630a072738eSCyrill Gorcunov 631a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_SCALAR_DP_UOP, ALL, 15), 632a072738eSCyrill Gorcunov 633a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_64BIT_MMX_UOP, ALL, 15), 634a072738eSCyrill Gorcunov 635a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_128BIT_MMX_UOP, ALL, 15), 636a072738eSCyrill Gorcunov 637a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_X87_FP_UOP, ALL, 15), 638a072738eSCyrill Gorcunov 639a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_TC_MISC, FLUSH, 4), 640a072738eSCyrill Gorcunov 641a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_GLOBAL_POWER_EVENTS, RUNNING, 0), 642a072738eSCyrill Gorcunov 643a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_TC_MS_XFER, CISC, 0), 644a072738eSCyrill Gorcunov 645a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_UOP_QUEUE_WRITES, FROM_TC_BUILD, 0), 646a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_UOP_QUEUE_WRITES, FROM_TC_DELIVER, 1), 647a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_UOP_QUEUE_WRITES, FROM_ROM, 2), 648a072738eSCyrill Gorcunov 649a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_RETIRED_MISPRED_BRANCH_TYPE, CONDITIONAL, 1), 650a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_RETIRED_MISPRED_BRANCH_TYPE, CALL, 2), 651a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_RETIRED_MISPRED_BRANCH_TYPE, RETURN, 3), 652a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_RETIRED_MISPRED_BRANCH_TYPE, INDIRECT, 4), 653a072738eSCyrill Gorcunov 654a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_RETIRED_BRANCH_TYPE, CONDITIONAL, 1), 655a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_RETIRED_BRANCH_TYPE, CALL, 2), 656a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_RETIRED_BRANCH_TYPE, RETURN, 3), 657a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_RETIRED_BRANCH_TYPE, INDIRECT, 4), 658a072738eSCyrill Gorcunov 659a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_RESOURCE_STALL, SBFULL, 5), 660a072738eSCyrill Gorcunov 661a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_WC_BUFFER, WCB_EVICTS, 0), 662a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_WC_BUFFER, WCB_FULL_EVICTS, 1), 663a072738eSCyrill Gorcunov 664a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_FRONT_END_EVENT, NBOGUS, 0), 665a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_FRONT_END_EVENT, BOGUS, 1), 666a072738eSCyrill Gorcunov 667a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_EXECUTION_EVENT, NBOGUS0, 0), 668a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_EXECUTION_EVENT, NBOGUS1, 1), 669a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_EXECUTION_EVENT, NBOGUS2, 2), 670a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_EXECUTION_EVENT, NBOGUS3, 3), 671a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_EXECUTION_EVENT, BOGUS0, 4), 672a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_EXECUTION_EVENT, BOGUS1, 5), 673a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_EXECUTION_EVENT, BOGUS2, 6), 674a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_EXECUTION_EVENT, BOGUS3, 7), 675a072738eSCyrill Gorcunov 676a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_REPLAY_EVENT, NBOGUS, 0), 677a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_REPLAY_EVENT, BOGUS, 1), 678a072738eSCyrill Gorcunov 679a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_INSTR_RETIRED, NBOGUSNTAG, 0), 680a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_INSTR_RETIRED, NBOGUSTAG, 1), 681a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_INSTR_RETIRED, BOGUSNTAG, 2), 682a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_INSTR_RETIRED, BOGUSTAG, 3), 683a072738eSCyrill Gorcunov 684a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_UOPS_RETIRED, NBOGUS, 0), 685a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_UOPS_RETIRED, BOGUS, 1), 686a072738eSCyrill Gorcunov 687a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_UOP_TYPE, TAGLOADS, 1), 688a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_UOP_TYPE, TAGSTORES, 2), 689a072738eSCyrill Gorcunov 690a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_BRANCH_RETIRED, MMNP, 0), 691a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_BRANCH_RETIRED, MMNM, 1), 692a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_BRANCH_RETIRED, MMTP, 2), 693a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_BRANCH_RETIRED, MMTM, 3), 694a072738eSCyrill Gorcunov 695a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_MISPRED_BRANCH_RETIRED, NBOGUS, 0), 696a072738eSCyrill Gorcunov 697a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_X87_ASSIST, FPSU, 0), 698a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_X87_ASSIST, FPSO, 1), 699a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_X87_ASSIST, POAO, 2), 700a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_X87_ASSIST, POAU, 3), 701a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_X87_ASSIST, PREA, 4), 702a072738eSCyrill Gorcunov 703a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_MACHINE_CLEAR, CLEAR, 0), 704a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_MACHINE_CLEAR, MOCLEAR, 1), 705a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_MACHINE_CLEAR, SMCLEAR, 2), 706a072738eSCyrill Gorcunov 707a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_INSTR_COMPLETED, NBOGUS, 0), 708a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_INSTR_COMPLETED, BOGUS, 1), 709a072738eSCyrill Gorcunov }; 710a072738eSCyrill Gorcunov 711*cb7d6b50SLin Ming enum { 712*cb7d6b50SLin Ming KEY_P4_L1D_OP_READ_RESULT_MISS, 713*cb7d6b50SLin Ming KEY_P4_LL_OP_READ_RESULT_MISS, 714*cb7d6b50SLin Ming KEY_P4_DTLB_OP_READ_RESULT_MISS, 715*cb7d6b50SLin Ming KEY_P4_DTLB_OP_WRITE_RESULT_MISS, 716*cb7d6b50SLin Ming KEY_P4_ITLB_OP_READ_RESULT_ACCESS, 717*cb7d6b50SLin Ming KEY_P4_ITLB_OP_READ_RESULT_MISS, 718*cb7d6b50SLin Ming KEY_P4_UOP_TYPE, 719*cb7d6b50SLin Ming }; 720*cb7d6b50SLin Ming 721a072738eSCyrill Gorcunov #endif /* PERF_EVENT_P4_H */ 722