1a072738eSCyrill Gorcunov /* 2a072738eSCyrill Gorcunov * Netburst Perfomance Events (P4, old Xeon) 3a072738eSCyrill Gorcunov */ 4a072738eSCyrill Gorcunov 5a072738eSCyrill Gorcunov #ifndef PERF_EVENT_P4_H 6a072738eSCyrill Gorcunov #define PERF_EVENT_P4_H 7a072738eSCyrill Gorcunov 8a072738eSCyrill Gorcunov #include <linux/cpu.h> 9a072738eSCyrill Gorcunov #include <linux/bitops.h> 10a072738eSCyrill Gorcunov 11a072738eSCyrill Gorcunov /* 12a072738eSCyrill Gorcunov * NetBurst has perfomance MSRs shared between 13a072738eSCyrill Gorcunov * threads if HT is turned on, ie for both logical 14a072738eSCyrill Gorcunov * processors (mem: in turn in Atom with HT support 15a072738eSCyrill Gorcunov * perf-MSRs are not shared and every thread has its 16a072738eSCyrill Gorcunov * own perf-MSRs set) 17a072738eSCyrill Gorcunov */ 18a072738eSCyrill Gorcunov #define ARCH_P4_TOTAL_ESCR (46) 19a072738eSCyrill Gorcunov #define ARCH_P4_RESERVED_ESCR (2) /* IQ_ESCR(0,1) not always present */ 20a072738eSCyrill Gorcunov #define ARCH_P4_MAX_ESCR (ARCH_P4_TOTAL_ESCR - ARCH_P4_RESERVED_ESCR) 21a072738eSCyrill Gorcunov #define ARCH_P4_MAX_CCCR (18) 22a072738eSCyrill Gorcunov 23d814f301SCyrill Gorcunov #define P4_ESCR_EVENT_MASK 0x7e000000U 24d814f301SCyrill Gorcunov #define P4_ESCR_EVENT_SHIFT 25 25d814f301SCyrill Gorcunov #define P4_ESCR_EVENTMASK_MASK 0x01fffe00U 26d814f301SCyrill Gorcunov #define P4_ESCR_EVENTMASK_SHIFT 9 27d814f301SCyrill Gorcunov #define P4_ESCR_TAG_MASK 0x000001e0U 28d814f301SCyrill Gorcunov #define P4_ESCR_TAG_SHIFT 5 29d814f301SCyrill Gorcunov #define P4_ESCR_TAG_ENABLE 0x00000010U 30d814f301SCyrill Gorcunov #define P4_ESCR_T0_OS 0x00000008U 31d814f301SCyrill Gorcunov #define P4_ESCR_T0_USR 0x00000004U 32d814f301SCyrill Gorcunov #define P4_ESCR_T1_OS 0x00000002U 33d814f301SCyrill Gorcunov #define P4_ESCR_T1_USR 0x00000001U 34d814f301SCyrill Gorcunov 35d814f301SCyrill Gorcunov #define P4_ESCR_EVENT(v) ((v) << P4_ESCR_EVENT_SHIFT) 36d814f301SCyrill Gorcunov #define P4_ESCR_EMASK(v) ((v) << P4_ESCR_EVENTMASK_SHIFT) 37d814f301SCyrill Gorcunov #define P4_ESCR_TAG(v) ((v) << P4_ESCR_TAG_SHIFT) 38a072738eSCyrill Gorcunov 39a072738eSCyrill Gorcunov #define P4_CCCR_OVF 0x80000000U 40a072738eSCyrill Gorcunov #define P4_CCCR_CASCADE 0x40000000U 41a072738eSCyrill Gorcunov #define P4_CCCR_OVF_PMI_T0 0x04000000U 42a072738eSCyrill Gorcunov #define P4_CCCR_OVF_PMI_T1 0x08000000U 43a072738eSCyrill Gorcunov #define P4_CCCR_FORCE_OVF 0x02000000U 44a072738eSCyrill Gorcunov #define P4_CCCR_EDGE 0x01000000U 45a072738eSCyrill Gorcunov #define P4_CCCR_THRESHOLD_MASK 0x00f00000U 46a072738eSCyrill Gorcunov #define P4_CCCR_THRESHOLD_SHIFT 20 47a072738eSCyrill Gorcunov #define P4_CCCR_COMPLEMENT 0x00080000U 48a072738eSCyrill Gorcunov #define P4_CCCR_COMPARE 0x00040000U 49a072738eSCyrill Gorcunov #define P4_CCCR_ESCR_SELECT_MASK 0x0000e000U 50a072738eSCyrill Gorcunov #define P4_CCCR_ESCR_SELECT_SHIFT 13 51a072738eSCyrill Gorcunov #define P4_CCCR_ENABLE 0x00001000U 52a072738eSCyrill Gorcunov #define P4_CCCR_THREAD_SINGLE 0x00010000U 53a072738eSCyrill Gorcunov #define P4_CCCR_THREAD_BOTH 0x00020000U 54a072738eSCyrill Gorcunov #define P4_CCCR_THREAD_ANY 0x00030000U 55f34edbc1SLin Ming #define P4_CCCR_RESERVED 0x00000fffU 56a072738eSCyrill Gorcunov 57d814f301SCyrill Gorcunov #define P4_CCCR_THRESHOLD(v) ((v) << P4_CCCR_THRESHOLD_SHIFT) 58d814f301SCyrill Gorcunov #define P4_CCCR_ESEL(v) ((v) << P4_CCCR_ESCR_SELECT_SHIFT) 59d814f301SCyrill Gorcunov 60d814f301SCyrill Gorcunov #define P4_GEN_ESCR_EMASK(class, name, bit) \ 61d814f301SCyrill Gorcunov class##__##name = ((1 << bit) << P4_ESCR_EVENTMASK_SHIFT) 62d814f301SCyrill Gorcunov #define P4_ESCR_EMASK_BIT(class, name) class##__##name 63a072738eSCyrill Gorcunov 64a072738eSCyrill Gorcunov /* 65a072738eSCyrill Gorcunov * config field is 64bit width and consists of 66a072738eSCyrill Gorcunov * HT << 63 | ESCR << 32 | CCCR 67a072738eSCyrill Gorcunov * where HT is HyperThreading bit (since ESCR 68a072738eSCyrill Gorcunov * has it reserved we may use it for own purpose) 69a072738eSCyrill Gorcunov * 70a072738eSCyrill Gorcunov * note that this is NOT the addresses of respective 71a072738eSCyrill Gorcunov * ESCR and CCCR but rather an only packed value should 72a072738eSCyrill Gorcunov * be unpacked and written to a proper addresses 73a072738eSCyrill Gorcunov * 7439ef13a4SCyrill Gorcunov * the base idea is to pack as much info as possible 75a072738eSCyrill Gorcunov */ 76a072738eSCyrill Gorcunov #define p4_config_pack_escr(v) (((u64)(v)) << 32) 77a072738eSCyrill Gorcunov #define p4_config_pack_cccr(v) (((u64)(v)) & 0xffffffffULL) 78a072738eSCyrill Gorcunov #define p4_config_unpack_escr(v) (((u64)(v)) >> 32) 79d814f301SCyrill Gorcunov #define p4_config_unpack_cccr(v) (((u64)(v)) & 0xffffffffULL) 80a072738eSCyrill Gorcunov 81a072738eSCyrill Gorcunov #define p4_config_unpack_emask(v) \ 82a072738eSCyrill Gorcunov ({ \ 83a072738eSCyrill Gorcunov u32 t = p4_config_unpack_escr((v)); \ 84d814f301SCyrill Gorcunov t = t & P4_ESCR_EVENTMASK_MASK; \ 85d814f301SCyrill Gorcunov t = t >> P4_ESCR_EVENTMASK_SHIFT; \ 86a072738eSCyrill Gorcunov t; \ 87a072738eSCyrill Gorcunov }) 88a072738eSCyrill Gorcunov 89d814f301SCyrill Gorcunov #define p4_config_unpack_event(v) \ 90d814f301SCyrill Gorcunov ({ \ 91d814f301SCyrill Gorcunov u32 t = p4_config_unpack_escr((v)); \ 92d814f301SCyrill Gorcunov t = t & P4_ESCR_EVENT_MASK; \ 93d814f301SCyrill Gorcunov t = t >> P4_ESCR_EVENT_SHIFT; \ 94d814f301SCyrill Gorcunov t; \ 95d814f301SCyrill Gorcunov }) 96d814f301SCyrill Gorcunov 97a072738eSCyrill Gorcunov #define P4_CONFIG_HT_SHIFT 63 98a072738eSCyrill Gorcunov #define P4_CONFIG_HT (1ULL << P4_CONFIG_HT_SHIFT) 99a072738eSCyrill Gorcunov 100c9cf4a01SCyrill Gorcunov /* 101c9cf4a01SCyrill Gorcunov * The bits we allow to pass for RAW events 102c9cf4a01SCyrill Gorcunov */ 103c9cf4a01SCyrill Gorcunov #define P4_CONFIG_MASK_ESCR \ 104c9cf4a01SCyrill Gorcunov P4_ESCR_EVENT_MASK | \ 105c9cf4a01SCyrill Gorcunov P4_ESCR_EVENTMASK_MASK | \ 106c9cf4a01SCyrill Gorcunov P4_ESCR_TAG_MASK | \ 107c9cf4a01SCyrill Gorcunov P4_ESCR_TAG_ENABLE 108c9cf4a01SCyrill Gorcunov 109c9cf4a01SCyrill Gorcunov #define P4_CONFIG_MASK_CCCR \ 110c9cf4a01SCyrill Gorcunov P4_CCCR_EDGE | \ 111c9cf4a01SCyrill Gorcunov P4_CCCR_THRESHOLD_MASK | \ 112c9cf4a01SCyrill Gorcunov P4_CCCR_COMPLEMENT | \ 113c9cf4a01SCyrill Gorcunov P4_CCCR_COMPARE | \ 114c9cf4a01SCyrill Gorcunov P4_CCCR_THREAD_ANY | \ 115c9cf4a01SCyrill Gorcunov P4_CCCR_RESERVED 116c9cf4a01SCyrill Gorcunov 117c9cf4a01SCyrill Gorcunov /* some dangerous bits are reserved for kernel internals */ 118c9cf4a01SCyrill Gorcunov #define P4_CONFIG_MASK \ 119c9cf4a01SCyrill Gorcunov (p4_config_pack_escr(P4_CONFIG_MASK_ESCR)) | \ 120c9cf4a01SCyrill Gorcunov (p4_config_pack_cccr(P4_CONFIG_MASK_CCCR)) 121c9cf4a01SCyrill Gorcunov 122a072738eSCyrill Gorcunov static inline bool p4_is_event_cascaded(u64 config) 123a072738eSCyrill Gorcunov { 124a072738eSCyrill Gorcunov u32 cccr = p4_config_unpack_cccr(config); 125a072738eSCyrill Gorcunov return !!(cccr & P4_CCCR_CASCADE); 126a072738eSCyrill Gorcunov } 127a072738eSCyrill Gorcunov 128a072738eSCyrill Gorcunov static inline int p4_ht_config_thread(u64 config) 129a072738eSCyrill Gorcunov { 130a072738eSCyrill Gorcunov return !!(config & P4_CONFIG_HT); 131a072738eSCyrill Gorcunov } 132a072738eSCyrill Gorcunov 133a072738eSCyrill Gorcunov static inline u64 p4_set_ht_bit(u64 config) 134a072738eSCyrill Gorcunov { 135a072738eSCyrill Gorcunov return config | P4_CONFIG_HT; 136a072738eSCyrill Gorcunov } 137a072738eSCyrill Gorcunov 138a072738eSCyrill Gorcunov static inline u64 p4_clear_ht_bit(u64 config) 139a072738eSCyrill Gorcunov { 140a072738eSCyrill Gorcunov return config & ~P4_CONFIG_HT; 141a072738eSCyrill Gorcunov } 142a072738eSCyrill Gorcunov 143a072738eSCyrill Gorcunov static inline int p4_ht_active(void) 144a072738eSCyrill Gorcunov { 145a072738eSCyrill Gorcunov #ifdef CONFIG_SMP 146a072738eSCyrill Gorcunov return smp_num_siblings > 1; 147a072738eSCyrill Gorcunov #endif 148a072738eSCyrill Gorcunov return 0; 149a072738eSCyrill Gorcunov } 150a072738eSCyrill Gorcunov 151a072738eSCyrill Gorcunov static inline int p4_ht_thread(int cpu) 152a072738eSCyrill Gorcunov { 153a072738eSCyrill Gorcunov #ifdef CONFIG_SMP 154a072738eSCyrill Gorcunov if (smp_num_siblings == 2) 155a072738eSCyrill Gorcunov return cpu != cpumask_first(__get_cpu_var(cpu_sibling_map)); 156a072738eSCyrill Gorcunov #endif 157a072738eSCyrill Gorcunov return 0; 158a072738eSCyrill Gorcunov } 159a072738eSCyrill Gorcunov 160a072738eSCyrill Gorcunov static inline int p4_should_swap_ts(u64 config, int cpu) 161a072738eSCyrill Gorcunov { 162a072738eSCyrill Gorcunov return p4_ht_config_thread(config) ^ p4_ht_thread(cpu); 163a072738eSCyrill Gorcunov } 164a072738eSCyrill Gorcunov 165a072738eSCyrill Gorcunov static inline u32 p4_default_cccr_conf(int cpu) 166a072738eSCyrill Gorcunov { 167a072738eSCyrill Gorcunov /* 168a072738eSCyrill Gorcunov * Note that P4_CCCR_THREAD_ANY is "required" on 169a072738eSCyrill Gorcunov * non-HT machines (on HT machines we count TS events 170a072738eSCyrill Gorcunov * regardless the state of second logical processor 171a072738eSCyrill Gorcunov */ 172a072738eSCyrill Gorcunov u32 cccr = P4_CCCR_THREAD_ANY; 173a072738eSCyrill Gorcunov 174a072738eSCyrill Gorcunov if (!p4_ht_thread(cpu)) 175a072738eSCyrill Gorcunov cccr |= P4_CCCR_OVF_PMI_T0; 176a072738eSCyrill Gorcunov else 177a072738eSCyrill Gorcunov cccr |= P4_CCCR_OVF_PMI_T1; 178a072738eSCyrill Gorcunov 179a072738eSCyrill Gorcunov return cccr; 180a072738eSCyrill Gorcunov } 181a072738eSCyrill Gorcunov 182a072738eSCyrill Gorcunov static inline u32 p4_default_escr_conf(int cpu, int exclude_os, int exclude_usr) 183a072738eSCyrill Gorcunov { 184a072738eSCyrill Gorcunov u32 escr = 0; 185a072738eSCyrill Gorcunov 186a072738eSCyrill Gorcunov if (!p4_ht_thread(cpu)) { 187a072738eSCyrill Gorcunov if (!exclude_os) 188d814f301SCyrill Gorcunov escr |= P4_ESCR_T0_OS; 189a072738eSCyrill Gorcunov if (!exclude_usr) 190d814f301SCyrill Gorcunov escr |= P4_ESCR_T0_USR; 191a072738eSCyrill Gorcunov } else { 192a072738eSCyrill Gorcunov if (!exclude_os) 193d814f301SCyrill Gorcunov escr |= P4_ESCR_T1_OS; 194a072738eSCyrill Gorcunov if (!exclude_usr) 195d814f301SCyrill Gorcunov escr |= P4_ESCR_T1_USR; 196a072738eSCyrill Gorcunov } 197a072738eSCyrill Gorcunov 198a072738eSCyrill Gorcunov return escr; 199a072738eSCyrill Gorcunov } 200a072738eSCyrill Gorcunov 20139ef13a4SCyrill Gorcunov /* 20239ef13a4SCyrill Gorcunov * This are the events which should be used in "Event Select" 20339ef13a4SCyrill Gorcunov * field of ESCR register, they are like unique keys which allow 20439ef13a4SCyrill Gorcunov * the kernel to determinate which CCCR and COUNTER should be 20539ef13a4SCyrill Gorcunov * used to track an event 20639ef13a4SCyrill Gorcunov */ 207d814f301SCyrill Gorcunov enum P4_EVENTS { 208d814f301SCyrill Gorcunov P4_EVENT_TC_DELIVER_MODE, 209d814f301SCyrill Gorcunov P4_EVENT_BPU_FETCH_REQUEST, 210d814f301SCyrill Gorcunov P4_EVENT_ITLB_REFERENCE, 211d814f301SCyrill Gorcunov P4_EVENT_MEMORY_CANCEL, 212d814f301SCyrill Gorcunov P4_EVENT_MEMORY_COMPLETE, 213d814f301SCyrill Gorcunov P4_EVENT_LOAD_PORT_REPLAY, 214d814f301SCyrill Gorcunov P4_EVENT_STORE_PORT_REPLAY, 215d814f301SCyrill Gorcunov P4_EVENT_MOB_LOAD_REPLAY, 216d814f301SCyrill Gorcunov P4_EVENT_PAGE_WALK_TYPE, 217d814f301SCyrill Gorcunov P4_EVENT_BSQ_CACHE_REFERENCE, 218d814f301SCyrill Gorcunov P4_EVENT_IOQ_ALLOCATION, 219d814f301SCyrill Gorcunov P4_EVENT_IOQ_ACTIVE_ENTRIES, 220d814f301SCyrill Gorcunov P4_EVENT_FSB_DATA_ACTIVITY, 221d814f301SCyrill Gorcunov P4_EVENT_BSQ_ALLOCATION, 222d814f301SCyrill Gorcunov P4_EVENT_BSQ_ACTIVE_ENTRIES, 223d814f301SCyrill Gorcunov P4_EVENT_SSE_INPUT_ASSIST, 224d814f301SCyrill Gorcunov P4_EVENT_PACKED_SP_UOP, 225d814f301SCyrill Gorcunov P4_EVENT_PACKED_DP_UOP, 226d814f301SCyrill Gorcunov P4_EVENT_SCALAR_SP_UOP, 227d814f301SCyrill Gorcunov P4_EVENT_SCALAR_DP_UOP, 228d814f301SCyrill Gorcunov P4_EVENT_64BIT_MMX_UOP, 229d814f301SCyrill Gorcunov P4_EVENT_128BIT_MMX_UOP, 230d814f301SCyrill Gorcunov P4_EVENT_X87_FP_UOP, 231d814f301SCyrill Gorcunov P4_EVENT_TC_MISC, 232d814f301SCyrill Gorcunov P4_EVENT_GLOBAL_POWER_EVENTS, 233d814f301SCyrill Gorcunov P4_EVENT_TC_MS_XFER, 234d814f301SCyrill Gorcunov P4_EVENT_UOP_QUEUE_WRITES, 235d814f301SCyrill Gorcunov P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE, 236d814f301SCyrill Gorcunov P4_EVENT_RETIRED_BRANCH_TYPE, 237d814f301SCyrill Gorcunov P4_EVENT_RESOURCE_STALL, 238d814f301SCyrill Gorcunov P4_EVENT_WC_BUFFER, 239d814f301SCyrill Gorcunov P4_EVENT_B2B_CYCLES, 240d814f301SCyrill Gorcunov P4_EVENT_BNR, 241d814f301SCyrill Gorcunov P4_EVENT_SNOOP, 242d814f301SCyrill Gorcunov P4_EVENT_RESPONSE, 243d814f301SCyrill Gorcunov P4_EVENT_FRONT_END_EVENT, 244d814f301SCyrill Gorcunov P4_EVENT_EXECUTION_EVENT, 245d814f301SCyrill Gorcunov P4_EVENT_REPLAY_EVENT, 246d814f301SCyrill Gorcunov P4_EVENT_INSTR_RETIRED, 247d814f301SCyrill Gorcunov P4_EVENT_UOPS_RETIRED, 248d814f301SCyrill Gorcunov P4_EVENT_UOP_TYPE, 249d814f301SCyrill Gorcunov P4_EVENT_BRANCH_RETIRED, 250d814f301SCyrill Gorcunov P4_EVENT_MISPRED_BRANCH_RETIRED, 251d814f301SCyrill Gorcunov P4_EVENT_X87_ASSIST, 252d814f301SCyrill Gorcunov P4_EVENT_MACHINE_CLEAR, 253d814f301SCyrill Gorcunov P4_EVENT_INSTR_COMPLETED, 254d814f301SCyrill Gorcunov }; 255d814f301SCyrill Gorcunov 256d814f301SCyrill Gorcunov #define P4_OPCODE(event) event##_OPCODE 257d814f301SCyrill Gorcunov #define P4_OPCODE_ESEL(opcode) ((opcode & 0x00ff) >> 0) 258d814f301SCyrill Gorcunov #define P4_OPCODE_EVNT(opcode) ((opcode & 0xff00) >> 8) 259d814f301SCyrill Gorcunov #define P4_OPCODE_PACK(event, sel) (((event) << 8) | sel) 260d814f301SCyrill Gorcunov 261a072738eSCyrill Gorcunov /* 262a072738eSCyrill Gorcunov * Comments below the event represent ESCR restriction 263a072738eSCyrill Gorcunov * for this event and counter index per ESCR 264a072738eSCyrill Gorcunov * 265a072738eSCyrill Gorcunov * MSR_P4_IQ_ESCR0 and MSR_P4_IQ_ESCR1 are available only on early 266a072738eSCyrill Gorcunov * processor builds (family 0FH, models 01H-02H). These MSRs 267a072738eSCyrill Gorcunov * are not available on later versions, so that we don't use 268a072738eSCyrill Gorcunov * them completely 269a072738eSCyrill Gorcunov * 270a072738eSCyrill Gorcunov * Also note that CCCR1 do not have P4_CCCR_ENABLE bit properly 271a072738eSCyrill Gorcunov * working so that we should not use this CCCR and respective 272a072738eSCyrill Gorcunov * counter as result 273a072738eSCyrill Gorcunov */ 274d814f301SCyrill Gorcunov enum P4_EVENT_OPCODES { 275d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_TC_DELIVER_MODE) = P4_OPCODE_PACK(0x01, 0x01), 276a072738eSCyrill Gorcunov /* 277a072738eSCyrill Gorcunov * MSR_P4_TC_ESCR0: 4, 5 278a072738eSCyrill Gorcunov * MSR_P4_TC_ESCR1: 6, 7 279a072738eSCyrill Gorcunov */ 280a072738eSCyrill Gorcunov 281d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_BPU_FETCH_REQUEST) = P4_OPCODE_PACK(0x03, 0x00), 282a072738eSCyrill Gorcunov /* 283a072738eSCyrill Gorcunov * MSR_P4_BPU_ESCR0: 0, 1 284a072738eSCyrill Gorcunov * MSR_P4_BPU_ESCR1: 2, 3 285a072738eSCyrill Gorcunov */ 286a072738eSCyrill Gorcunov 287d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_ITLB_REFERENCE) = P4_OPCODE_PACK(0x18, 0x03), 288a072738eSCyrill Gorcunov /* 289a072738eSCyrill Gorcunov * MSR_P4_ITLB_ESCR0: 0, 1 290a072738eSCyrill Gorcunov * MSR_P4_ITLB_ESCR1: 2, 3 291a072738eSCyrill Gorcunov */ 292a072738eSCyrill Gorcunov 293d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_MEMORY_CANCEL) = P4_OPCODE_PACK(0x02, 0x05), 294a072738eSCyrill Gorcunov /* 295a072738eSCyrill Gorcunov * MSR_P4_DAC_ESCR0: 8, 9 296a072738eSCyrill Gorcunov * MSR_P4_DAC_ESCR1: 10, 11 297a072738eSCyrill Gorcunov */ 298a072738eSCyrill Gorcunov 299d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_MEMORY_COMPLETE) = P4_OPCODE_PACK(0x08, 0x02), 300a072738eSCyrill Gorcunov /* 301a072738eSCyrill Gorcunov * MSR_P4_SAAT_ESCR0: 8, 9 302a072738eSCyrill Gorcunov * MSR_P4_SAAT_ESCR1: 10, 11 303a072738eSCyrill Gorcunov */ 304a072738eSCyrill Gorcunov 305d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_LOAD_PORT_REPLAY) = P4_OPCODE_PACK(0x04, 0x02), 306a072738eSCyrill Gorcunov /* 307a072738eSCyrill Gorcunov * MSR_P4_SAAT_ESCR0: 8, 9 308a072738eSCyrill Gorcunov * MSR_P4_SAAT_ESCR1: 10, 11 309a072738eSCyrill Gorcunov */ 310a072738eSCyrill Gorcunov 311d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_STORE_PORT_REPLAY) = P4_OPCODE_PACK(0x05, 0x02), 312a072738eSCyrill Gorcunov /* 313a072738eSCyrill Gorcunov * MSR_P4_SAAT_ESCR0: 8, 9 314a072738eSCyrill Gorcunov * MSR_P4_SAAT_ESCR1: 10, 11 315a072738eSCyrill Gorcunov */ 316a072738eSCyrill Gorcunov 317d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_MOB_LOAD_REPLAY) = P4_OPCODE_PACK(0x03, 0x02), 318a072738eSCyrill Gorcunov /* 319a072738eSCyrill Gorcunov * MSR_P4_MOB_ESCR0: 0, 1 320a072738eSCyrill Gorcunov * MSR_P4_MOB_ESCR1: 2, 3 321a072738eSCyrill Gorcunov */ 322a072738eSCyrill Gorcunov 323d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_PAGE_WALK_TYPE) = P4_OPCODE_PACK(0x01, 0x04), 324a072738eSCyrill Gorcunov /* 325a072738eSCyrill Gorcunov * MSR_P4_PMH_ESCR0: 0, 1 326a072738eSCyrill Gorcunov * MSR_P4_PMH_ESCR1: 2, 3 327a072738eSCyrill Gorcunov */ 328a072738eSCyrill Gorcunov 329d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_BSQ_CACHE_REFERENCE) = P4_OPCODE_PACK(0x0c, 0x07), 330a072738eSCyrill Gorcunov /* 331a072738eSCyrill Gorcunov * MSR_P4_BSU_ESCR0: 0, 1 332a072738eSCyrill Gorcunov * MSR_P4_BSU_ESCR1: 2, 3 333a072738eSCyrill Gorcunov */ 334a072738eSCyrill Gorcunov 335d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_IOQ_ALLOCATION) = P4_OPCODE_PACK(0x03, 0x06), 336a072738eSCyrill Gorcunov /* 337a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR0: 0, 1 338a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR1: 2, 3 339a072738eSCyrill Gorcunov */ 340a072738eSCyrill Gorcunov 341d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_IOQ_ACTIVE_ENTRIES) = P4_OPCODE_PACK(0x1a, 0x06), 342a072738eSCyrill Gorcunov /* 343a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR1: 2, 3 344a072738eSCyrill Gorcunov */ 345a072738eSCyrill Gorcunov 346d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_FSB_DATA_ACTIVITY) = P4_OPCODE_PACK(0x17, 0x06), 347a072738eSCyrill Gorcunov /* 348a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR0: 0, 1 349a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR1: 2, 3 350a072738eSCyrill Gorcunov */ 351a072738eSCyrill Gorcunov 352d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_BSQ_ALLOCATION) = P4_OPCODE_PACK(0x05, 0x07), 353a072738eSCyrill Gorcunov /* 354a072738eSCyrill Gorcunov * MSR_P4_BSU_ESCR0: 0, 1 355a072738eSCyrill Gorcunov */ 356a072738eSCyrill Gorcunov 357d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_BSQ_ACTIVE_ENTRIES) = P4_OPCODE_PACK(0x06, 0x07), 358a072738eSCyrill Gorcunov /* 3598ea7f544SLin Ming * NOTE: no ESCR name in docs, it's guessed 360a072738eSCyrill Gorcunov * MSR_P4_BSU_ESCR1: 2, 3 361a072738eSCyrill Gorcunov */ 362a072738eSCyrill Gorcunov 363d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_SSE_INPUT_ASSIST) = P4_OPCODE_PACK(0x34, 0x01), 364a072738eSCyrill Gorcunov /* 365e4495262SCyrill Gorcunov * MSR_P4_FIRM_ESCR0: 8, 9 366e4495262SCyrill Gorcunov * MSR_P4_FIRM_ESCR1: 10, 11 367a072738eSCyrill Gorcunov */ 368a072738eSCyrill Gorcunov 369d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_PACKED_SP_UOP) = P4_OPCODE_PACK(0x08, 0x01), 370a072738eSCyrill Gorcunov /* 371a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR0: 8, 9 372a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR1: 10, 11 373a072738eSCyrill Gorcunov */ 374a072738eSCyrill Gorcunov 375d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_PACKED_DP_UOP) = P4_OPCODE_PACK(0x0c, 0x01), 376a072738eSCyrill Gorcunov /* 377a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR0: 8, 9 378a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR1: 10, 11 379a072738eSCyrill Gorcunov */ 380a072738eSCyrill Gorcunov 381d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_SCALAR_SP_UOP) = P4_OPCODE_PACK(0x0a, 0x01), 382a072738eSCyrill Gorcunov /* 383a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR0: 8, 9 384a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR1: 10, 11 385a072738eSCyrill Gorcunov */ 386a072738eSCyrill Gorcunov 387d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_SCALAR_DP_UOP) = P4_OPCODE_PACK(0x0e, 0x01), 388a072738eSCyrill Gorcunov /* 389a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR0: 8, 9 390a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR1: 10, 11 391a072738eSCyrill Gorcunov */ 392a072738eSCyrill Gorcunov 393d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_64BIT_MMX_UOP) = P4_OPCODE_PACK(0x02, 0x01), 394a072738eSCyrill Gorcunov /* 395a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR0: 8, 9 396a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR1: 10, 11 397a072738eSCyrill Gorcunov */ 398a072738eSCyrill Gorcunov 399d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_128BIT_MMX_UOP) = P4_OPCODE_PACK(0x1a, 0x01), 400a072738eSCyrill Gorcunov /* 401a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR0: 8, 9 402a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR1: 10, 11 403a072738eSCyrill Gorcunov */ 404a072738eSCyrill Gorcunov 405d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_X87_FP_UOP) = P4_OPCODE_PACK(0x04, 0x01), 406a072738eSCyrill Gorcunov /* 407a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR0: 8, 9 408a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR1: 10, 11 409a072738eSCyrill Gorcunov */ 410a072738eSCyrill Gorcunov 411d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_TC_MISC) = P4_OPCODE_PACK(0x06, 0x01), 412a072738eSCyrill Gorcunov /* 413a072738eSCyrill Gorcunov * MSR_P4_TC_ESCR0: 4, 5 414a072738eSCyrill Gorcunov * MSR_P4_TC_ESCR1: 6, 7 415a072738eSCyrill Gorcunov */ 416a072738eSCyrill Gorcunov 417d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_GLOBAL_POWER_EVENTS) = P4_OPCODE_PACK(0x13, 0x06), 418a072738eSCyrill Gorcunov /* 419a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR0: 0, 1 420a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR1: 2, 3 421a072738eSCyrill Gorcunov */ 422a072738eSCyrill Gorcunov 423d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_TC_MS_XFER) = P4_OPCODE_PACK(0x05, 0x00), 424a072738eSCyrill Gorcunov /* 425a072738eSCyrill Gorcunov * MSR_P4_MS_ESCR0: 4, 5 426a072738eSCyrill Gorcunov * MSR_P4_MS_ESCR1: 6, 7 427a072738eSCyrill Gorcunov */ 428a072738eSCyrill Gorcunov 429d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_UOP_QUEUE_WRITES) = P4_OPCODE_PACK(0x09, 0x00), 430a072738eSCyrill Gorcunov /* 431a072738eSCyrill Gorcunov * MSR_P4_MS_ESCR0: 4, 5 432a072738eSCyrill Gorcunov * MSR_P4_MS_ESCR1: 6, 7 433a072738eSCyrill Gorcunov */ 434a072738eSCyrill Gorcunov 435d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE) = P4_OPCODE_PACK(0x05, 0x02), 436a072738eSCyrill Gorcunov /* 437a072738eSCyrill Gorcunov * MSR_P4_TBPU_ESCR0: 4, 5 4389c8c6badSCyrill Gorcunov * MSR_P4_TBPU_ESCR1: 6, 7 439a072738eSCyrill Gorcunov */ 440a072738eSCyrill Gorcunov 441d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_RETIRED_BRANCH_TYPE) = P4_OPCODE_PACK(0x04, 0x02), 442a072738eSCyrill Gorcunov /* 443a072738eSCyrill Gorcunov * MSR_P4_TBPU_ESCR0: 4, 5 4449c8c6badSCyrill Gorcunov * MSR_P4_TBPU_ESCR1: 6, 7 445a072738eSCyrill Gorcunov */ 446a072738eSCyrill Gorcunov 447d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_RESOURCE_STALL) = P4_OPCODE_PACK(0x01, 0x01), 448a072738eSCyrill Gorcunov /* 449a072738eSCyrill Gorcunov * MSR_P4_ALF_ESCR0: 12, 13, 16 450a072738eSCyrill Gorcunov * MSR_P4_ALF_ESCR1: 14, 15, 17 451a072738eSCyrill Gorcunov */ 452a072738eSCyrill Gorcunov 453d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_WC_BUFFER) = P4_OPCODE_PACK(0x05, 0x05), 454a072738eSCyrill Gorcunov /* 455a072738eSCyrill Gorcunov * MSR_P4_DAC_ESCR0: 8, 9 456a072738eSCyrill Gorcunov * MSR_P4_DAC_ESCR1: 10, 11 457a072738eSCyrill Gorcunov */ 458a072738eSCyrill Gorcunov 459d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_B2B_CYCLES) = P4_OPCODE_PACK(0x16, 0x03), 460a072738eSCyrill Gorcunov /* 461a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR0: 0, 1 462a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR1: 2, 3 463a072738eSCyrill Gorcunov */ 464a072738eSCyrill Gorcunov 465d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_BNR) = P4_OPCODE_PACK(0x08, 0x03), 466a072738eSCyrill Gorcunov /* 467a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR0: 0, 1 468a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR1: 2, 3 469a072738eSCyrill Gorcunov */ 470a072738eSCyrill Gorcunov 471d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_SNOOP) = P4_OPCODE_PACK(0x06, 0x03), 472a072738eSCyrill Gorcunov /* 473a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR0: 0, 1 474a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR1: 2, 3 475a072738eSCyrill Gorcunov */ 476a072738eSCyrill Gorcunov 477d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_RESPONSE) = P4_OPCODE_PACK(0x04, 0x03), 478a072738eSCyrill Gorcunov /* 479a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR0: 0, 1 480a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR1: 2, 3 481a072738eSCyrill Gorcunov */ 482a072738eSCyrill Gorcunov 483d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_FRONT_END_EVENT) = P4_OPCODE_PACK(0x08, 0x05), 484a072738eSCyrill Gorcunov /* 485a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR2: 12, 13, 16 486a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR3: 14, 15, 17 487a072738eSCyrill Gorcunov */ 488a072738eSCyrill Gorcunov 489d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_EXECUTION_EVENT) = P4_OPCODE_PACK(0x0c, 0x05), 490a072738eSCyrill Gorcunov /* 491a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR2: 12, 13, 16 492a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR3: 14, 15, 17 493a072738eSCyrill Gorcunov */ 494a072738eSCyrill Gorcunov 495d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_REPLAY_EVENT) = P4_OPCODE_PACK(0x09, 0x05), 496a072738eSCyrill Gorcunov /* 497a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR2: 12, 13, 16 498a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR3: 14, 15, 17 499a072738eSCyrill Gorcunov */ 500a072738eSCyrill Gorcunov 501d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_INSTR_RETIRED) = P4_OPCODE_PACK(0x02, 0x04), 502a072738eSCyrill Gorcunov /* 503e4495262SCyrill Gorcunov * MSR_P4_CRU_ESCR0: 12, 13, 16 504e4495262SCyrill Gorcunov * MSR_P4_CRU_ESCR1: 14, 15, 17 505a072738eSCyrill Gorcunov */ 506a072738eSCyrill Gorcunov 507d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_UOPS_RETIRED) = P4_OPCODE_PACK(0x01, 0x04), 508a072738eSCyrill Gorcunov /* 5098ea7f544SLin Ming * MSR_P4_CRU_ESCR0: 12, 13, 16 5108ea7f544SLin Ming * MSR_P4_CRU_ESCR1: 14, 15, 17 511a072738eSCyrill Gorcunov */ 512a072738eSCyrill Gorcunov 513d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_UOP_TYPE) = P4_OPCODE_PACK(0x02, 0x02), 514a072738eSCyrill Gorcunov /* 515a072738eSCyrill Gorcunov * MSR_P4_RAT_ESCR0: 12, 13, 16 516a072738eSCyrill Gorcunov * MSR_P4_RAT_ESCR1: 14, 15, 17 517a072738eSCyrill Gorcunov */ 518a072738eSCyrill Gorcunov 519d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_BRANCH_RETIRED) = P4_OPCODE_PACK(0x06, 0x05), 520a072738eSCyrill Gorcunov /* 521a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR2: 12, 13, 16 522a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR3: 14, 15, 17 523a072738eSCyrill Gorcunov */ 524a072738eSCyrill Gorcunov 525d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_MISPRED_BRANCH_RETIRED) = P4_OPCODE_PACK(0x03, 0x04), 526a072738eSCyrill Gorcunov /* 527a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR0: 12, 13, 16 528a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR1: 14, 15, 17 529a072738eSCyrill Gorcunov */ 530a072738eSCyrill Gorcunov 531d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_X87_ASSIST) = P4_OPCODE_PACK(0x03, 0x05), 532a072738eSCyrill Gorcunov /* 533a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR2: 12, 13, 16 534a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR3: 14, 15, 17 535a072738eSCyrill Gorcunov */ 536a072738eSCyrill Gorcunov 537d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_MACHINE_CLEAR) = P4_OPCODE_PACK(0x02, 0x05), 538a072738eSCyrill Gorcunov /* 539a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR2: 12, 13, 16 540a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR3: 14, 15, 17 541a072738eSCyrill Gorcunov */ 542a072738eSCyrill Gorcunov 543d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_INSTR_COMPLETED) = P4_OPCODE_PACK(0x07, 0x04), 544a072738eSCyrill Gorcunov /* 545a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR0: 12, 13, 16 546a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR1: 14, 15, 17 547a072738eSCyrill Gorcunov */ 548a072738eSCyrill Gorcunov }; 549a072738eSCyrill Gorcunov 550d814f301SCyrill Gorcunov /* 551d814f301SCyrill Gorcunov * a caller should use P4_ESCR_EMASK_NAME helper to 552d814f301SCyrill Gorcunov * pick the EventMask needed, for example 553d814f301SCyrill Gorcunov * 55439ef13a4SCyrill Gorcunov * P4_ESCR_EMASK_BIT(P4_EVENT_TC_DELIVER_MODE, DD) 555d814f301SCyrill Gorcunov */ 556d814f301SCyrill Gorcunov enum P4_ESCR_EMASKS { 557d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, DD, 0), 558d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, DB, 1), 559d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, DI, 2), 560d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, BD, 3), 561d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, BB, 4), 562d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, BI, 5), 563d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, ID, 6), 564d814f301SCyrill Gorcunov 565d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BPU_FETCH_REQUEST, TCMISS, 0), 566d814f301SCyrill Gorcunov 567d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_ITLB_REFERENCE, HIT, 0), 568d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_ITLB_REFERENCE, MISS, 1), 569d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_ITLB_REFERENCE, HIT_UK, 2), 570d814f301SCyrill Gorcunov 571d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_MEMORY_CANCEL, ST_RB_FULL, 2), 572d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_MEMORY_CANCEL, 64K_CONF, 3), 573d814f301SCyrill Gorcunov 574d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_MEMORY_COMPLETE, LSC, 0), 575d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_MEMORY_COMPLETE, SSC, 1), 576d814f301SCyrill Gorcunov 577d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_LOAD_PORT_REPLAY, SPLIT_LD, 1), 578d814f301SCyrill Gorcunov 579d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_STORE_PORT_REPLAY, SPLIT_ST, 1), 580d814f301SCyrill Gorcunov 581d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_MOB_LOAD_REPLAY, NO_STA, 1), 582d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_MOB_LOAD_REPLAY, NO_STD, 3), 583d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_MOB_LOAD_REPLAY, PARTIAL_DATA, 4), 584d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_MOB_LOAD_REPLAY, UNALGN_ADDR, 5), 585d814f301SCyrill Gorcunov 586d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_PAGE_WALK_TYPE, DTMISS, 0), 587d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_PAGE_WALK_TYPE, ITMISS, 1), 588d814f301SCyrill Gorcunov 589d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_HITS, 0), 590d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_HITE, 1), 591d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_HITM, 2), 592d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_HITS, 3), 593d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_HITE, 4), 594d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_HITM, 5), 595d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_MISS, 8), 596d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_MISS, 9), 597d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, WR_2ndL_MISS, 10), 598d814f301SCyrill Gorcunov 599d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, DEFAULT, 0), 600d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, ALL_READ, 5), 601d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, ALL_WRITE, 6), 602d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, MEM_UC, 7), 603d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, MEM_WC, 8), 604d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, MEM_WT, 9), 605d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, MEM_WP, 10), 606d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, MEM_WB, 11), 607d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, OWN, 13), 608d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, OTHER, 14), 609d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, PREFETCH, 15), 610d814f301SCyrill Gorcunov 611d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, DEFAULT, 0), 612d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, ALL_READ, 5), 613d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, ALL_WRITE, 6), 614d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, MEM_UC, 7), 615d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, MEM_WC, 8), 616d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, MEM_WT, 9), 617d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, MEM_WP, 10), 618d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, MEM_WB, 11), 619d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, OWN, 13), 620d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, OTHER, 14), 621d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, PREFETCH, 15), 622d814f301SCyrill Gorcunov 623d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_FSB_DATA_ACTIVITY, DRDY_DRV, 0), 624d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_FSB_DATA_ACTIVITY, DRDY_OWN, 1), 625d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_FSB_DATA_ACTIVITY, DRDY_OTHER, 2), 626d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_FSB_DATA_ACTIVITY, DBSY_DRV, 3), 627d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_FSB_DATA_ACTIVITY, DBSY_OWN, 4), 628d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_FSB_DATA_ACTIVITY, DBSY_OTHER, 5), 629d814f301SCyrill Gorcunov 630d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_TYPE0, 0), 631d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_TYPE1, 1), 632d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_LEN0, 2), 633d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_LEN1, 3), 634d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_IO_TYPE, 5), 635d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_LOCK_TYPE, 6), 636d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_CACHE_TYPE, 7), 637d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_SPLIT_TYPE, 8), 638d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_DEM_TYPE, 9), 639d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_ORD_TYPE, 10), 640d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, MEM_TYPE0, 11), 641d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, MEM_TYPE1, 12), 642d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, MEM_TYPE2, 13), 643d814f301SCyrill Gorcunov 644d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_TYPE0, 0), 645d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_TYPE1, 1), 646d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_LEN0, 2), 647d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_LEN1, 3), 648d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_IO_TYPE, 5), 649d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_LOCK_TYPE, 6), 650d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_CACHE_TYPE, 7), 651d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_SPLIT_TYPE, 8), 652d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_DEM_TYPE, 9), 653d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_ORD_TYPE, 10), 654d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, MEM_TYPE0, 11), 655d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, MEM_TYPE1, 12), 656d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, MEM_TYPE2, 13), 657d814f301SCyrill Gorcunov 658d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_SSE_INPUT_ASSIST, ALL, 15), 659d814f301SCyrill Gorcunov 660d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_PACKED_SP_UOP, ALL, 15), 661d814f301SCyrill Gorcunov 662d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_PACKED_DP_UOP, ALL, 15), 663d814f301SCyrill Gorcunov 664d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_SCALAR_SP_UOP, ALL, 15), 665d814f301SCyrill Gorcunov 666d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_SCALAR_DP_UOP, ALL, 15), 667d814f301SCyrill Gorcunov 668d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_64BIT_MMX_UOP, ALL, 15), 669d814f301SCyrill Gorcunov 670d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_128BIT_MMX_UOP, ALL, 15), 671d814f301SCyrill Gorcunov 672d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_X87_FP_UOP, ALL, 15), 673d814f301SCyrill Gorcunov 674d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_TC_MISC, FLUSH, 4), 675d814f301SCyrill Gorcunov 676d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_GLOBAL_POWER_EVENTS, RUNNING, 0), 677d814f301SCyrill Gorcunov 678d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_TC_MS_XFER, CISC, 0), 679d814f301SCyrill Gorcunov 680d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_UOP_QUEUE_WRITES, FROM_TC_BUILD, 0), 681d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_UOP_QUEUE_WRITES, FROM_TC_DELIVER, 1), 682d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_UOP_QUEUE_WRITES, FROM_ROM, 2), 683d814f301SCyrill Gorcunov 684d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE, CONDITIONAL, 1), 685d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE, CALL, 2), 686d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE, RETURN, 3), 687d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE, INDIRECT, 4), 688d814f301SCyrill Gorcunov 689d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_BRANCH_TYPE, CONDITIONAL, 1), 690d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_BRANCH_TYPE, CALL, 2), 691d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_BRANCH_TYPE, RETURN, 3), 692d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_BRANCH_TYPE, INDIRECT, 4), 693d814f301SCyrill Gorcunov 694d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_RESOURCE_STALL, SBFULL, 5), 695d814f301SCyrill Gorcunov 696d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_WC_BUFFER, WCB_EVICTS, 0), 697d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_WC_BUFFER, WCB_FULL_EVICTS, 1), 698d814f301SCyrill Gorcunov 699d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_FRONT_END_EVENT, NBOGUS, 0), 700d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_FRONT_END_EVENT, BOGUS, 1), 701d814f301SCyrill Gorcunov 702d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, NBOGUS0, 0), 703d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, NBOGUS1, 1), 704d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, NBOGUS2, 2), 705d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, NBOGUS3, 3), 706d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, BOGUS0, 4), 707d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, BOGUS1, 5), 708d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, BOGUS2, 6), 709d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, BOGUS3, 7), 710d814f301SCyrill Gorcunov 711d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_REPLAY_EVENT, NBOGUS, 0), 712d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_REPLAY_EVENT, BOGUS, 1), 713d814f301SCyrill Gorcunov 714d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_INSTR_RETIRED, NBOGUSNTAG, 0), 715d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_INSTR_RETIRED, NBOGUSTAG, 1), 716d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_INSTR_RETIRED, BOGUSNTAG, 2), 717d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_INSTR_RETIRED, BOGUSTAG, 3), 718d814f301SCyrill Gorcunov 719d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_UOPS_RETIRED, NBOGUS, 0), 720d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_UOPS_RETIRED, BOGUS, 1), 721d814f301SCyrill Gorcunov 722d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_UOP_TYPE, TAGLOADS, 1), 723d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_UOP_TYPE, TAGSTORES, 2), 724d814f301SCyrill Gorcunov 725d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BRANCH_RETIRED, MMNP, 0), 726d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BRANCH_RETIRED, MMNM, 1), 727d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BRANCH_RETIRED, MMTP, 2), 728d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BRANCH_RETIRED, MMTM, 3), 729d814f301SCyrill Gorcunov 730d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_MISPRED_BRANCH_RETIRED, NBOGUS, 0), 731d814f301SCyrill Gorcunov 732d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_X87_ASSIST, FPSU, 0), 733d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_X87_ASSIST, FPSO, 1), 734d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_X87_ASSIST, POAO, 2), 735d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_X87_ASSIST, POAU, 3), 736d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_X87_ASSIST, PREA, 4), 737d814f301SCyrill Gorcunov 738d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_MACHINE_CLEAR, CLEAR, 0), 739d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_MACHINE_CLEAR, MOCLEAR, 1), 740d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_MACHINE_CLEAR, SMCLEAR, 2), 741d814f301SCyrill Gorcunov 742d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_INSTR_COMPLETED, NBOGUS, 0), 743d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_INSTR_COMPLETED, BOGUS, 1), 744d814f301SCyrill Gorcunov }; 745d814f301SCyrill Gorcunov 74639ef13a4SCyrill Gorcunov /* 74739ef13a4SCyrill Gorcunov * Note we have UOP and PEBS bits reserved for now 74839ef13a4SCyrill Gorcunov * just in case if we will need them once 74939ef13a4SCyrill Gorcunov */ 75039ef13a4SCyrill Gorcunov #define P4_PEBS_CONFIG_ENABLE (1 << 7) 75139ef13a4SCyrill Gorcunov #define P4_PEBS_CONFIG_UOP_TAG (1 << 8) 75239ef13a4SCyrill Gorcunov #define P4_PEBS_CONFIG_METRIC_MASK 0x3f 75339ef13a4SCyrill Gorcunov #define P4_PEBS_CONFIG_MASK 0xff 75439ef13a4SCyrill Gorcunov 75539ef13a4SCyrill Gorcunov /* 75639ef13a4SCyrill Gorcunov * mem: Only counters MSR_IQ_COUNTER4 (16) and 75739ef13a4SCyrill Gorcunov * MSR_IQ_COUNTER5 (17) are allowed for PEBS sampling 75839ef13a4SCyrill Gorcunov */ 759d814f301SCyrill Gorcunov #define P4_PEBS_ENABLE 0x02000000U 76039ef13a4SCyrill Gorcunov #define P4_PEBS_ENABLE_UOP_TAG 0x01000000U 761d814f301SCyrill Gorcunov 76239ef13a4SCyrill Gorcunov #define p4_config_unpack_metric(v) (((u64)(v)) & P4_PEBS_CONFIG_METRIC_MASK) 76339ef13a4SCyrill Gorcunov #define p4_config_unpack_pebs(v) (((u64)(v)) & P4_PEBS_CONFIG_MASK) 764d814f301SCyrill Gorcunov 76539ef13a4SCyrill Gorcunov #define p4_config_pebs_has(v, mask) (p4_config_unpack_pebs(v) & (mask)) 766d814f301SCyrill Gorcunov 76739ef13a4SCyrill Gorcunov enum P4_PEBS_METRIC { 76839ef13a4SCyrill Gorcunov P4_PEBS_METRIC__none, 769d814f301SCyrill Gorcunov 77039ef13a4SCyrill Gorcunov P4_PEBS_METRIC__1stl_cache_load_miss_retired, 77139ef13a4SCyrill Gorcunov P4_PEBS_METRIC__2ndl_cache_load_miss_retired, 77239ef13a4SCyrill Gorcunov P4_PEBS_METRIC__dtlb_load_miss_retired, 77339ef13a4SCyrill Gorcunov P4_PEBS_METRIC__dtlb_store_miss_retired, 77439ef13a4SCyrill Gorcunov P4_PEBS_METRIC__dtlb_all_miss_retired, 77539ef13a4SCyrill Gorcunov P4_PEBS_METRIC__tagged_mispred_branch, 77639ef13a4SCyrill Gorcunov P4_PEBS_METRIC__mob_load_replay_retired, 77739ef13a4SCyrill Gorcunov P4_PEBS_METRIC__split_load_retired, 77839ef13a4SCyrill Gorcunov P4_PEBS_METRIC__split_store_retired, 779d814f301SCyrill Gorcunov 78039ef13a4SCyrill Gorcunov P4_PEBS_METRIC__max 781cb7d6b50SLin Ming }; 782cb7d6b50SLin Ming 783*af86da53SCyrill Gorcunov /* 784*af86da53SCyrill Gorcunov * Notes on internal configuration of ESCR+CCCR tuples 785*af86da53SCyrill Gorcunov * 786*af86da53SCyrill Gorcunov * Since P4 has quite the different architecture of 787*af86da53SCyrill Gorcunov * performance registers in compare with "architectural" 788*af86da53SCyrill Gorcunov * once and we have on 64 bits to keep configuration 789*af86da53SCyrill Gorcunov * of performance event, the following trick is used. 790*af86da53SCyrill Gorcunov * 791*af86da53SCyrill Gorcunov * 1) Since both ESCR and CCCR registers have only low 792*af86da53SCyrill Gorcunov * 32 bits valuable, we pack them into a single 64 bit 793*af86da53SCyrill Gorcunov * configuration. Low 32 bits of such config correspond 794*af86da53SCyrill Gorcunov * to low 32 bits of CCCR register and high 32 bits 795*af86da53SCyrill Gorcunov * correspond to low 32 bits of ESCR register. 796*af86da53SCyrill Gorcunov * 797*af86da53SCyrill Gorcunov * 2) The meaning of every bit of such config field can 798*af86da53SCyrill Gorcunov * be found in Intel SDM but it should be noted that 799*af86da53SCyrill Gorcunov * we "borrow" some reserved bits for own usage and 800*af86da53SCyrill Gorcunov * clean them or set to a proper value when we do 801*af86da53SCyrill Gorcunov * a real write to hardware registers. 802*af86da53SCyrill Gorcunov * 803*af86da53SCyrill Gorcunov * 3) The format of bits of config is the following 804*af86da53SCyrill Gorcunov * and should be either 0 or set to some predefined 805*af86da53SCyrill Gorcunov * values: 806*af86da53SCyrill Gorcunov * 807*af86da53SCyrill Gorcunov * Low 32 bits 808*af86da53SCyrill Gorcunov * ----------- 809*af86da53SCyrill Gorcunov * 0-6: P4_PEBS_METRIC enum 810*af86da53SCyrill Gorcunov * 7-11: reserved 811*af86da53SCyrill Gorcunov * 12: reserved (Enable) 812*af86da53SCyrill Gorcunov * 13-15: reserved (ESCR select) 813*af86da53SCyrill Gorcunov * 16-17: Active Thread 814*af86da53SCyrill Gorcunov * 18: Compare 815*af86da53SCyrill Gorcunov * 19: Complement 816*af86da53SCyrill Gorcunov * 20-23: Threshold 817*af86da53SCyrill Gorcunov * 24: Edge 818*af86da53SCyrill Gorcunov * 25: reserved (FORCE_OVF) 819*af86da53SCyrill Gorcunov * 26: reserved (OVF_PMI_T0) 820*af86da53SCyrill Gorcunov * 27: reserved (OVF_PMI_T1) 821*af86da53SCyrill Gorcunov * 28-29: reserved 822*af86da53SCyrill Gorcunov * 30: reserved (Cascade) 823*af86da53SCyrill Gorcunov * 31: reserved (OVF) 824*af86da53SCyrill Gorcunov * 825*af86da53SCyrill Gorcunov * High 32 bits 826*af86da53SCyrill Gorcunov * ------------ 827*af86da53SCyrill Gorcunov * 0: reserved (T1_USR) 828*af86da53SCyrill Gorcunov * 1: reserved (T1_OS) 829*af86da53SCyrill Gorcunov * 2: reserved (T0_USR) 830*af86da53SCyrill Gorcunov * 3: reserved (T0_OS) 831*af86da53SCyrill Gorcunov * 4: Tag Enable 832*af86da53SCyrill Gorcunov * 5-8: Tag Value 833*af86da53SCyrill Gorcunov * 9-24: Event Mask (may use P4_ESCR_EMASK_BIT helper) 834*af86da53SCyrill Gorcunov * 25-30: enum P4_EVENTS 835*af86da53SCyrill Gorcunov * 31: reserved (HT thread) 836*af86da53SCyrill Gorcunov */ 837*af86da53SCyrill Gorcunov 838a072738eSCyrill Gorcunov #endif /* PERF_EVENT_P4_H */ 83939ef13a4SCyrill Gorcunov 840