1*a072738eSCyrill Gorcunov /* 2*a072738eSCyrill Gorcunov * Netburst Perfomance Events (P4, old Xeon) 3*a072738eSCyrill Gorcunov */ 4*a072738eSCyrill Gorcunov 5*a072738eSCyrill Gorcunov #ifndef PERF_EVENT_P4_H 6*a072738eSCyrill Gorcunov #define PERF_EVENT_P4_H 7*a072738eSCyrill Gorcunov 8*a072738eSCyrill Gorcunov #include <linux/cpu.h> 9*a072738eSCyrill Gorcunov #include <linux/bitops.h> 10*a072738eSCyrill Gorcunov 11*a072738eSCyrill Gorcunov /* 12*a072738eSCyrill Gorcunov * NetBurst has perfomance MSRs shared between 13*a072738eSCyrill Gorcunov * threads if HT is turned on, ie for both logical 14*a072738eSCyrill Gorcunov * processors (mem: in turn in Atom with HT support 15*a072738eSCyrill Gorcunov * perf-MSRs are not shared and every thread has its 16*a072738eSCyrill Gorcunov * own perf-MSRs set) 17*a072738eSCyrill Gorcunov */ 18*a072738eSCyrill Gorcunov #define ARCH_P4_TOTAL_ESCR (46) 19*a072738eSCyrill Gorcunov #define ARCH_P4_RESERVED_ESCR (2) /* IQ_ESCR(0,1) not always present */ 20*a072738eSCyrill Gorcunov #define ARCH_P4_MAX_ESCR (ARCH_P4_TOTAL_ESCR - ARCH_P4_RESERVED_ESCR) 21*a072738eSCyrill Gorcunov #define ARCH_P4_MAX_CCCR (18) 22*a072738eSCyrill Gorcunov #define ARCH_P4_MAX_COUNTER (ARCH_P4_MAX_CCCR / 2) 23*a072738eSCyrill Gorcunov 24*a072738eSCyrill Gorcunov #define P4_EVNTSEL_EVENT_MASK 0x7e000000U 25*a072738eSCyrill Gorcunov #define P4_EVNTSEL_EVENT_SHIFT 25 26*a072738eSCyrill Gorcunov #define P4_EVNTSEL_EVENTMASK_MASK 0x01fffe00U 27*a072738eSCyrill Gorcunov #define P4_EVNTSEL_EVENTMASK_SHIFT 9 28*a072738eSCyrill Gorcunov #define P4_EVNTSEL_TAG_MASK 0x000001e0U 29*a072738eSCyrill Gorcunov #define P4_EVNTSEL_TAG_SHIFT 5 30*a072738eSCyrill Gorcunov #define P4_EVNTSEL_TAG_ENABLE 0x00000010U 31*a072738eSCyrill Gorcunov #define P4_EVNTSEL_T0_OS 0x00000008U 32*a072738eSCyrill Gorcunov #define P4_EVNTSEL_T0_USR 0x00000004U 33*a072738eSCyrill Gorcunov #define P4_EVNTSEL_T1_OS 0x00000002U 34*a072738eSCyrill Gorcunov #define P4_EVNTSEL_T1_USR 0x00000001U 35*a072738eSCyrill Gorcunov 36*a072738eSCyrill Gorcunov /* Non HT mask */ 37*a072738eSCyrill Gorcunov #define P4_EVNTSEL_MASK \ 38*a072738eSCyrill Gorcunov (P4_EVNTSEL_EVENT_MASK | \ 39*a072738eSCyrill Gorcunov P4_EVNTSEL_EVENTMASK_MASK | \ 40*a072738eSCyrill Gorcunov P4_EVNTSEL_TAG_MASK | \ 41*a072738eSCyrill Gorcunov P4_EVNTSEL_TAG_ENABLE | \ 42*a072738eSCyrill Gorcunov P4_EVNTSEL_T0_OS | \ 43*a072738eSCyrill Gorcunov P4_EVNTSEL_T0_USR) 44*a072738eSCyrill Gorcunov 45*a072738eSCyrill Gorcunov /* HT mask */ 46*a072738eSCyrill Gorcunov #define P4_EVNTSEL_MASK_HT \ 47*a072738eSCyrill Gorcunov (P4_EVNTSEL_MASK | \ 48*a072738eSCyrill Gorcunov P4_EVNTSEL_T1_OS | \ 49*a072738eSCyrill Gorcunov P4_EVNTSEL_T1_USR) 50*a072738eSCyrill Gorcunov 51*a072738eSCyrill Gorcunov #define P4_CCCR_OVF 0x80000000U 52*a072738eSCyrill Gorcunov #define P4_CCCR_CASCADE 0x40000000U 53*a072738eSCyrill Gorcunov #define P4_CCCR_OVF_PMI_T0 0x04000000U 54*a072738eSCyrill Gorcunov #define P4_CCCR_OVF_PMI_T1 0x08000000U 55*a072738eSCyrill Gorcunov #define P4_CCCR_FORCE_OVF 0x02000000U 56*a072738eSCyrill Gorcunov #define P4_CCCR_EDGE 0x01000000U 57*a072738eSCyrill Gorcunov #define P4_CCCR_THRESHOLD_MASK 0x00f00000U 58*a072738eSCyrill Gorcunov #define P4_CCCR_THRESHOLD_SHIFT 20 59*a072738eSCyrill Gorcunov #define P4_CCCR_THRESHOLD(v) ((v) << P4_CCCR_THRESHOLD_SHIFT) 60*a072738eSCyrill Gorcunov #define P4_CCCR_COMPLEMENT 0x00080000U 61*a072738eSCyrill Gorcunov #define P4_CCCR_COMPARE 0x00040000U 62*a072738eSCyrill Gorcunov #define P4_CCCR_ESCR_SELECT_MASK 0x0000e000U 63*a072738eSCyrill Gorcunov #define P4_CCCR_ESCR_SELECT_SHIFT 13 64*a072738eSCyrill Gorcunov #define P4_CCCR_ENABLE 0x00001000U 65*a072738eSCyrill Gorcunov #define P4_CCCR_THREAD_SINGLE 0x00010000U 66*a072738eSCyrill Gorcunov #define P4_CCCR_THREAD_BOTH 0x00020000U 67*a072738eSCyrill Gorcunov #define P4_CCCR_THREAD_ANY 0x00030000U 68*a072738eSCyrill Gorcunov 69*a072738eSCyrill Gorcunov /* Non HT mask */ 70*a072738eSCyrill Gorcunov #define P4_CCCR_MASK \ 71*a072738eSCyrill Gorcunov (P4_CCCR_OVF | \ 72*a072738eSCyrill Gorcunov P4_CCCR_CASCADE | \ 73*a072738eSCyrill Gorcunov P4_CCCR_OVF_PMI_T0 | \ 74*a072738eSCyrill Gorcunov P4_CCCR_FORCE_OVF | \ 75*a072738eSCyrill Gorcunov P4_CCCR_EDGE | \ 76*a072738eSCyrill Gorcunov P4_CCCR_THRESHOLD_MASK | \ 77*a072738eSCyrill Gorcunov P4_CCCR_COMPLEMENT | \ 78*a072738eSCyrill Gorcunov P4_CCCR_COMPARE | \ 79*a072738eSCyrill Gorcunov P4_CCCR_ESCR_SELECT_MASK | \ 80*a072738eSCyrill Gorcunov P4_CCCR_ENABLE) 81*a072738eSCyrill Gorcunov 82*a072738eSCyrill Gorcunov /* HT mask */ 83*a072738eSCyrill Gorcunov #define P4_CCCR_MASK_HT \ 84*a072738eSCyrill Gorcunov (P4_CCCR_MASK | \ 85*a072738eSCyrill Gorcunov P4_CCCR_THREAD_ANY) 86*a072738eSCyrill Gorcunov 87*a072738eSCyrill Gorcunov /* 88*a072738eSCyrill Gorcunov * format is 32 bit: ee ss aa aa 89*a072738eSCyrill Gorcunov * where 90*a072738eSCyrill Gorcunov * ee - 8 bit event 91*a072738eSCyrill Gorcunov * ss - 8 bit selector 92*a072738eSCyrill Gorcunov * aa aa - 16 bits reserved for tags/attributes 93*a072738eSCyrill Gorcunov */ 94*a072738eSCyrill Gorcunov #define P4_EVENT_PACK(event, selector) (((event) << 24) | ((selector) << 16)) 95*a072738eSCyrill Gorcunov #define P4_EVENT_UNPACK_EVENT(packed) (((packed) >> 24) & 0xff) 96*a072738eSCyrill Gorcunov #define P4_EVENT_UNPACK_SELECTOR(packed) (((packed) >> 16) & 0xff) 97*a072738eSCyrill Gorcunov #define P4_EVENT_PACK_ATTR(attr) ((attr)) 98*a072738eSCyrill Gorcunov #define P4_EVENT_UNPACK_ATTR(packed) ((packed) & 0xffff) 99*a072738eSCyrill Gorcunov #define P4_MAKE_EVENT_ATTR(class, name, bit) class##_##name = (1 << bit) 100*a072738eSCyrill Gorcunov #define P4_EVENT_ATTR(class, name) class##_##name 101*a072738eSCyrill Gorcunov #define P4_EVENT_ATTR_STR(class, name) __stringify(class##_##name) 102*a072738eSCyrill Gorcunov 103*a072738eSCyrill Gorcunov /* 104*a072738eSCyrill Gorcunov * config field is 64bit width and consists of 105*a072738eSCyrill Gorcunov * HT << 63 | ESCR << 32 | CCCR 106*a072738eSCyrill Gorcunov * where HT is HyperThreading bit (since ESCR 107*a072738eSCyrill Gorcunov * has it reserved we may use it for own purpose) 108*a072738eSCyrill Gorcunov * 109*a072738eSCyrill Gorcunov * note that this is NOT the addresses of respective 110*a072738eSCyrill Gorcunov * ESCR and CCCR but rather an only packed value should 111*a072738eSCyrill Gorcunov * be unpacked and written to a proper addresses 112*a072738eSCyrill Gorcunov * 113*a072738eSCyrill Gorcunov * the base idea is to pack as much info as 114*a072738eSCyrill Gorcunov * possible 115*a072738eSCyrill Gorcunov */ 116*a072738eSCyrill Gorcunov #define p4_config_pack_escr(v) (((u64)(v)) << 32) 117*a072738eSCyrill Gorcunov #define p4_config_pack_cccr(v) (((u64)(v)) & 0xffffffffULL) 118*a072738eSCyrill Gorcunov #define p4_config_unpack_escr(v) (((u64)(v)) >> 32) 119*a072738eSCyrill Gorcunov #define p4_config_unpack_cccr(v) (((u64)(v)) & 0xffffffffULL) 120*a072738eSCyrill Gorcunov 121*a072738eSCyrill Gorcunov #define p4_config_unpack_emask(v) \ 122*a072738eSCyrill Gorcunov ({ \ 123*a072738eSCyrill Gorcunov u32 t = p4_config_unpack_escr((v)); \ 124*a072738eSCyrill Gorcunov t &= P4_EVNTSEL_EVENTMASK_MASK; \ 125*a072738eSCyrill Gorcunov t >>= P4_EVNTSEL_EVENTMASK_SHIFT; \ 126*a072738eSCyrill Gorcunov t; \ 127*a072738eSCyrill Gorcunov }) 128*a072738eSCyrill Gorcunov 129*a072738eSCyrill Gorcunov #define P4_CONFIG_HT_SHIFT 63 130*a072738eSCyrill Gorcunov #define P4_CONFIG_HT (1ULL << P4_CONFIG_HT_SHIFT) 131*a072738eSCyrill Gorcunov 132*a072738eSCyrill Gorcunov static inline u32 p4_config_unpack_opcode(u64 config) 133*a072738eSCyrill Gorcunov { 134*a072738eSCyrill Gorcunov u32 e, s; 135*a072738eSCyrill Gorcunov 136*a072738eSCyrill Gorcunov /* 137*a072738eSCyrill Gorcunov * we don't care about HT presence here since 138*a072738eSCyrill Gorcunov * event opcode doesn't depend on it 139*a072738eSCyrill Gorcunov */ 140*a072738eSCyrill Gorcunov e = (p4_config_unpack_escr(config) & P4_EVNTSEL_EVENT_MASK) >> P4_EVNTSEL_EVENT_SHIFT; 141*a072738eSCyrill Gorcunov s = (p4_config_unpack_cccr(config) & P4_CCCR_ESCR_SELECT_MASK) >> P4_CCCR_ESCR_SELECT_SHIFT; 142*a072738eSCyrill Gorcunov 143*a072738eSCyrill Gorcunov return P4_EVENT_PACK(e, s); 144*a072738eSCyrill Gorcunov } 145*a072738eSCyrill Gorcunov 146*a072738eSCyrill Gorcunov static inline bool p4_is_event_cascaded(u64 config) 147*a072738eSCyrill Gorcunov { 148*a072738eSCyrill Gorcunov u32 cccr = p4_config_unpack_cccr(config); 149*a072738eSCyrill Gorcunov return !!(cccr & P4_CCCR_CASCADE); 150*a072738eSCyrill Gorcunov } 151*a072738eSCyrill Gorcunov 152*a072738eSCyrill Gorcunov static inline int p4_ht_config_thread(u64 config) 153*a072738eSCyrill Gorcunov { 154*a072738eSCyrill Gorcunov return !!(config & P4_CONFIG_HT); 155*a072738eSCyrill Gorcunov } 156*a072738eSCyrill Gorcunov 157*a072738eSCyrill Gorcunov static inline u64 p4_set_ht_bit(u64 config) 158*a072738eSCyrill Gorcunov { 159*a072738eSCyrill Gorcunov return config | P4_CONFIG_HT; 160*a072738eSCyrill Gorcunov } 161*a072738eSCyrill Gorcunov 162*a072738eSCyrill Gorcunov static inline u64 p4_clear_ht_bit(u64 config) 163*a072738eSCyrill Gorcunov { 164*a072738eSCyrill Gorcunov return config & ~P4_CONFIG_HT; 165*a072738eSCyrill Gorcunov } 166*a072738eSCyrill Gorcunov 167*a072738eSCyrill Gorcunov static inline int p4_ht_active(void) 168*a072738eSCyrill Gorcunov { 169*a072738eSCyrill Gorcunov #ifdef CONFIG_SMP 170*a072738eSCyrill Gorcunov return smp_num_siblings > 1; 171*a072738eSCyrill Gorcunov #endif 172*a072738eSCyrill Gorcunov return 0; 173*a072738eSCyrill Gorcunov } 174*a072738eSCyrill Gorcunov 175*a072738eSCyrill Gorcunov static inline int p4_ht_thread(int cpu) 176*a072738eSCyrill Gorcunov { 177*a072738eSCyrill Gorcunov #ifdef CONFIG_SMP 178*a072738eSCyrill Gorcunov if (smp_num_siblings == 2) 179*a072738eSCyrill Gorcunov return cpu != cpumask_first(__get_cpu_var(cpu_sibling_map)); 180*a072738eSCyrill Gorcunov #endif 181*a072738eSCyrill Gorcunov return 0; 182*a072738eSCyrill Gorcunov } 183*a072738eSCyrill Gorcunov 184*a072738eSCyrill Gorcunov static inline int p4_should_swap_ts(u64 config, int cpu) 185*a072738eSCyrill Gorcunov { 186*a072738eSCyrill Gorcunov return p4_ht_config_thread(config) ^ p4_ht_thread(cpu); 187*a072738eSCyrill Gorcunov } 188*a072738eSCyrill Gorcunov 189*a072738eSCyrill Gorcunov static inline u32 p4_default_cccr_conf(int cpu) 190*a072738eSCyrill Gorcunov { 191*a072738eSCyrill Gorcunov /* 192*a072738eSCyrill Gorcunov * Note that P4_CCCR_THREAD_ANY is "required" on 193*a072738eSCyrill Gorcunov * non-HT machines (on HT machines we count TS events 194*a072738eSCyrill Gorcunov * regardless the state of second logical processor 195*a072738eSCyrill Gorcunov */ 196*a072738eSCyrill Gorcunov u32 cccr = P4_CCCR_THREAD_ANY; 197*a072738eSCyrill Gorcunov 198*a072738eSCyrill Gorcunov if (!p4_ht_thread(cpu)) 199*a072738eSCyrill Gorcunov cccr |= P4_CCCR_OVF_PMI_T0; 200*a072738eSCyrill Gorcunov else 201*a072738eSCyrill Gorcunov cccr |= P4_CCCR_OVF_PMI_T1; 202*a072738eSCyrill Gorcunov 203*a072738eSCyrill Gorcunov return cccr; 204*a072738eSCyrill Gorcunov } 205*a072738eSCyrill Gorcunov 206*a072738eSCyrill Gorcunov static inline u32 p4_default_escr_conf(int cpu, int exclude_os, int exclude_usr) 207*a072738eSCyrill Gorcunov { 208*a072738eSCyrill Gorcunov u32 escr = 0; 209*a072738eSCyrill Gorcunov 210*a072738eSCyrill Gorcunov if (!p4_ht_thread(cpu)) { 211*a072738eSCyrill Gorcunov if (!exclude_os) 212*a072738eSCyrill Gorcunov escr |= P4_EVNTSEL_T0_OS; 213*a072738eSCyrill Gorcunov if (!exclude_usr) 214*a072738eSCyrill Gorcunov escr |= P4_EVNTSEL_T0_USR; 215*a072738eSCyrill Gorcunov } else { 216*a072738eSCyrill Gorcunov if (!exclude_os) 217*a072738eSCyrill Gorcunov escr |= P4_EVNTSEL_T1_OS; 218*a072738eSCyrill Gorcunov if (!exclude_usr) 219*a072738eSCyrill Gorcunov escr |= P4_EVNTSEL_T1_USR; 220*a072738eSCyrill Gorcunov } 221*a072738eSCyrill Gorcunov 222*a072738eSCyrill Gorcunov return escr; 223*a072738eSCyrill Gorcunov } 224*a072738eSCyrill Gorcunov 225*a072738eSCyrill Gorcunov /* 226*a072738eSCyrill Gorcunov * Comments below the event represent ESCR restriction 227*a072738eSCyrill Gorcunov * for this event and counter index per ESCR 228*a072738eSCyrill Gorcunov * 229*a072738eSCyrill Gorcunov * MSR_P4_IQ_ESCR0 and MSR_P4_IQ_ESCR1 are available only on early 230*a072738eSCyrill Gorcunov * processor builds (family 0FH, models 01H-02H). These MSRs 231*a072738eSCyrill Gorcunov * are not available on later versions, so that we don't use 232*a072738eSCyrill Gorcunov * them completely 233*a072738eSCyrill Gorcunov * 234*a072738eSCyrill Gorcunov * Also note that CCCR1 do not have P4_CCCR_ENABLE bit properly 235*a072738eSCyrill Gorcunov * working so that we should not use this CCCR and respective 236*a072738eSCyrill Gorcunov * counter as result 237*a072738eSCyrill Gorcunov */ 238*a072738eSCyrill Gorcunov #define P4_TC_DELIVER_MODE P4_EVENT_PACK(0x01, 0x01) 239*a072738eSCyrill Gorcunov /* 240*a072738eSCyrill Gorcunov * MSR_P4_TC_ESCR0: 4, 5 241*a072738eSCyrill Gorcunov * MSR_P4_TC_ESCR1: 6, 7 242*a072738eSCyrill Gorcunov */ 243*a072738eSCyrill Gorcunov 244*a072738eSCyrill Gorcunov #define P4_BPU_FETCH_REQUEST P4_EVENT_PACK(0x03, 0x00) 245*a072738eSCyrill Gorcunov /* 246*a072738eSCyrill Gorcunov * MSR_P4_BPU_ESCR0: 0, 1 247*a072738eSCyrill Gorcunov * MSR_P4_BPU_ESCR1: 2, 3 248*a072738eSCyrill Gorcunov */ 249*a072738eSCyrill Gorcunov 250*a072738eSCyrill Gorcunov #define P4_ITLB_REFERENCE P4_EVENT_PACK(0x18, 0x03) 251*a072738eSCyrill Gorcunov /* 252*a072738eSCyrill Gorcunov * MSR_P4_ITLB_ESCR0: 0, 1 253*a072738eSCyrill Gorcunov * MSR_P4_ITLB_ESCR1: 2, 3 254*a072738eSCyrill Gorcunov */ 255*a072738eSCyrill Gorcunov 256*a072738eSCyrill Gorcunov #define P4_MEMORY_CANCEL P4_EVENT_PACK(0x02, 0x05) 257*a072738eSCyrill Gorcunov /* 258*a072738eSCyrill Gorcunov * MSR_P4_DAC_ESCR0: 8, 9 259*a072738eSCyrill Gorcunov * MSR_P4_DAC_ESCR1: 10, 11 260*a072738eSCyrill Gorcunov */ 261*a072738eSCyrill Gorcunov 262*a072738eSCyrill Gorcunov #define P4_MEMORY_COMPLETE P4_EVENT_PACK(0x08, 0x02) 263*a072738eSCyrill Gorcunov /* 264*a072738eSCyrill Gorcunov * MSR_P4_SAAT_ESCR0: 8, 9 265*a072738eSCyrill Gorcunov * MSR_P4_SAAT_ESCR1: 10, 11 266*a072738eSCyrill Gorcunov */ 267*a072738eSCyrill Gorcunov 268*a072738eSCyrill Gorcunov #define P4_LOAD_PORT_REPLAY P4_EVENT_PACK(0x04, 0x02) 269*a072738eSCyrill Gorcunov /* 270*a072738eSCyrill Gorcunov * MSR_P4_SAAT_ESCR0: 8, 9 271*a072738eSCyrill Gorcunov * MSR_P4_SAAT_ESCR1: 10, 11 272*a072738eSCyrill Gorcunov */ 273*a072738eSCyrill Gorcunov 274*a072738eSCyrill Gorcunov #define P4_STORE_PORT_REPLAY P4_EVENT_PACK(0x05, 0x02) 275*a072738eSCyrill Gorcunov /* 276*a072738eSCyrill Gorcunov * MSR_P4_SAAT_ESCR0: 8, 9 277*a072738eSCyrill Gorcunov * MSR_P4_SAAT_ESCR1: 10, 11 278*a072738eSCyrill Gorcunov */ 279*a072738eSCyrill Gorcunov 280*a072738eSCyrill Gorcunov #define P4_MOB_LOAD_REPLAY P4_EVENT_PACK(0x03, 0x02) 281*a072738eSCyrill Gorcunov /* 282*a072738eSCyrill Gorcunov * MSR_P4_MOB_ESCR0: 0, 1 283*a072738eSCyrill Gorcunov * MSR_P4_MOB_ESCR1: 2, 3 284*a072738eSCyrill Gorcunov */ 285*a072738eSCyrill Gorcunov 286*a072738eSCyrill Gorcunov #define P4_PAGE_WALK_TYPE P4_EVENT_PACK(0x01, 0x04) 287*a072738eSCyrill Gorcunov /* 288*a072738eSCyrill Gorcunov * MSR_P4_PMH_ESCR0: 0, 1 289*a072738eSCyrill Gorcunov * MSR_P4_PMH_ESCR1: 2, 3 290*a072738eSCyrill Gorcunov */ 291*a072738eSCyrill Gorcunov 292*a072738eSCyrill Gorcunov #define P4_BSQ_CACHE_REFERENCE P4_EVENT_PACK(0x0c, 0x07) 293*a072738eSCyrill Gorcunov /* 294*a072738eSCyrill Gorcunov * MSR_P4_BSU_ESCR0: 0, 1 295*a072738eSCyrill Gorcunov * MSR_P4_BSU_ESCR1: 2, 3 296*a072738eSCyrill Gorcunov */ 297*a072738eSCyrill Gorcunov 298*a072738eSCyrill Gorcunov #define P4_IOQ_ALLOCATION P4_EVENT_PACK(0x03, 0x06) 299*a072738eSCyrill Gorcunov /* 300*a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR0: 0, 1 301*a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR1: 2, 3 302*a072738eSCyrill Gorcunov */ 303*a072738eSCyrill Gorcunov 304*a072738eSCyrill Gorcunov #define P4_IOQ_ACTIVE_ENTRIES P4_EVENT_PACK(0x1a, 0x06) 305*a072738eSCyrill Gorcunov /* 306*a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR1: 2, 3 307*a072738eSCyrill Gorcunov */ 308*a072738eSCyrill Gorcunov 309*a072738eSCyrill Gorcunov #define P4_FSB_DATA_ACTIVITY P4_EVENT_PACK(0x17, 0x06) 310*a072738eSCyrill Gorcunov /* 311*a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR0: 0, 1 312*a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR1: 2, 3 313*a072738eSCyrill Gorcunov */ 314*a072738eSCyrill Gorcunov 315*a072738eSCyrill Gorcunov #define P4_BSQ_ALLOCATION P4_EVENT_PACK(0x05, 0x07) 316*a072738eSCyrill Gorcunov /* 317*a072738eSCyrill Gorcunov * MSR_P4_BSU_ESCR0: 0, 1 318*a072738eSCyrill Gorcunov */ 319*a072738eSCyrill Gorcunov 320*a072738eSCyrill Gorcunov #define P4_BSQ_ACTIVE_ENTRIES P4_EVENT_PACK(0x06, 0x07) 321*a072738eSCyrill Gorcunov /* 322*a072738eSCyrill Gorcunov * MSR_P4_BSU_ESCR1: 2, 3 323*a072738eSCyrill Gorcunov */ 324*a072738eSCyrill Gorcunov 325*a072738eSCyrill Gorcunov #define P4_SSE_INPUT_ASSIST P4_EVENT_PACK(0x34, 0x01) 326*a072738eSCyrill Gorcunov /* 327*a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR: 8, 9 328*a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR: 10, 11 329*a072738eSCyrill Gorcunov */ 330*a072738eSCyrill Gorcunov 331*a072738eSCyrill Gorcunov #define P4_PACKED_SP_UOP P4_EVENT_PACK(0x08, 0x01) 332*a072738eSCyrill Gorcunov /* 333*a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR0: 8, 9 334*a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR1: 10, 11 335*a072738eSCyrill Gorcunov */ 336*a072738eSCyrill Gorcunov 337*a072738eSCyrill Gorcunov #define P4_PACKED_DP_UOP P4_EVENT_PACK(0x0c, 0x01) 338*a072738eSCyrill Gorcunov /* 339*a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR0: 8, 9 340*a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR1: 10, 11 341*a072738eSCyrill Gorcunov */ 342*a072738eSCyrill Gorcunov 343*a072738eSCyrill Gorcunov #define P4_SCALAR_SP_UOP P4_EVENT_PACK(0x0a, 0x01) 344*a072738eSCyrill Gorcunov /* 345*a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR0: 8, 9 346*a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR1: 10, 11 347*a072738eSCyrill Gorcunov */ 348*a072738eSCyrill Gorcunov 349*a072738eSCyrill Gorcunov #define P4_SCALAR_DP_UOP P4_EVENT_PACK(0x0e, 0x01) 350*a072738eSCyrill Gorcunov /* 351*a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR0: 8, 9 352*a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR1: 10, 11 353*a072738eSCyrill Gorcunov */ 354*a072738eSCyrill Gorcunov 355*a072738eSCyrill Gorcunov #define P4_64BIT_MMX_UOP P4_EVENT_PACK(0x02, 0x01) 356*a072738eSCyrill Gorcunov /* 357*a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR0: 8, 9 358*a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR1: 10, 11 359*a072738eSCyrill Gorcunov */ 360*a072738eSCyrill Gorcunov 361*a072738eSCyrill Gorcunov #define P4_128BIT_MMX_UOP P4_EVENT_PACK(0x1a, 0x01) 362*a072738eSCyrill Gorcunov /* 363*a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR0: 8, 9 364*a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR1: 10, 11 365*a072738eSCyrill Gorcunov */ 366*a072738eSCyrill Gorcunov 367*a072738eSCyrill Gorcunov #define P4_X87_FP_UOP P4_EVENT_PACK(0x04, 0x01) 368*a072738eSCyrill Gorcunov /* 369*a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR0: 8, 9 370*a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR1: 10, 11 371*a072738eSCyrill Gorcunov */ 372*a072738eSCyrill Gorcunov 373*a072738eSCyrill Gorcunov #define P4_TC_MISC P4_EVENT_PACK(0x06, 0x01) 374*a072738eSCyrill Gorcunov /* 375*a072738eSCyrill Gorcunov * MSR_P4_TC_ESCR0: 4, 5 376*a072738eSCyrill Gorcunov * MSR_P4_TC_ESCR1: 6, 7 377*a072738eSCyrill Gorcunov */ 378*a072738eSCyrill Gorcunov 379*a072738eSCyrill Gorcunov #define P4_GLOBAL_POWER_EVENTS P4_EVENT_PACK(0x13, 0x06) 380*a072738eSCyrill Gorcunov /* 381*a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR0: 0, 1 382*a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR1: 2, 3 383*a072738eSCyrill Gorcunov */ 384*a072738eSCyrill Gorcunov 385*a072738eSCyrill Gorcunov #define P4_TC_MS_XFER P4_EVENT_PACK(0x05, 0x00) 386*a072738eSCyrill Gorcunov /* 387*a072738eSCyrill Gorcunov * MSR_P4_MS_ESCR0: 4, 5 388*a072738eSCyrill Gorcunov * MSR_P4_MS_ESCR1: 6, 7 389*a072738eSCyrill Gorcunov */ 390*a072738eSCyrill Gorcunov 391*a072738eSCyrill Gorcunov #define P4_UOP_QUEUE_WRITES P4_EVENT_PACK(0x09, 0x00) 392*a072738eSCyrill Gorcunov /* 393*a072738eSCyrill Gorcunov * MSR_P4_MS_ESCR0: 4, 5 394*a072738eSCyrill Gorcunov * MSR_P4_MS_ESCR1: 6, 7 395*a072738eSCyrill Gorcunov */ 396*a072738eSCyrill Gorcunov 397*a072738eSCyrill Gorcunov #define P4_RETIRED_MISPRED_BRANCH_TYPE P4_EVENT_PACK(0x05, 0x02) 398*a072738eSCyrill Gorcunov /* 399*a072738eSCyrill Gorcunov * MSR_P4_TBPU_ESCR0: 4, 5 400*a072738eSCyrill Gorcunov * MSR_P4_TBPU_ESCR0: 6, 7 401*a072738eSCyrill Gorcunov */ 402*a072738eSCyrill Gorcunov 403*a072738eSCyrill Gorcunov #define P4_RETIRED_BRANCH_TYPE P4_EVENT_PACK(0x04, 0x02) 404*a072738eSCyrill Gorcunov /* 405*a072738eSCyrill Gorcunov * MSR_P4_TBPU_ESCR0: 4, 5 406*a072738eSCyrill Gorcunov * MSR_P4_TBPU_ESCR0: 6, 7 407*a072738eSCyrill Gorcunov */ 408*a072738eSCyrill Gorcunov 409*a072738eSCyrill Gorcunov #define P4_RESOURCE_STALL P4_EVENT_PACK(0x01, 0x01) 410*a072738eSCyrill Gorcunov /* 411*a072738eSCyrill Gorcunov * MSR_P4_ALF_ESCR0: 12, 13, 16 412*a072738eSCyrill Gorcunov * MSR_P4_ALF_ESCR1: 14, 15, 17 413*a072738eSCyrill Gorcunov */ 414*a072738eSCyrill Gorcunov 415*a072738eSCyrill Gorcunov #define P4_WC_BUFFER P4_EVENT_PACK(0x05, 0x05) 416*a072738eSCyrill Gorcunov /* 417*a072738eSCyrill Gorcunov * MSR_P4_DAC_ESCR0: 8, 9 418*a072738eSCyrill Gorcunov * MSR_P4_DAC_ESCR1: 10, 11 419*a072738eSCyrill Gorcunov */ 420*a072738eSCyrill Gorcunov 421*a072738eSCyrill Gorcunov #define P4_B2B_CYCLES P4_EVENT_PACK(0x16, 0x03) 422*a072738eSCyrill Gorcunov /* 423*a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR0: 0, 1 424*a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR1: 2, 3 425*a072738eSCyrill Gorcunov */ 426*a072738eSCyrill Gorcunov 427*a072738eSCyrill Gorcunov #define P4_BNR P4_EVENT_PACK(0x08, 0x03) 428*a072738eSCyrill Gorcunov /* 429*a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR0: 0, 1 430*a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR1: 2, 3 431*a072738eSCyrill Gorcunov */ 432*a072738eSCyrill Gorcunov 433*a072738eSCyrill Gorcunov #define P4_SNOOP P4_EVENT_PACK(0x06, 0x03) 434*a072738eSCyrill Gorcunov /* 435*a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR0: 0, 1 436*a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR1: 2, 3 437*a072738eSCyrill Gorcunov */ 438*a072738eSCyrill Gorcunov 439*a072738eSCyrill Gorcunov #define P4_RESPONSE P4_EVENT_PACK(0x04, 0x03) 440*a072738eSCyrill Gorcunov /* 441*a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR0: 0, 1 442*a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR1: 2, 3 443*a072738eSCyrill Gorcunov */ 444*a072738eSCyrill Gorcunov 445*a072738eSCyrill Gorcunov #define P4_FRONT_END_EVENT P4_EVENT_PACK(0x08, 0x05) 446*a072738eSCyrill Gorcunov /* 447*a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR2: 12, 13, 16 448*a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR3: 14, 15, 17 449*a072738eSCyrill Gorcunov */ 450*a072738eSCyrill Gorcunov 451*a072738eSCyrill Gorcunov #define P4_EXECUTION_EVENT P4_EVENT_PACK(0x0c, 0x05) 452*a072738eSCyrill Gorcunov /* 453*a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR2: 12, 13, 16 454*a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR3: 14, 15, 17 455*a072738eSCyrill Gorcunov */ 456*a072738eSCyrill Gorcunov 457*a072738eSCyrill Gorcunov #define P4_REPLAY_EVENT P4_EVENT_PACK(0x09, 0x05) 458*a072738eSCyrill Gorcunov /* 459*a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR2: 12, 13, 16 460*a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR3: 14, 15, 17 461*a072738eSCyrill Gorcunov */ 462*a072738eSCyrill Gorcunov 463*a072738eSCyrill Gorcunov #define P4_INSTR_RETIRED P4_EVENT_PACK(0x02, 0x04) 464*a072738eSCyrill Gorcunov /* 465*a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR2: 12, 13, 16 466*a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR3: 14, 15, 17 467*a072738eSCyrill Gorcunov */ 468*a072738eSCyrill Gorcunov 469*a072738eSCyrill Gorcunov #define P4_UOPS_RETIRED P4_EVENT_PACK(0x01, 0x04) 470*a072738eSCyrill Gorcunov /* 471*a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR2: 12, 13, 16 472*a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR3: 14, 15, 17 473*a072738eSCyrill Gorcunov */ 474*a072738eSCyrill Gorcunov 475*a072738eSCyrill Gorcunov #define P4_UOP_TYPE P4_EVENT_PACK(0x02, 0x02) 476*a072738eSCyrill Gorcunov /* 477*a072738eSCyrill Gorcunov * MSR_P4_RAT_ESCR0: 12, 13, 16 478*a072738eSCyrill Gorcunov * MSR_P4_RAT_ESCR1: 14, 15, 17 479*a072738eSCyrill Gorcunov */ 480*a072738eSCyrill Gorcunov 481*a072738eSCyrill Gorcunov #define P4_BRANCH_RETIRED P4_EVENT_PACK(0x06, 0x05) 482*a072738eSCyrill Gorcunov /* 483*a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR2: 12, 13, 16 484*a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR3: 14, 15, 17 485*a072738eSCyrill Gorcunov */ 486*a072738eSCyrill Gorcunov 487*a072738eSCyrill Gorcunov #define P4_MISPRED_BRANCH_RETIRED P4_EVENT_PACK(0x03, 0x04) 488*a072738eSCyrill Gorcunov /* 489*a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR0: 12, 13, 16 490*a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR1: 14, 15, 17 491*a072738eSCyrill Gorcunov */ 492*a072738eSCyrill Gorcunov 493*a072738eSCyrill Gorcunov #define P4_X87_ASSIST P4_EVENT_PACK(0x03, 0x05) 494*a072738eSCyrill Gorcunov /* 495*a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR2: 12, 13, 16 496*a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR3: 14, 15, 17 497*a072738eSCyrill Gorcunov */ 498*a072738eSCyrill Gorcunov 499*a072738eSCyrill Gorcunov #define P4_MACHINE_CLEAR P4_EVENT_PACK(0x02, 0x05) 500*a072738eSCyrill Gorcunov /* 501*a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR2: 12, 13, 16 502*a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR3: 14, 15, 17 503*a072738eSCyrill Gorcunov */ 504*a072738eSCyrill Gorcunov 505*a072738eSCyrill Gorcunov #define P4_INSTR_COMPLETED P4_EVENT_PACK(0x07, 0x04) 506*a072738eSCyrill Gorcunov /* 507*a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR0: 12, 13, 16 508*a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR1: 14, 15, 17 509*a072738eSCyrill Gorcunov */ 510*a072738eSCyrill Gorcunov 511*a072738eSCyrill Gorcunov /* 512*a072738eSCyrill Gorcunov * a caller should use P4_EVENT_ATTR helper to 513*a072738eSCyrill Gorcunov * pick the attribute needed, for example 514*a072738eSCyrill Gorcunov * 515*a072738eSCyrill Gorcunov * P4_EVENT_ATTR(P4_TC_DELIVER_MODE, DD) 516*a072738eSCyrill Gorcunov */ 517*a072738eSCyrill Gorcunov enum P4_EVENTS_ATTR { 518*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_TC_DELIVER_MODE, DD, 0), 519*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_TC_DELIVER_MODE, DB, 1), 520*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_TC_DELIVER_MODE, DI, 2), 521*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_TC_DELIVER_MODE, BD, 3), 522*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_TC_DELIVER_MODE, BB, 4), 523*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_TC_DELIVER_MODE, BI, 5), 524*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_TC_DELIVER_MODE, ID, 6), 525*a072738eSCyrill Gorcunov 526*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_BPU_FETCH_REQUEST, TCMISS, 0), 527*a072738eSCyrill Gorcunov 528*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_ITLB_REFERENCE, HIT, 0), 529*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_ITLB_REFERENCE, MISS, 1), 530*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_ITLB_REFERENCE, HIT_UK, 2), 531*a072738eSCyrill Gorcunov 532*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_MEMORY_CANCEL, ST_RB_FULL, 2), 533*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_MEMORY_CANCEL, 64K_CONF, 3), 534*a072738eSCyrill Gorcunov 535*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_MEMORY_COMPLETE, LSC, 0), 536*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_MEMORY_COMPLETE, SSC, 1), 537*a072738eSCyrill Gorcunov 538*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_LOAD_PORT_REPLAY, SPLIT_LD, 1), 539*a072738eSCyrill Gorcunov 540*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_STORE_PORT_REPLAY, SPLIT_ST, 1), 541*a072738eSCyrill Gorcunov 542*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_MOB_LOAD_REPLAY, NO_STA, 1), 543*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_MOB_LOAD_REPLAY, NO_STD, 3), 544*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_MOB_LOAD_REPLAY, PARTIAL_DATA, 4), 545*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_MOB_LOAD_REPLAY, UNALGN_ADDR, 5), 546*a072738eSCyrill Gorcunov 547*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_PAGE_WALK_TYPE, DTMISS, 0), 548*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_PAGE_WALK_TYPE, ITMISS, 1), 549*a072738eSCyrill Gorcunov 550*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_BSQ_CACHE_REFERENCE, RD_2ndL_HITS, 0), 551*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_BSQ_CACHE_REFERENCE, RD_2ndL_HITE, 1), 552*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_BSQ_CACHE_REFERENCE, RD_2ndL_HITM, 2), 553*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_BSQ_CACHE_REFERENCE, RD_3rdL_HITS, 3), 554*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_BSQ_CACHE_REFERENCE, RD_3rdL_HITE, 4), 555*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_BSQ_CACHE_REFERENCE, RD_3rdL_HITM, 5), 556*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_BSQ_CACHE_REFERENCE, RD_2ndL_MISS, 8), 557*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_BSQ_CACHE_REFERENCE, RD_3rdL_MISS, 9), 558*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_BSQ_CACHE_REFERENCE, WR_2ndL_MISS, 10), 559*a072738eSCyrill Gorcunov 560*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_IOQ_ALLOCATION, DEFAULT, 0), 561*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_IOQ_ALLOCATION, ALL_READ, 5), 562*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_IOQ_ALLOCATION, ALL_WRITE, 6), 563*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_IOQ_ALLOCATION, MEM_UC, 7), 564*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_IOQ_ALLOCATION, MEM_WC, 8), 565*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_IOQ_ALLOCATION, MEM_WT, 9), 566*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_IOQ_ALLOCATION, MEM_WP, 10), 567*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_IOQ_ALLOCATION, MEM_WB, 11), 568*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_IOQ_ALLOCATION, OWN, 13), 569*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_IOQ_ALLOCATION, OTHER, 14), 570*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_IOQ_ALLOCATION, PREFETCH, 15), 571*a072738eSCyrill Gorcunov 572*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_IOQ_ACTIVE_ENTRIES, DEFAULT, 0), 573*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_IOQ_ACTIVE_ENTRIES, ALL_READ, 5), 574*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_IOQ_ACTIVE_ENTRIES, ALL_WRITE, 6), 575*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_IOQ_ACTIVE_ENTRIES, MEM_UC, 7), 576*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_IOQ_ACTIVE_ENTRIES, MEM_WC, 8), 577*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_IOQ_ACTIVE_ENTRIES, MEM_WT, 9), 578*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_IOQ_ACTIVE_ENTRIES, MEM_WP, 10), 579*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_IOQ_ACTIVE_ENTRIES, MEM_WB, 11), 580*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_IOQ_ACTIVE_ENTRIES, OWN, 13), 581*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_IOQ_ACTIVE_ENTRIES, OTHER, 14), 582*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_IOQ_ACTIVE_ENTRIES, PREFETCH, 15), 583*a072738eSCyrill Gorcunov 584*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_FSB_DATA_ACTIVITY, DRDY_DRV, 0), 585*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_FSB_DATA_ACTIVITY, DRDY_OWN, 1), 586*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_FSB_DATA_ACTIVITY, DRDY_OTHER, 2), 587*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_FSB_DATA_ACTIVITY, DBSY_DRV, 3), 588*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_FSB_DATA_ACTIVITY, DBSY_OWN, 4), 589*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_FSB_DATA_ACTIVITY, DBSY_OTHER, 5), 590*a072738eSCyrill Gorcunov 591*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_BSQ_ALLOCATION, REQ_TYPE0, 0), 592*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_BSQ_ALLOCATION, REQ_TYPE1, 1), 593*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_BSQ_ALLOCATION, REQ_LEN0, 2), 594*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_BSQ_ALLOCATION, REQ_LEN1, 3), 595*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_BSQ_ALLOCATION, REQ_IO_TYPE, 5), 596*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_BSQ_ALLOCATION, REQ_LOCK_TYPE, 6), 597*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_BSQ_ALLOCATION, REQ_CACHE_TYPE, 7), 598*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_BSQ_ALLOCATION, REQ_SPLIT_TYPE, 8), 599*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_BSQ_ALLOCATION, REQ_DEM_TYPE, 9), 600*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_BSQ_ALLOCATION, REQ_ORD_TYPE, 10), 601*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_BSQ_ALLOCATION, MEM_TYPE0, 11), 602*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_BSQ_ALLOCATION, MEM_TYPE1, 12), 603*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_BSQ_ALLOCATION, MEM_TYPE2, 13), 604*a072738eSCyrill Gorcunov 605*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_BSQ_ACTIVE_ENTRIES, REQ_TYPE0, 0), 606*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_BSQ_ACTIVE_ENTRIES, REQ_TYPE1, 1), 607*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_BSQ_ACTIVE_ENTRIES, REQ_LEN0, 2), 608*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_BSQ_ACTIVE_ENTRIES, REQ_LEN1, 3), 609*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_BSQ_ACTIVE_ENTRIES, REQ_IO_TYPE, 5), 610*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_BSQ_ACTIVE_ENTRIES, REQ_LOCK_TYPE, 6), 611*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_BSQ_ACTIVE_ENTRIES, REQ_CACHE_TYPE, 7), 612*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_BSQ_ACTIVE_ENTRIES, REQ_SPLIT_TYPE, 8), 613*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_BSQ_ACTIVE_ENTRIES, REQ_DEM_TYPE, 9), 614*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_BSQ_ACTIVE_ENTRIES, REQ_ORD_TYPE, 10), 615*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_BSQ_ACTIVE_ENTRIES, MEM_TYPE0, 11), 616*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_BSQ_ACTIVE_ENTRIES, MEM_TYPE1, 12), 617*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_BSQ_ACTIVE_ENTRIES, MEM_TYPE2, 13), 618*a072738eSCyrill Gorcunov 619*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_SSE_INPUT_ASSIST, ALL, 15), 620*a072738eSCyrill Gorcunov 621*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_PACKED_SP_UOP, ALL, 15), 622*a072738eSCyrill Gorcunov 623*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_PACKED_DP_UOP, ALL, 15), 624*a072738eSCyrill Gorcunov 625*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_SCALAR_SP_UOP, ALL, 15), 626*a072738eSCyrill Gorcunov 627*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_SCALAR_DP_UOP, ALL, 15), 628*a072738eSCyrill Gorcunov 629*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_64BIT_MMX_UOP, ALL, 15), 630*a072738eSCyrill Gorcunov 631*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_128BIT_MMX_UOP, ALL, 15), 632*a072738eSCyrill Gorcunov 633*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_X87_FP_UOP, ALL, 15), 634*a072738eSCyrill Gorcunov 635*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_TC_MISC, FLUSH, 4), 636*a072738eSCyrill Gorcunov 637*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_GLOBAL_POWER_EVENTS, RUNNING, 0), 638*a072738eSCyrill Gorcunov 639*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_TC_MS_XFER, CISC, 0), 640*a072738eSCyrill Gorcunov 641*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_UOP_QUEUE_WRITES, FROM_TC_BUILD, 0), 642*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_UOP_QUEUE_WRITES, FROM_TC_DELIVER, 1), 643*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_UOP_QUEUE_WRITES, FROM_ROM, 2), 644*a072738eSCyrill Gorcunov 645*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_RETIRED_MISPRED_BRANCH_TYPE, CONDITIONAL, 1), 646*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_RETIRED_MISPRED_BRANCH_TYPE, CALL, 2), 647*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_RETIRED_MISPRED_BRANCH_TYPE, RETURN, 3), 648*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_RETIRED_MISPRED_BRANCH_TYPE, INDIRECT, 4), 649*a072738eSCyrill Gorcunov 650*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_RETIRED_BRANCH_TYPE, CONDITIONAL, 1), 651*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_RETIRED_BRANCH_TYPE, CALL, 2), 652*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_RETIRED_BRANCH_TYPE, RETURN, 3), 653*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_RETIRED_BRANCH_TYPE, INDIRECT, 4), 654*a072738eSCyrill Gorcunov 655*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_RESOURCE_STALL, SBFULL, 5), 656*a072738eSCyrill Gorcunov 657*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_WC_BUFFER, WCB_EVICTS, 0), 658*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_WC_BUFFER, WCB_FULL_EVICTS, 1), 659*a072738eSCyrill Gorcunov 660*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_FRONT_END_EVENT, NBOGUS, 0), 661*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_FRONT_END_EVENT, BOGUS, 1), 662*a072738eSCyrill Gorcunov 663*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_EXECUTION_EVENT, NBOGUS0, 0), 664*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_EXECUTION_EVENT, NBOGUS1, 1), 665*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_EXECUTION_EVENT, NBOGUS2, 2), 666*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_EXECUTION_EVENT, NBOGUS3, 3), 667*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_EXECUTION_EVENT, BOGUS0, 4), 668*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_EXECUTION_EVENT, BOGUS1, 5), 669*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_EXECUTION_EVENT, BOGUS2, 6), 670*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_EXECUTION_EVENT, BOGUS3, 7), 671*a072738eSCyrill Gorcunov 672*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_REPLAY_EVENT, NBOGUS, 0), 673*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_REPLAY_EVENT, BOGUS, 1), 674*a072738eSCyrill Gorcunov 675*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_INSTR_RETIRED, NBOGUSNTAG, 0), 676*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_INSTR_RETIRED, NBOGUSTAG, 1), 677*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_INSTR_RETIRED, BOGUSNTAG, 2), 678*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_INSTR_RETIRED, BOGUSTAG, 3), 679*a072738eSCyrill Gorcunov 680*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_UOPS_RETIRED, NBOGUS, 0), 681*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_UOPS_RETIRED, BOGUS, 1), 682*a072738eSCyrill Gorcunov 683*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_UOP_TYPE, TAGLOADS, 1), 684*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_UOP_TYPE, TAGSTORES, 2), 685*a072738eSCyrill Gorcunov 686*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_BRANCH_RETIRED, MMNP, 0), 687*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_BRANCH_RETIRED, MMNM, 1), 688*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_BRANCH_RETIRED, MMTP, 2), 689*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_BRANCH_RETIRED, MMTM, 3), 690*a072738eSCyrill Gorcunov 691*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_MISPRED_BRANCH_RETIRED, NBOGUS, 0), 692*a072738eSCyrill Gorcunov 693*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_X87_ASSIST, FPSU, 0), 694*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_X87_ASSIST, FPSO, 1), 695*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_X87_ASSIST, POAO, 2), 696*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_X87_ASSIST, POAU, 3), 697*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_X87_ASSIST, PREA, 4), 698*a072738eSCyrill Gorcunov 699*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_MACHINE_CLEAR, CLEAR, 0), 700*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_MACHINE_CLEAR, MOCLEAR, 1), 701*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_MACHINE_CLEAR, SMCLEAR, 2), 702*a072738eSCyrill Gorcunov 703*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_INSTR_COMPLETED, NBOGUS, 0), 704*a072738eSCyrill Gorcunov P4_MAKE_EVENT_ATTR(P4_INSTR_COMPLETED, BOGUS, 1), 705*a072738eSCyrill Gorcunov }; 706*a072738eSCyrill Gorcunov 707*a072738eSCyrill Gorcunov #endif /* PERF_EVENT_P4_H */ 708