1a072738eSCyrill Gorcunov /* 2a072738eSCyrill Gorcunov * Netburst Perfomance Events (P4, old Xeon) 3a072738eSCyrill Gorcunov */ 4a072738eSCyrill Gorcunov 5a072738eSCyrill Gorcunov #ifndef PERF_EVENT_P4_H 6a072738eSCyrill Gorcunov #define PERF_EVENT_P4_H 7a072738eSCyrill Gorcunov 8a072738eSCyrill Gorcunov #include <linux/cpu.h> 9a072738eSCyrill Gorcunov #include <linux/bitops.h> 10a072738eSCyrill Gorcunov 11a072738eSCyrill Gorcunov /* 12a072738eSCyrill Gorcunov * NetBurst has perfomance MSRs shared between 13a072738eSCyrill Gorcunov * threads if HT is turned on, ie for both logical 14a072738eSCyrill Gorcunov * processors (mem: in turn in Atom with HT support 15a072738eSCyrill Gorcunov * perf-MSRs are not shared and every thread has its 16a072738eSCyrill Gorcunov * own perf-MSRs set) 17a072738eSCyrill Gorcunov */ 18a072738eSCyrill Gorcunov #define ARCH_P4_TOTAL_ESCR (46) 19a072738eSCyrill Gorcunov #define ARCH_P4_RESERVED_ESCR (2) /* IQ_ESCR(0,1) not always present */ 20a072738eSCyrill Gorcunov #define ARCH_P4_MAX_ESCR (ARCH_P4_TOTAL_ESCR - ARCH_P4_RESERVED_ESCR) 21a072738eSCyrill Gorcunov #define ARCH_P4_MAX_CCCR (18) 22a072738eSCyrill Gorcunov 23d814f301SCyrill Gorcunov #define P4_ESCR_EVENT_MASK 0x7e000000U 24d814f301SCyrill Gorcunov #define P4_ESCR_EVENT_SHIFT 25 25d814f301SCyrill Gorcunov #define P4_ESCR_EVENTMASK_MASK 0x01fffe00U 26d814f301SCyrill Gorcunov #define P4_ESCR_EVENTMASK_SHIFT 9 27d814f301SCyrill Gorcunov #define P4_ESCR_TAG_MASK 0x000001e0U 28d814f301SCyrill Gorcunov #define P4_ESCR_TAG_SHIFT 5 29d814f301SCyrill Gorcunov #define P4_ESCR_TAG_ENABLE 0x00000010U 30d814f301SCyrill Gorcunov #define P4_ESCR_T0_OS 0x00000008U 31d814f301SCyrill Gorcunov #define P4_ESCR_T0_USR 0x00000004U 32d814f301SCyrill Gorcunov #define P4_ESCR_T1_OS 0x00000002U 33d814f301SCyrill Gorcunov #define P4_ESCR_T1_USR 0x00000001U 34d814f301SCyrill Gorcunov 35d814f301SCyrill Gorcunov #define P4_ESCR_EVENT(v) ((v) << P4_ESCR_EVENT_SHIFT) 36d814f301SCyrill Gorcunov #define P4_ESCR_EMASK(v) ((v) << P4_ESCR_EVENTMASK_SHIFT) 37d814f301SCyrill Gorcunov #define P4_ESCR_TAG(v) ((v) << P4_ESCR_TAG_SHIFT) 38a072738eSCyrill Gorcunov 39a072738eSCyrill Gorcunov /* Non HT mask */ 40d814f301SCyrill Gorcunov #define P4_ESCR_MASK \ 41d814f301SCyrill Gorcunov (P4_ESCR_EVENT_MASK | \ 42d814f301SCyrill Gorcunov P4_ESCR_EVENTMASK_MASK | \ 43d814f301SCyrill Gorcunov P4_ESCR_TAG_MASK | \ 44d814f301SCyrill Gorcunov P4_ESCR_TAG_ENABLE | \ 45d814f301SCyrill Gorcunov P4_ESCR_T0_OS | \ 46d814f301SCyrill Gorcunov P4_ESCR_T0_USR) 47a072738eSCyrill Gorcunov 48a072738eSCyrill Gorcunov /* HT mask */ 49d814f301SCyrill Gorcunov #define P4_ESCR_MASK_HT \ 50d814f301SCyrill Gorcunov (P4_ESCR_MASK | P4_ESCR_T1_OS | P4_ESCR_T1_USR) 51a072738eSCyrill Gorcunov 52a072738eSCyrill Gorcunov #define P4_CCCR_OVF 0x80000000U 53a072738eSCyrill Gorcunov #define P4_CCCR_CASCADE 0x40000000U 54a072738eSCyrill Gorcunov #define P4_CCCR_OVF_PMI_T0 0x04000000U 55a072738eSCyrill Gorcunov #define P4_CCCR_OVF_PMI_T1 0x08000000U 56a072738eSCyrill Gorcunov #define P4_CCCR_FORCE_OVF 0x02000000U 57a072738eSCyrill Gorcunov #define P4_CCCR_EDGE 0x01000000U 58a072738eSCyrill Gorcunov #define P4_CCCR_THRESHOLD_MASK 0x00f00000U 59a072738eSCyrill Gorcunov #define P4_CCCR_THRESHOLD_SHIFT 20 60a072738eSCyrill Gorcunov #define P4_CCCR_COMPLEMENT 0x00080000U 61a072738eSCyrill Gorcunov #define P4_CCCR_COMPARE 0x00040000U 62a072738eSCyrill Gorcunov #define P4_CCCR_ESCR_SELECT_MASK 0x0000e000U 63a072738eSCyrill Gorcunov #define P4_CCCR_ESCR_SELECT_SHIFT 13 64a072738eSCyrill Gorcunov #define P4_CCCR_ENABLE 0x00001000U 65a072738eSCyrill Gorcunov #define P4_CCCR_THREAD_SINGLE 0x00010000U 66a072738eSCyrill Gorcunov #define P4_CCCR_THREAD_BOTH 0x00020000U 67a072738eSCyrill Gorcunov #define P4_CCCR_THREAD_ANY 0x00030000U 68f34edbc1SLin Ming #define P4_CCCR_RESERVED 0x00000fffU 69a072738eSCyrill Gorcunov 70d814f301SCyrill Gorcunov #define P4_CCCR_THRESHOLD(v) ((v) << P4_CCCR_THRESHOLD_SHIFT) 71d814f301SCyrill Gorcunov #define P4_CCCR_ESEL(v) ((v) << P4_CCCR_ESCR_SELECT_SHIFT) 72d814f301SCyrill Gorcunov 73a072738eSCyrill Gorcunov /* Non HT mask */ 74a072738eSCyrill Gorcunov #define P4_CCCR_MASK \ 75a072738eSCyrill Gorcunov (P4_CCCR_OVF | \ 76a072738eSCyrill Gorcunov P4_CCCR_CASCADE | \ 77a072738eSCyrill Gorcunov P4_CCCR_OVF_PMI_T0 | \ 78a072738eSCyrill Gorcunov P4_CCCR_FORCE_OVF | \ 79a072738eSCyrill Gorcunov P4_CCCR_EDGE | \ 80a072738eSCyrill Gorcunov P4_CCCR_THRESHOLD_MASK | \ 81a072738eSCyrill Gorcunov P4_CCCR_COMPLEMENT | \ 82a072738eSCyrill Gorcunov P4_CCCR_COMPARE | \ 83a072738eSCyrill Gorcunov P4_CCCR_ESCR_SELECT_MASK | \ 84a072738eSCyrill Gorcunov P4_CCCR_ENABLE) 85a072738eSCyrill Gorcunov 86a072738eSCyrill Gorcunov /* HT mask */ 87ce7f1545SCyrill Gorcunov #define P4_CCCR_MASK_HT \ 88ce7f1545SCyrill Gorcunov (P4_CCCR_MASK | P4_CCCR_OVF_PMI_T1 | P4_CCCR_THREAD_ANY) 89a072738eSCyrill Gorcunov 90d814f301SCyrill Gorcunov #define P4_GEN_ESCR_EMASK(class, name, bit) \ 91d814f301SCyrill Gorcunov class##__##name = ((1 << bit) << P4_ESCR_EVENTMASK_SHIFT) 92d814f301SCyrill Gorcunov #define P4_ESCR_EMASK_BIT(class, name) class##__##name 93a072738eSCyrill Gorcunov 94a072738eSCyrill Gorcunov /* 95a072738eSCyrill Gorcunov * config field is 64bit width and consists of 96a072738eSCyrill Gorcunov * HT << 63 | ESCR << 32 | CCCR 97a072738eSCyrill Gorcunov * where HT is HyperThreading bit (since ESCR 98a072738eSCyrill Gorcunov * has it reserved we may use it for own purpose) 99a072738eSCyrill Gorcunov * 100a072738eSCyrill Gorcunov * note that this is NOT the addresses of respective 101a072738eSCyrill Gorcunov * ESCR and CCCR but rather an only packed value should 102a072738eSCyrill Gorcunov * be unpacked and written to a proper addresses 103a072738eSCyrill Gorcunov * 104*39ef13a4SCyrill Gorcunov * the base idea is to pack as much info as possible 105a072738eSCyrill Gorcunov */ 106a072738eSCyrill Gorcunov #define p4_config_pack_escr(v) (((u64)(v)) << 32) 107a072738eSCyrill Gorcunov #define p4_config_pack_cccr(v) (((u64)(v)) & 0xffffffffULL) 108a072738eSCyrill Gorcunov #define p4_config_unpack_escr(v) (((u64)(v)) >> 32) 109d814f301SCyrill Gorcunov #define p4_config_unpack_cccr(v) (((u64)(v)) & 0xffffffffULL) 110a072738eSCyrill Gorcunov 111a072738eSCyrill Gorcunov #define p4_config_unpack_emask(v) \ 112a072738eSCyrill Gorcunov ({ \ 113a072738eSCyrill Gorcunov u32 t = p4_config_unpack_escr((v)); \ 114d814f301SCyrill Gorcunov t = t & P4_ESCR_EVENTMASK_MASK; \ 115d814f301SCyrill Gorcunov t = t >> P4_ESCR_EVENTMASK_SHIFT; \ 116a072738eSCyrill Gorcunov t; \ 117a072738eSCyrill Gorcunov }) 118a072738eSCyrill Gorcunov 119d814f301SCyrill Gorcunov #define p4_config_unpack_event(v) \ 120d814f301SCyrill Gorcunov ({ \ 121d814f301SCyrill Gorcunov u32 t = p4_config_unpack_escr((v)); \ 122d814f301SCyrill Gorcunov t = t & P4_ESCR_EVENT_MASK; \ 123d814f301SCyrill Gorcunov t = t >> P4_ESCR_EVENT_SHIFT; \ 124d814f301SCyrill Gorcunov t; \ 125d814f301SCyrill Gorcunov }) 126d814f301SCyrill Gorcunov 127a072738eSCyrill Gorcunov #define P4_CONFIG_HT_SHIFT 63 128a072738eSCyrill Gorcunov #define P4_CONFIG_HT (1ULL << P4_CONFIG_HT_SHIFT) 129a072738eSCyrill Gorcunov 130a072738eSCyrill Gorcunov static inline bool p4_is_event_cascaded(u64 config) 131a072738eSCyrill Gorcunov { 132a072738eSCyrill Gorcunov u32 cccr = p4_config_unpack_cccr(config); 133a072738eSCyrill Gorcunov return !!(cccr & P4_CCCR_CASCADE); 134a072738eSCyrill Gorcunov } 135a072738eSCyrill Gorcunov 136a072738eSCyrill Gorcunov static inline int p4_ht_config_thread(u64 config) 137a072738eSCyrill Gorcunov { 138a072738eSCyrill Gorcunov return !!(config & P4_CONFIG_HT); 139a072738eSCyrill Gorcunov } 140a072738eSCyrill Gorcunov 141a072738eSCyrill Gorcunov static inline u64 p4_set_ht_bit(u64 config) 142a072738eSCyrill Gorcunov { 143a072738eSCyrill Gorcunov return config | P4_CONFIG_HT; 144a072738eSCyrill Gorcunov } 145a072738eSCyrill Gorcunov 146a072738eSCyrill Gorcunov static inline u64 p4_clear_ht_bit(u64 config) 147a072738eSCyrill Gorcunov { 148a072738eSCyrill Gorcunov return config & ~P4_CONFIG_HT; 149a072738eSCyrill Gorcunov } 150a072738eSCyrill Gorcunov 151a072738eSCyrill Gorcunov static inline int p4_ht_active(void) 152a072738eSCyrill Gorcunov { 153a072738eSCyrill Gorcunov #ifdef CONFIG_SMP 154a072738eSCyrill Gorcunov return smp_num_siblings > 1; 155a072738eSCyrill Gorcunov #endif 156a072738eSCyrill Gorcunov return 0; 157a072738eSCyrill Gorcunov } 158a072738eSCyrill Gorcunov 159a072738eSCyrill Gorcunov static inline int p4_ht_thread(int cpu) 160a072738eSCyrill Gorcunov { 161a072738eSCyrill Gorcunov #ifdef CONFIG_SMP 162a072738eSCyrill Gorcunov if (smp_num_siblings == 2) 163a072738eSCyrill Gorcunov return cpu != cpumask_first(__get_cpu_var(cpu_sibling_map)); 164a072738eSCyrill Gorcunov #endif 165a072738eSCyrill Gorcunov return 0; 166a072738eSCyrill Gorcunov } 167a072738eSCyrill Gorcunov 168a072738eSCyrill Gorcunov static inline int p4_should_swap_ts(u64 config, int cpu) 169a072738eSCyrill Gorcunov { 170a072738eSCyrill Gorcunov return p4_ht_config_thread(config) ^ p4_ht_thread(cpu); 171a072738eSCyrill Gorcunov } 172a072738eSCyrill Gorcunov 173a072738eSCyrill Gorcunov static inline u32 p4_default_cccr_conf(int cpu) 174a072738eSCyrill Gorcunov { 175a072738eSCyrill Gorcunov /* 176a072738eSCyrill Gorcunov * Note that P4_CCCR_THREAD_ANY is "required" on 177a072738eSCyrill Gorcunov * non-HT machines (on HT machines we count TS events 178a072738eSCyrill Gorcunov * regardless the state of second logical processor 179a072738eSCyrill Gorcunov */ 180a072738eSCyrill Gorcunov u32 cccr = P4_CCCR_THREAD_ANY; 181a072738eSCyrill Gorcunov 182a072738eSCyrill Gorcunov if (!p4_ht_thread(cpu)) 183a072738eSCyrill Gorcunov cccr |= P4_CCCR_OVF_PMI_T0; 184a072738eSCyrill Gorcunov else 185a072738eSCyrill Gorcunov cccr |= P4_CCCR_OVF_PMI_T1; 186a072738eSCyrill Gorcunov 187a072738eSCyrill Gorcunov return cccr; 188a072738eSCyrill Gorcunov } 189a072738eSCyrill Gorcunov 190a072738eSCyrill Gorcunov static inline u32 p4_default_escr_conf(int cpu, int exclude_os, int exclude_usr) 191a072738eSCyrill Gorcunov { 192a072738eSCyrill Gorcunov u32 escr = 0; 193a072738eSCyrill Gorcunov 194a072738eSCyrill Gorcunov if (!p4_ht_thread(cpu)) { 195a072738eSCyrill Gorcunov if (!exclude_os) 196d814f301SCyrill Gorcunov escr |= P4_ESCR_T0_OS; 197a072738eSCyrill Gorcunov if (!exclude_usr) 198d814f301SCyrill Gorcunov escr |= P4_ESCR_T0_USR; 199a072738eSCyrill Gorcunov } else { 200a072738eSCyrill Gorcunov if (!exclude_os) 201d814f301SCyrill Gorcunov escr |= P4_ESCR_T1_OS; 202a072738eSCyrill Gorcunov if (!exclude_usr) 203d814f301SCyrill Gorcunov escr |= P4_ESCR_T1_USR; 204a072738eSCyrill Gorcunov } 205a072738eSCyrill Gorcunov 206a072738eSCyrill Gorcunov return escr; 207a072738eSCyrill Gorcunov } 208a072738eSCyrill Gorcunov 209*39ef13a4SCyrill Gorcunov /* 210*39ef13a4SCyrill Gorcunov * This are the events which should be used in "Event Select" 211*39ef13a4SCyrill Gorcunov * field of ESCR register, they are like unique keys which allow 212*39ef13a4SCyrill Gorcunov * the kernel to determinate which CCCR and COUNTER should be 213*39ef13a4SCyrill Gorcunov * used to track an event 214*39ef13a4SCyrill Gorcunov */ 215d814f301SCyrill Gorcunov enum P4_EVENTS { 216d814f301SCyrill Gorcunov P4_EVENT_TC_DELIVER_MODE, 217d814f301SCyrill Gorcunov P4_EVENT_BPU_FETCH_REQUEST, 218d814f301SCyrill Gorcunov P4_EVENT_ITLB_REFERENCE, 219d814f301SCyrill Gorcunov P4_EVENT_MEMORY_CANCEL, 220d814f301SCyrill Gorcunov P4_EVENT_MEMORY_COMPLETE, 221d814f301SCyrill Gorcunov P4_EVENT_LOAD_PORT_REPLAY, 222d814f301SCyrill Gorcunov P4_EVENT_STORE_PORT_REPLAY, 223d814f301SCyrill Gorcunov P4_EVENT_MOB_LOAD_REPLAY, 224d814f301SCyrill Gorcunov P4_EVENT_PAGE_WALK_TYPE, 225d814f301SCyrill Gorcunov P4_EVENT_BSQ_CACHE_REFERENCE, 226d814f301SCyrill Gorcunov P4_EVENT_IOQ_ALLOCATION, 227d814f301SCyrill Gorcunov P4_EVENT_IOQ_ACTIVE_ENTRIES, 228d814f301SCyrill Gorcunov P4_EVENT_FSB_DATA_ACTIVITY, 229d814f301SCyrill Gorcunov P4_EVENT_BSQ_ALLOCATION, 230d814f301SCyrill Gorcunov P4_EVENT_BSQ_ACTIVE_ENTRIES, 231d814f301SCyrill Gorcunov P4_EVENT_SSE_INPUT_ASSIST, 232d814f301SCyrill Gorcunov P4_EVENT_PACKED_SP_UOP, 233d814f301SCyrill Gorcunov P4_EVENT_PACKED_DP_UOP, 234d814f301SCyrill Gorcunov P4_EVENT_SCALAR_SP_UOP, 235d814f301SCyrill Gorcunov P4_EVENT_SCALAR_DP_UOP, 236d814f301SCyrill Gorcunov P4_EVENT_64BIT_MMX_UOP, 237d814f301SCyrill Gorcunov P4_EVENT_128BIT_MMX_UOP, 238d814f301SCyrill Gorcunov P4_EVENT_X87_FP_UOP, 239d814f301SCyrill Gorcunov P4_EVENT_TC_MISC, 240d814f301SCyrill Gorcunov P4_EVENT_GLOBAL_POWER_EVENTS, 241d814f301SCyrill Gorcunov P4_EVENT_TC_MS_XFER, 242d814f301SCyrill Gorcunov P4_EVENT_UOP_QUEUE_WRITES, 243d814f301SCyrill Gorcunov P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE, 244d814f301SCyrill Gorcunov P4_EVENT_RETIRED_BRANCH_TYPE, 245d814f301SCyrill Gorcunov P4_EVENT_RESOURCE_STALL, 246d814f301SCyrill Gorcunov P4_EVENT_WC_BUFFER, 247d814f301SCyrill Gorcunov P4_EVENT_B2B_CYCLES, 248d814f301SCyrill Gorcunov P4_EVENT_BNR, 249d814f301SCyrill Gorcunov P4_EVENT_SNOOP, 250d814f301SCyrill Gorcunov P4_EVENT_RESPONSE, 251d814f301SCyrill Gorcunov P4_EVENT_FRONT_END_EVENT, 252d814f301SCyrill Gorcunov P4_EVENT_EXECUTION_EVENT, 253d814f301SCyrill Gorcunov P4_EVENT_REPLAY_EVENT, 254d814f301SCyrill Gorcunov P4_EVENT_INSTR_RETIRED, 255d814f301SCyrill Gorcunov P4_EVENT_UOPS_RETIRED, 256d814f301SCyrill Gorcunov P4_EVENT_UOP_TYPE, 257d814f301SCyrill Gorcunov P4_EVENT_BRANCH_RETIRED, 258d814f301SCyrill Gorcunov P4_EVENT_MISPRED_BRANCH_RETIRED, 259d814f301SCyrill Gorcunov P4_EVENT_X87_ASSIST, 260d814f301SCyrill Gorcunov P4_EVENT_MACHINE_CLEAR, 261d814f301SCyrill Gorcunov P4_EVENT_INSTR_COMPLETED, 262d814f301SCyrill Gorcunov }; 263d814f301SCyrill Gorcunov 264d814f301SCyrill Gorcunov #define P4_OPCODE(event) event##_OPCODE 265d814f301SCyrill Gorcunov #define P4_OPCODE_ESEL(opcode) ((opcode & 0x00ff) >> 0) 266d814f301SCyrill Gorcunov #define P4_OPCODE_EVNT(opcode) ((opcode & 0xff00) >> 8) 267d814f301SCyrill Gorcunov #define P4_OPCODE_PACK(event, sel) (((event) << 8) | sel) 268d814f301SCyrill Gorcunov 269a072738eSCyrill Gorcunov /* 270a072738eSCyrill Gorcunov * Comments below the event represent ESCR restriction 271a072738eSCyrill Gorcunov * for this event and counter index per ESCR 272a072738eSCyrill Gorcunov * 273a072738eSCyrill Gorcunov * MSR_P4_IQ_ESCR0 and MSR_P4_IQ_ESCR1 are available only on early 274a072738eSCyrill Gorcunov * processor builds (family 0FH, models 01H-02H). These MSRs 275a072738eSCyrill Gorcunov * are not available on later versions, so that we don't use 276a072738eSCyrill Gorcunov * them completely 277a072738eSCyrill Gorcunov * 278a072738eSCyrill Gorcunov * Also note that CCCR1 do not have P4_CCCR_ENABLE bit properly 279a072738eSCyrill Gorcunov * working so that we should not use this CCCR and respective 280a072738eSCyrill Gorcunov * counter as result 281a072738eSCyrill Gorcunov */ 282d814f301SCyrill Gorcunov enum P4_EVENT_OPCODES { 283d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_TC_DELIVER_MODE) = P4_OPCODE_PACK(0x01, 0x01), 284a072738eSCyrill Gorcunov /* 285a072738eSCyrill Gorcunov * MSR_P4_TC_ESCR0: 4, 5 286a072738eSCyrill Gorcunov * MSR_P4_TC_ESCR1: 6, 7 287a072738eSCyrill Gorcunov */ 288a072738eSCyrill Gorcunov 289d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_BPU_FETCH_REQUEST) = P4_OPCODE_PACK(0x03, 0x00), 290a072738eSCyrill Gorcunov /* 291a072738eSCyrill Gorcunov * MSR_P4_BPU_ESCR0: 0, 1 292a072738eSCyrill Gorcunov * MSR_P4_BPU_ESCR1: 2, 3 293a072738eSCyrill Gorcunov */ 294a072738eSCyrill Gorcunov 295d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_ITLB_REFERENCE) = P4_OPCODE_PACK(0x18, 0x03), 296a072738eSCyrill Gorcunov /* 297a072738eSCyrill Gorcunov * MSR_P4_ITLB_ESCR0: 0, 1 298a072738eSCyrill Gorcunov * MSR_P4_ITLB_ESCR1: 2, 3 299a072738eSCyrill Gorcunov */ 300a072738eSCyrill Gorcunov 301d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_MEMORY_CANCEL) = P4_OPCODE_PACK(0x02, 0x05), 302a072738eSCyrill Gorcunov /* 303a072738eSCyrill Gorcunov * MSR_P4_DAC_ESCR0: 8, 9 304a072738eSCyrill Gorcunov * MSR_P4_DAC_ESCR1: 10, 11 305a072738eSCyrill Gorcunov */ 306a072738eSCyrill Gorcunov 307d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_MEMORY_COMPLETE) = P4_OPCODE_PACK(0x08, 0x02), 308a072738eSCyrill Gorcunov /* 309a072738eSCyrill Gorcunov * MSR_P4_SAAT_ESCR0: 8, 9 310a072738eSCyrill Gorcunov * MSR_P4_SAAT_ESCR1: 10, 11 311a072738eSCyrill Gorcunov */ 312a072738eSCyrill Gorcunov 313d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_LOAD_PORT_REPLAY) = P4_OPCODE_PACK(0x04, 0x02), 314a072738eSCyrill Gorcunov /* 315a072738eSCyrill Gorcunov * MSR_P4_SAAT_ESCR0: 8, 9 316a072738eSCyrill Gorcunov * MSR_P4_SAAT_ESCR1: 10, 11 317a072738eSCyrill Gorcunov */ 318a072738eSCyrill Gorcunov 319d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_STORE_PORT_REPLAY) = P4_OPCODE_PACK(0x05, 0x02), 320a072738eSCyrill Gorcunov /* 321a072738eSCyrill Gorcunov * MSR_P4_SAAT_ESCR0: 8, 9 322a072738eSCyrill Gorcunov * MSR_P4_SAAT_ESCR1: 10, 11 323a072738eSCyrill Gorcunov */ 324a072738eSCyrill Gorcunov 325d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_MOB_LOAD_REPLAY) = P4_OPCODE_PACK(0x03, 0x02), 326a072738eSCyrill Gorcunov /* 327a072738eSCyrill Gorcunov * MSR_P4_MOB_ESCR0: 0, 1 328a072738eSCyrill Gorcunov * MSR_P4_MOB_ESCR1: 2, 3 329a072738eSCyrill Gorcunov */ 330a072738eSCyrill Gorcunov 331d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_PAGE_WALK_TYPE) = P4_OPCODE_PACK(0x01, 0x04), 332a072738eSCyrill Gorcunov /* 333a072738eSCyrill Gorcunov * MSR_P4_PMH_ESCR0: 0, 1 334a072738eSCyrill Gorcunov * MSR_P4_PMH_ESCR1: 2, 3 335a072738eSCyrill Gorcunov */ 336a072738eSCyrill Gorcunov 337d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_BSQ_CACHE_REFERENCE) = P4_OPCODE_PACK(0x0c, 0x07), 338a072738eSCyrill Gorcunov /* 339a072738eSCyrill Gorcunov * MSR_P4_BSU_ESCR0: 0, 1 340a072738eSCyrill Gorcunov * MSR_P4_BSU_ESCR1: 2, 3 341a072738eSCyrill Gorcunov */ 342a072738eSCyrill Gorcunov 343d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_IOQ_ALLOCATION) = P4_OPCODE_PACK(0x03, 0x06), 344a072738eSCyrill Gorcunov /* 345a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR0: 0, 1 346a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR1: 2, 3 347a072738eSCyrill Gorcunov */ 348a072738eSCyrill Gorcunov 349d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_IOQ_ACTIVE_ENTRIES) = P4_OPCODE_PACK(0x1a, 0x06), 350a072738eSCyrill Gorcunov /* 351a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR1: 2, 3 352a072738eSCyrill Gorcunov */ 353a072738eSCyrill Gorcunov 354d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_FSB_DATA_ACTIVITY) = P4_OPCODE_PACK(0x17, 0x06), 355a072738eSCyrill Gorcunov /* 356a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR0: 0, 1 357a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR1: 2, 3 358a072738eSCyrill Gorcunov */ 359a072738eSCyrill Gorcunov 360d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_BSQ_ALLOCATION) = P4_OPCODE_PACK(0x05, 0x07), 361a072738eSCyrill Gorcunov /* 362a072738eSCyrill Gorcunov * MSR_P4_BSU_ESCR0: 0, 1 363a072738eSCyrill Gorcunov */ 364a072738eSCyrill Gorcunov 365d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_BSQ_ACTIVE_ENTRIES) = P4_OPCODE_PACK(0x06, 0x07), 366a072738eSCyrill Gorcunov /* 3678ea7f544SLin Ming * NOTE: no ESCR name in docs, it's guessed 368a072738eSCyrill Gorcunov * MSR_P4_BSU_ESCR1: 2, 3 369a072738eSCyrill Gorcunov */ 370a072738eSCyrill Gorcunov 371d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_SSE_INPUT_ASSIST) = P4_OPCODE_PACK(0x34, 0x01), 372a072738eSCyrill Gorcunov /* 373e4495262SCyrill Gorcunov * MSR_P4_FIRM_ESCR0: 8, 9 374e4495262SCyrill Gorcunov * MSR_P4_FIRM_ESCR1: 10, 11 375a072738eSCyrill Gorcunov */ 376a072738eSCyrill Gorcunov 377d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_PACKED_SP_UOP) = P4_OPCODE_PACK(0x08, 0x01), 378a072738eSCyrill Gorcunov /* 379a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR0: 8, 9 380a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR1: 10, 11 381a072738eSCyrill Gorcunov */ 382a072738eSCyrill Gorcunov 383d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_PACKED_DP_UOP) = P4_OPCODE_PACK(0x0c, 0x01), 384a072738eSCyrill Gorcunov /* 385a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR0: 8, 9 386a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR1: 10, 11 387a072738eSCyrill Gorcunov */ 388a072738eSCyrill Gorcunov 389d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_SCALAR_SP_UOP) = P4_OPCODE_PACK(0x0a, 0x01), 390a072738eSCyrill Gorcunov /* 391a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR0: 8, 9 392a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR1: 10, 11 393a072738eSCyrill Gorcunov */ 394a072738eSCyrill Gorcunov 395d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_SCALAR_DP_UOP) = P4_OPCODE_PACK(0x0e, 0x01), 396a072738eSCyrill Gorcunov /* 397a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR0: 8, 9 398a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR1: 10, 11 399a072738eSCyrill Gorcunov */ 400a072738eSCyrill Gorcunov 401d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_64BIT_MMX_UOP) = P4_OPCODE_PACK(0x02, 0x01), 402a072738eSCyrill Gorcunov /* 403a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR0: 8, 9 404a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR1: 10, 11 405a072738eSCyrill Gorcunov */ 406a072738eSCyrill Gorcunov 407d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_128BIT_MMX_UOP) = P4_OPCODE_PACK(0x1a, 0x01), 408a072738eSCyrill Gorcunov /* 409a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR0: 8, 9 410a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR1: 10, 11 411a072738eSCyrill Gorcunov */ 412a072738eSCyrill Gorcunov 413d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_X87_FP_UOP) = P4_OPCODE_PACK(0x04, 0x01), 414a072738eSCyrill Gorcunov /* 415a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR0: 8, 9 416a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR1: 10, 11 417a072738eSCyrill Gorcunov */ 418a072738eSCyrill Gorcunov 419d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_TC_MISC) = P4_OPCODE_PACK(0x06, 0x01), 420a072738eSCyrill Gorcunov /* 421a072738eSCyrill Gorcunov * MSR_P4_TC_ESCR0: 4, 5 422a072738eSCyrill Gorcunov * MSR_P4_TC_ESCR1: 6, 7 423a072738eSCyrill Gorcunov */ 424a072738eSCyrill Gorcunov 425d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_GLOBAL_POWER_EVENTS) = P4_OPCODE_PACK(0x13, 0x06), 426a072738eSCyrill Gorcunov /* 427a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR0: 0, 1 428a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR1: 2, 3 429a072738eSCyrill Gorcunov */ 430a072738eSCyrill Gorcunov 431d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_TC_MS_XFER) = P4_OPCODE_PACK(0x05, 0x00), 432a072738eSCyrill Gorcunov /* 433a072738eSCyrill Gorcunov * MSR_P4_MS_ESCR0: 4, 5 434a072738eSCyrill Gorcunov * MSR_P4_MS_ESCR1: 6, 7 435a072738eSCyrill Gorcunov */ 436a072738eSCyrill Gorcunov 437d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_UOP_QUEUE_WRITES) = P4_OPCODE_PACK(0x09, 0x00), 438a072738eSCyrill Gorcunov /* 439a072738eSCyrill Gorcunov * MSR_P4_MS_ESCR0: 4, 5 440a072738eSCyrill Gorcunov * MSR_P4_MS_ESCR1: 6, 7 441a072738eSCyrill Gorcunov */ 442a072738eSCyrill Gorcunov 443d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE) = P4_OPCODE_PACK(0x05, 0x02), 444a072738eSCyrill Gorcunov /* 445a072738eSCyrill Gorcunov * MSR_P4_TBPU_ESCR0: 4, 5 4469c8c6badSCyrill Gorcunov * MSR_P4_TBPU_ESCR1: 6, 7 447a072738eSCyrill Gorcunov */ 448a072738eSCyrill Gorcunov 449d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_RETIRED_BRANCH_TYPE) = P4_OPCODE_PACK(0x04, 0x02), 450a072738eSCyrill Gorcunov /* 451a072738eSCyrill Gorcunov * MSR_P4_TBPU_ESCR0: 4, 5 4529c8c6badSCyrill Gorcunov * MSR_P4_TBPU_ESCR1: 6, 7 453a072738eSCyrill Gorcunov */ 454a072738eSCyrill Gorcunov 455d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_RESOURCE_STALL) = P4_OPCODE_PACK(0x01, 0x01), 456a072738eSCyrill Gorcunov /* 457a072738eSCyrill Gorcunov * MSR_P4_ALF_ESCR0: 12, 13, 16 458a072738eSCyrill Gorcunov * MSR_P4_ALF_ESCR1: 14, 15, 17 459a072738eSCyrill Gorcunov */ 460a072738eSCyrill Gorcunov 461d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_WC_BUFFER) = P4_OPCODE_PACK(0x05, 0x05), 462a072738eSCyrill Gorcunov /* 463a072738eSCyrill Gorcunov * MSR_P4_DAC_ESCR0: 8, 9 464a072738eSCyrill Gorcunov * MSR_P4_DAC_ESCR1: 10, 11 465a072738eSCyrill Gorcunov */ 466a072738eSCyrill Gorcunov 467d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_B2B_CYCLES) = P4_OPCODE_PACK(0x16, 0x03), 468a072738eSCyrill Gorcunov /* 469a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR0: 0, 1 470a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR1: 2, 3 471a072738eSCyrill Gorcunov */ 472a072738eSCyrill Gorcunov 473d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_BNR) = P4_OPCODE_PACK(0x08, 0x03), 474a072738eSCyrill Gorcunov /* 475a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR0: 0, 1 476a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR1: 2, 3 477a072738eSCyrill Gorcunov */ 478a072738eSCyrill Gorcunov 479d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_SNOOP) = P4_OPCODE_PACK(0x06, 0x03), 480a072738eSCyrill Gorcunov /* 481a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR0: 0, 1 482a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR1: 2, 3 483a072738eSCyrill Gorcunov */ 484a072738eSCyrill Gorcunov 485d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_RESPONSE) = P4_OPCODE_PACK(0x04, 0x03), 486a072738eSCyrill Gorcunov /* 487a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR0: 0, 1 488a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR1: 2, 3 489a072738eSCyrill Gorcunov */ 490a072738eSCyrill Gorcunov 491d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_FRONT_END_EVENT) = P4_OPCODE_PACK(0x08, 0x05), 492a072738eSCyrill Gorcunov /* 493a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR2: 12, 13, 16 494a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR3: 14, 15, 17 495a072738eSCyrill Gorcunov */ 496a072738eSCyrill Gorcunov 497d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_EXECUTION_EVENT) = P4_OPCODE_PACK(0x0c, 0x05), 498a072738eSCyrill Gorcunov /* 499a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR2: 12, 13, 16 500a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR3: 14, 15, 17 501a072738eSCyrill Gorcunov */ 502a072738eSCyrill Gorcunov 503d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_REPLAY_EVENT) = P4_OPCODE_PACK(0x09, 0x05), 504a072738eSCyrill Gorcunov /* 505a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR2: 12, 13, 16 506a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR3: 14, 15, 17 507a072738eSCyrill Gorcunov */ 508a072738eSCyrill Gorcunov 509d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_INSTR_RETIRED) = P4_OPCODE_PACK(0x02, 0x04), 510a072738eSCyrill Gorcunov /* 511e4495262SCyrill Gorcunov * MSR_P4_CRU_ESCR0: 12, 13, 16 512e4495262SCyrill Gorcunov * MSR_P4_CRU_ESCR1: 14, 15, 17 513a072738eSCyrill Gorcunov */ 514a072738eSCyrill Gorcunov 515d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_UOPS_RETIRED) = P4_OPCODE_PACK(0x01, 0x04), 516a072738eSCyrill Gorcunov /* 5178ea7f544SLin Ming * MSR_P4_CRU_ESCR0: 12, 13, 16 5188ea7f544SLin Ming * MSR_P4_CRU_ESCR1: 14, 15, 17 519a072738eSCyrill Gorcunov */ 520a072738eSCyrill Gorcunov 521d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_UOP_TYPE) = P4_OPCODE_PACK(0x02, 0x02), 522a072738eSCyrill Gorcunov /* 523a072738eSCyrill Gorcunov * MSR_P4_RAT_ESCR0: 12, 13, 16 524a072738eSCyrill Gorcunov * MSR_P4_RAT_ESCR1: 14, 15, 17 525a072738eSCyrill Gorcunov */ 526a072738eSCyrill Gorcunov 527d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_BRANCH_RETIRED) = P4_OPCODE_PACK(0x06, 0x05), 528a072738eSCyrill Gorcunov /* 529a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR2: 12, 13, 16 530a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR3: 14, 15, 17 531a072738eSCyrill Gorcunov */ 532a072738eSCyrill Gorcunov 533d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_MISPRED_BRANCH_RETIRED) = P4_OPCODE_PACK(0x03, 0x04), 534a072738eSCyrill Gorcunov /* 535a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR0: 12, 13, 16 536a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR1: 14, 15, 17 537a072738eSCyrill Gorcunov */ 538a072738eSCyrill Gorcunov 539d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_X87_ASSIST) = P4_OPCODE_PACK(0x03, 0x05), 540a072738eSCyrill Gorcunov /* 541a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR2: 12, 13, 16 542a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR3: 14, 15, 17 543a072738eSCyrill Gorcunov */ 544a072738eSCyrill Gorcunov 545d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_MACHINE_CLEAR) = P4_OPCODE_PACK(0x02, 0x05), 546a072738eSCyrill Gorcunov /* 547a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR2: 12, 13, 16 548a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR3: 14, 15, 17 549a072738eSCyrill Gorcunov */ 550a072738eSCyrill Gorcunov 551d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_INSTR_COMPLETED) = P4_OPCODE_PACK(0x07, 0x04), 552a072738eSCyrill Gorcunov /* 553a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR0: 12, 13, 16 554a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR1: 14, 15, 17 555a072738eSCyrill Gorcunov */ 556a072738eSCyrill Gorcunov }; 557a072738eSCyrill Gorcunov 558d814f301SCyrill Gorcunov /* 559d814f301SCyrill Gorcunov * a caller should use P4_ESCR_EMASK_NAME helper to 560d814f301SCyrill Gorcunov * pick the EventMask needed, for example 561d814f301SCyrill Gorcunov * 562*39ef13a4SCyrill Gorcunov * P4_ESCR_EMASK_BIT(P4_EVENT_TC_DELIVER_MODE, DD) 563d814f301SCyrill Gorcunov */ 564d814f301SCyrill Gorcunov enum P4_ESCR_EMASKS { 565d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, DD, 0), 566d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, DB, 1), 567d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, DI, 2), 568d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, BD, 3), 569d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, BB, 4), 570d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, BI, 5), 571d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, ID, 6), 572d814f301SCyrill Gorcunov 573d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BPU_FETCH_REQUEST, TCMISS, 0), 574d814f301SCyrill Gorcunov 575d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_ITLB_REFERENCE, HIT, 0), 576d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_ITLB_REFERENCE, MISS, 1), 577d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_ITLB_REFERENCE, HIT_UK, 2), 578d814f301SCyrill Gorcunov 579d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_MEMORY_CANCEL, ST_RB_FULL, 2), 580d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_MEMORY_CANCEL, 64K_CONF, 3), 581d814f301SCyrill Gorcunov 582d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_MEMORY_COMPLETE, LSC, 0), 583d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_MEMORY_COMPLETE, SSC, 1), 584d814f301SCyrill Gorcunov 585d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_LOAD_PORT_REPLAY, SPLIT_LD, 1), 586d814f301SCyrill Gorcunov 587d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_STORE_PORT_REPLAY, SPLIT_ST, 1), 588d814f301SCyrill Gorcunov 589d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_MOB_LOAD_REPLAY, NO_STA, 1), 590d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_MOB_LOAD_REPLAY, NO_STD, 3), 591d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_MOB_LOAD_REPLAY, PARTIAL_DATA, 4), 592d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_MOB_LOAD_REPLAY, UNALGN_ADDR, 5), 593d814f301SCyrill Gorcunov 594d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_PAGE_WALK_TYPE, DTMISS, 0), 595d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_PAGE_WALK_TYPE, ITMISS, 1), 596d814f301SCyrill Gorcunov 597d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_HITS, 0), 598d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_HITE, 1), 599d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_HITM, 2), 600d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_HITS, 3), 601d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_HITE, 4), 602d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_HITM, 5), 603d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_MISS, 8), 604d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_MISS, 9), 605d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, WR_2ndL_MISS, 10), 606d814f301SCyrill Gorcunov 607d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, DEFAULT, 0), 608d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, ALL_READ, 5), 609d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, ALL_WRITE, 6), 610d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, MEM_UC, 7), 611d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, MEM_WC, 8), 612d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, MEM_WT, 9), 613d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, MEM_WP, 10), 614d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, MEM_WB, 11), 615d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, OWN, 13), 616d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, OTHER, 14), 617d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, PREFETCH, 15), 618d814f301SCyrill Gorcunov 619d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, DEFAULT, 0), 620d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, ALL_READ, 5), 621d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, ALL_WRITE, 6), 622d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, MEM_UC, 7), 623d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, MEM_WC, 8), 624d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, MEM_WT, 9), 625d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, MEM_WP, 10), 626d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, MEM_WB, 11), 627d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, OWN, 13), 628d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, OTHER, 14), 629d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, PREFETCH, 15), 630d814f301SCyrill Gorcunov 631d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_FSB_DATA_ACTIVITY, DRDY_DRV, 0), 632d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_FSB_DATA_ACTIVITY, DRDY_OWN, 1), 633d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_FSB_DATA_ACTIVITY, DRDY_OTHER, 2), 634d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_FSB_DATA_ACTIVITY, DBSY_DRV, 3), 635d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_FSB_DATA_ACTIVITY, DBSY_OWN, 4), 636d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_FSB_DATA_ACTIVITY, DBSY_OTHER, 5), 637d814f301SCyrill Gorcunov 638d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_TYPE0, 0), 639d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_TYPE1, 1), 640d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_LEN0, 2), 641d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_LEN1, 3), 642d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_IO_TYPE, 5), 643d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_LOCK_TYPE, 6), 644d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_CACHE_TYPE, 7), 645d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_SPLIT_TYPE, 8), 646d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_DEM_TYPE, 9), 647d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_ORD_TYPE, 10), 648d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, MEM_TYPE0, 11), 649d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, MEM_TYPE1, 12), 650d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, MEM_TYPE2, 13), 651d814f301SCyrill Gorcunov 652d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_TYPE0, 0), 653d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_TYPE1, 1), 654d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_LEN0, 2), 655d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_LEN1, 3), 656d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_IO_TYPE, 5), 657d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_LOCK_TYPE, 6), 658d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_CACHE_TYPE, 7), 659d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_SPLIT_TYPE, 8), 660d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_DEM_TYPE, 9), 661d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_ORD_TYPE, 10), 662d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, MEM_TYPE0, 11), 663d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, MEM_TYPE1, 12), 664d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, MEM_TYPE2, 13), 665d814f301SCyrill Gorcunov 666d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_SSE_INPUT_ASSIST, ALL, 15), 667d814f301SCyrill Gorcunov 668d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_PACKED_SP_UOP, ALL, 15), 669d814f301SCyrill Gorcunov 670d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_PACKED_DP_UOP, ALL, 15), 671d814f301SCyrill Gorcunov 672d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_SCALAR_SP_UOP, ALL, 15), 673d814f301SCyrill Gorcunov 674d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_SCALAR_DP_UOP, ALL, 15), 675d814f301SCyrill Gorcunov 676d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_64BIT_MMX_UOP, ALL, 15), 677d814f301SCyrill Gorcunov 678d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_128BIT_MMX_UOP, ALL, 15), 679d814f301SCyrill Gorcunov 680d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_X87_FP_UOP, ALL, 15), 681d814f301SCyrill Gorcunov 682d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_TC_MISC, FLUSH, 4), 683d814f301SCyrill Gorcunov 684d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_GLOBAL_POWER_EVENTS, RUNNING, 0), 685d814f301SCyrill Gorcunov 686d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_TC_MS_XFER, CISC, 0), 687d814f301SCyrill Gorcunov 688d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_UOP_QUEUE_WRITES, FROM_TC_BUILD, 0), 689d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_UOP_QUEUE_WRITES, FROM_TC_DELIVER, 1), 690d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_UOP_QUEUE_WRITES, FROM_ROM, 2), 691d814f301SCyrill Gorcunov 692d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE, CONDITIONAL, 1), 693d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE, CALL, 2), 694d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE, RETURN, 3), 695d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE, INDIRECT, 4), 696d814f301SCyrill Gorcunov 697d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_BRANCH_TYPE, CONDITIONAL, 1), 698d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_BRANCH_TYPE, CALL, 2), 699d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_BRANCH_TYPE, RETURN, 3), 700d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_BRANCH_TYPE, INDIRECT, 4), 701d814f301SCyrill Gorcunov 702d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_RESOURCE_STALL, SBFULL, 5), 703d814f301SCyrill Gorcunov 704d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_WC_BUFFER, WCB_EVICTS, 0), 705d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_WC_BUFFER, WCB_FULL_EVICTS, 1), 706d814f301SCyrill Gorcunov 707d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_FRONT_END_EVENT, NBOGUS, 0), 708d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_FRONT_END_EVENT, BOGUS, 1), 709d814f301SCyrill Gorcunov 710d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, NBOGUS0, 0), 711d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, NBOGUS1, 1), 712d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, NBOGUS2, 2), 713d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, NBOGUS3, 3), 714d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, BOGUS0, 4), 715d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, BOGUS1, 5), 716d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, BOGUS2, 6), 717d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, BOGUS3, 7), 718d814f301SCyrill Gorcunov 719d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_REPLAY_EVENT, NBOGUS, 0), 720d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_REPLAY_EVENT, BOGUS, 1), 721d814f301SCyrill Gorcunov 722d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_INSTR_RETIRED, NBOGUSNTAG, 0), 723d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_INSTR_RETIRED, NBOGUSTAG, 1), 724d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_INSTR_RETIRED, BOGUSNTAG, 2), 725d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_INSTR_RETIRED, BOGUSTAG, 3), 726d814f301SCyrill Gorcunov 727d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_UOPS_RETIRED, NBOGUS, 0), 728d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_UOPS_RETIRED, BOGUS, 1), 729d814f301SCyrill Gorcunov 730d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_UOP_TYPE, TAGLOADS, 1), 731d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_UOP_TYPE, TAGSTORES, 2), 732d814f301SCyrill Gorcunov 733d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BRANCH_RETIRED, MMNP, 0), 734d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BRANCH_RETIRED, MMNM, 1), 735d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BRANCH_RETIRED, MMTP, 2), 736d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BRANCH_RETIRED, MMTM, 3), 737d814f301SCyrill Gorcunov 738d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_MISPRED_BRANCH_RETIRED, NBOGUS, 0), 739d814f301SCyrill Gorcunov 740d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_X87_ASSIST, FPSU, 0), 741d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_X87_ASSIST, FPSO, 1), 742d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_X87_ASSIST, POAO, 2), 743d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_X87_ASSIST, POAU, 3), 744d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_X87_ASSIST, PREA, 4), 745d814f301SCyrill Gorcunov 746d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_MACHINE_CLEAR, CLEAR, 0), 747d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_MACHINE_CLEAR, MOCLEAR, 1), 748d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_MACHINE_CLEAR, SMCLEAR, 2), 749d814f301SCyrill Gorcunov 750d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_INSTR_COMPLETED, NBOGUS, 0), 751d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_INSTR_COMPLETED, BOGUS, 1), 752d814f301SCyrill Gorcunov }; 753d814f301SCyrill Gorcunov 754*39ef13a4SCyrill Gorcunov /* 755*39ef13a4SCyrill Gorcunov * P4 PEBS specifics (Replay Event only) 756*39ef13a4SCyrill Gorcunov * 757*39ef13a4SCyrill Gorcunov * Format (bits): 758*39ef13a4SCyrill Gorcunov * 0-6: metric from P4_PEBS_METRIC enum 759*39ef13a4SCyrill Gorcunov * 7 : reserved 760*39ef13a4SCyrill Gorcunov * 8 : reserved 761*39ef13a4SCyrill Gorcunov * 9-11 : reserved 762*39ef13a4SCyrill Gorcunov * 763*39ef13a4SCyrill Gorcunov * Note we have UOP and PEBS bits reserved for now 764*39ef13a4SCyrill Gorcunov * just in case if we will need them once 765*39ef13a4SCyrill Gorcunov */ 766*39ef13a4SCyrill Gorcunov #define P4_PEBS_CONFIG_ENABLE (1 << 7) 767*39ef13a4SCyrill Gorcunov #define P4_PEBS_CONFIG_UOP_TAG (1 << 8) 768*39ef13a4SCyrill Gorcunov #define P4_PEBS_CONFIG_METRIC_MASK 0x3f 769*39ef13a4SCyrill Gorcunov #define P4_PEBS_CONFIG_MASK 0xff 770*39ef13a4SCyrill Gorcunov 771*39ef13a4SCyrill Gorcunov /* 772*39ef13a4SCyrill Gorcunov * mem: Only counters MSR_IQ_COUNTER4 (16) and 773*39ef13a4SCyrill Gorcunov * MSR_IQ_COUNTER5 (17) are allowed for PEBS sampling 774*39ef13a4SCyrill Gorcunov */ 775d814f301SCyrill Gorcunov #define P4_PEBS_ENABLE 0x02000000U 776*39ef13a4SCyrill Gorcunov #define P4_PEBS_ENABLE_UOP_TAG 0x01000000U 777d814f301SCyrill Gorcunov 778*39ef13a4SCyrill Gorcunov #define p4_config_unpack_metric(v) (((u64)(v)) & P4_PEBS_CONFIG_METRIC_MASK) 779*39ef13a4SCyrill Gorcunov #define p4_config_unpack_pebs(v) (((u64)(v)) & P4_PEBS_CONFIG_MASK) 780d814f301SCyrill Gorcunov 781*39ef13a4SCyrill Gorcunov #define p4_config_pebs_has(v, mask) (p4_config_unpack_pebs(v) & (mask)) 782d814f301SCyrill Gorcunov 783*39ef13a4SCyrill Gorcunov enum P4_PEBS_METRIC { 784*39ef13a4SCyrill Gorcunov P4_PEBS_METRIC__none, 785d814f301SCyrill Gorcunov 786*39ef13a4SCyrill Gorcunov P4_PEBS_METRIC__1stl_cache_load_miss_retired, 787*39ef13a4SCyrill Gorcunov P4_PEBS_METRIC__2ndl_cache_load_miss_retired, 788*39ef13a4SCyrill Gorcunov P4_PEBS_METRIC__dtlb_load_miss_retired, 789*39ef13a4SCyrill Gorcunov P4_PEBS_METRIC__dtlb_store_miss_retired, 790*39ef13a4SCyrill Gorcunov P4_PEBS_METRIC__dtlb_all_miss_retired, 791*39ef13a4SCyrill Gorcunov P4_PEBS_METRIC__tagged_mispred_branch, 792*39ef13a4SCyrill Gorcunov P4_PEBS_METRIC__mob_load_replay_retired, 793*39ef13a4SCyrill Gorcunov P4_PEBS_METRIC__split_load_retired, 794*39ef13a4SCyrill Gorcunov P4_PEBS_METRIC__split_store_retired, 795d814f301SCyrill Gorcunov 796*39ef13a4SCyrill Gorcunov P4_PEBS_METRIC__max 797cb7d6b50SLin Ming }; 798cb7d6b50SLin Ming 799a072738eSCyrill Gorcunov #endif /* PERF_EVENT_P4_H */ 800*39ef13a4SCyrill Gorcunov 801