1a072738eSCyrill Gorcunov /* 2*0d2eb44fSLucas De Marchi * Netburst Performance Events (P4, old Xeon) 3a072738eSCyrill Gorcunov */ 4a072738eSCyrill Gorcunov 5a072738eSCyrill Gorcunov #ifndef PERF_EVENT_P4_H 6a072738eSCyrill Gorcunov #define PERF_EVENT_P4_H 7a072738eSCyrill Gorcunov 8a072738eSCyrill Gorcunov #include <linux/cpu.h> 9a072738eSCyrill Gorcunov #include <linux/bitops.h> 10a072738eSCyrill Gorcunov 11a072738eSCyrill Gorcunov /* 12*0d2eb44fSLucas De Marchi * NetBurst has performance MSRs shared between 13a072738eSCyrill Gorcunov * threads if HT is turned on, ie for both logical 14a072738eSCyrill Gorcunov * processors (mem: in turn in Atom with HT support 15a072738eSCyrill Gorcunov * perf-MSRs are not shared and every thread has its 16a072738eSCyrill Gorcunov * own perf-MSRs set) 17a072738eSCyrill Gorcunov */ 18a072738eSCyrill Gorcunov #define ARCH_P4_TOTAL_ESCR (46) 19a072738eSCyrill Gorcunov #define ARCH_P4_RESERVED_ESCR (2) /* IQ_ESCR(0,1) not always present */ 20a072738eSCyrill Gorcunov #define ARCH_P4_MAX_ESCR (ARCH_P4_TOTAL_ESCR - ARCH_P4_RESERVED_ESCR) 21a072738eSCyrill Gorcunov #define ARCH_P4_MAX_CCCR (18) 22a072738eSCyrill Gorcunov 23047a3772SCyrill Gorcunov #define ARCH_P4_CNTRVAL_BITS (40) 24047a3772SCyrill Gorcunov #define ARCH_P4_CNTRVAL_MASK ((1ULL << ARCH_P4_CNTRVAL_BITS) - 1) 257d44ec19SCyrill Gorcunov #define ARCH_P4_UNFLAGGED_BIT ((1ULL) << (ARCH_P4_CNTRVAL_BITS - 1)) 26047a3772SCyrill Gorcunov 27d814f301SCyrill Gorcunov #define P4_ESCR_EVENT_MASK 0x7e000000U 28d814f301SCyrill Gorcunov #define P4_ESCR_EVENT_SHIFT 25 29d814f301SCyrill Gorcunov #define P4_ESCR_EVENTMASK_MASK 0x01fffe00U 30d814f301SCyrill Gorcunov #define P4_ESCR_EVENTMASK_SHIFT 9 31d814f301SCyrill Gorcunov #define P4_ESCR_TAG_MASK 0x000001e0U 32d814f301SCyrill Gorcunov #define P4_ESCR_TAG_SHIFT 5 33d814f301SCyrill Gorcunov #define P4_ESCR_TAG_ENABLE 0x00000010U 34d814f301SCyrill Gorcunov #define P4_ESCR_T0_OS 0x00000008U 35d814f301SCyrill Gorcunov #define P4_ESCR_T0_USR 0x00000004U 36d814f301SCyrill Gorcunov #define P4_ESCR_T1_OS 0x00000002U 37d814f301SCyrill Gorcunov #define P4_ESCR_T1_USR 0x00000001U 38d814f301SCyrill Gorcunov 39d814f301SCyrill Gorcunov #define P4_ESCR_EVENT(v) ((v) << P4_ESCR_EVENT_SHIFT) 40d814f301SCyrill Gorcunov #define P4_ESCR_EMASK(v) ((v) << P4_ESCR_EVENTMASK_SHIFT) 41d814f301SCyrill Gorcunov #define P4_ESCR_TAG(v) ((v) << P4_ESCR_TAG_SHIFT) 42a072738eSCyrill Gorcunov 43a072738eSCyrill Gorcunov #define P4_CCCR_OVF 0x80000000U 44a072738eSCyrill Gorcunov #define P4_CCCR_CASCADE 0x40000000U 45a072738eSCyrill Gorcunov #define P4_CCCR_OVF_PMI_T0 0x04000000U 46a072738eSCyrill Gorcunov #define P4_CCCR_OVF_PMI_T1 0x08000000U 47a072738eSCyrill Gorcunov #define P4_CCCR_FORCE_OVF 0x02000000U 48a072738eSCyrill Gorcunov #define P4_CCCR_EDGE 0x01000000U 49a072738eSCyrill Gorcunov #define P4_CCCR_THRESHOLD_MASK 0x00f00000U 50a072738eSCyrill Gorcunov #define P4_CCCR_THRESHOLD_SHIFT 20 51a072738eSCyrill Gorcunov #define P4_CCCR_COMPLEMENT 0x00080000U 52a072738eSCyrill Gorcunov #define P4_CCCR_COMPARE 0x00040000U 53a072738eSCyrill Gorcunov #define P4_CCCR_ESCR_SELECT_MASK 0x0000e000U 54a072738eSCyrill Gorcunov #define P4_CCCR_ESCR_SELECT_SHIFT 13 55a072738eSCyrill Gorcunov #define P4_CCCR_ENABLE 0x00001000U 56a072738eSCyrill Gorcunov #define P4_CCCR_THREAD_SINGLE 0x00010000U 57a072738eSCyrill Gorcunov #define P4_CCCR_THREAD_BOTH 0x00020000U 58a072738eSCyrill Gorcunov #define P4_CCCR_THREAD_ANY 0x00030000U 59f34edbc1SLin Ming #define P4_CCCR_RESERVED 0x00000fffU 60a072738eSCyrill Gorcunov 61d814f301SCyrill Gorcunov #define P4_CCCR_THRESHOLD(v) ((v) << P4_CCCR_THRESHOLD_SHIFT) 62d814f301SCyrill Gorcunov #define P4_CCCR_ESEL(v) ((v) << P4_CCCR_ESCR_SELECT_SHIFT) 63d814f301SCyrill Gorcunov 64d814f301SCyrill Gorcunov #define P4_GEN_ESCR_EMASK(class, name, bit) \ 65d814f301SCyrill Gorcunov class##__##name = ((1 << bit) << P4_ESCR_EVENTMASK_SHIFT) 66d814f301SCyrill Gorcunov #define P4_ESCR_EMASK_BIT(class, name) class##__##name 67a072738eSCyrill Gorcunov 68a072738eSCyrill Gorcunov /* 69a072738eSCyrill Gorcunov * config field is 64bit width and consists of 70a072738eSCyrill Gorcunov * HT << 63 | ESCR << 32 | CCCR 71a072738eSCyrill Gorcunov * where HT is HyperThreading bit (since ESCR 72a072738eSCyrill Gorcunov * has it reserved we may use it for own purpose) 73a072738eSCyrill Gorcunov * 74a072738eSCyrill Gorcunov * note that this is NOT the addresses of respective 75a072738eSCyrill Gorcunov * ESCR and CCCR but rather an only packed value should 76a072738eSCyrill Gorcunov * be unpacked and written to a proper addresses 77a072738eSCyrill Gorcunov * 7839ef13a4SCyrill Gorcunov * the base idea is to pack as much info as possible 79a072738eSCyrill Gorcunov */ 80a072738eSCyrill Gorcunov #define p4_config_pack_escr(v) (((u64)(v)) << 32) 81a072738eSCyrill Gorcunov #define p4_config_pack_cccr(v) (((u64)(v)) & 0xffffffffULL) 82a072738eSCyrill Gorcunov #define p4_config_unpack_escr(v) (((u64)(v)) >> 32) 83d814f301SCyrill Gorcunov #define p4_config_unpack_cccr(v) (((u64)(v)) & 0xffffffffULL) 84a072738eSCyrill Gorcunov 85a072738eSCyrill Gorcunov #define p4_config_unpack_emask(v) \ 86a072738eSCyrill Gorcunov ({ \ 87a072738eSCyrill Gorcunov u32 t = p4_config_unpack_escr((v)); \ 88d814f301SCyrill Gorcunov t = t & P4_ESCR_EVENTMASK_MASK; \ 89d814f301SCyrill Gorcunov t = t >> P4_ESCR_EVENTMASK_SHIFT; \ 90a072738eSCyrill Gorcunov t; \ 91a072738eSCyrill Gorcunov }) 92a072738eSCyrill Gorcunov 93d814f301SCyrill Gorcunov #define p4_config_unpack_event(v) \ 94d814f301SCyrill Gorcunov ({ \ 95d814f301SCyrill Gorcunov u32 t = p4_config_unpack_escr((v)); \ 96d814f301SCyrill Gorcunov t = t & P4_ESCR_EVENT_MASK; \ 97d814f301SCyrill Gorcunov t = t >> P4_ESCR_EVENT_SHIFT; \ 98d814f301SCyrill Gorcunov t; \ 99d814f301SCyrill Gorcunov }) 100d814f301SCyrill Gorcunov 101a072738eSCyrill Gorcunov #define P4_CONFIG_HT_SHIFT 63 102a072738eSCyrill Gorcunov #define P4_CONFIG_HT (1ULL << P4_CONFIG_HT_SHIFT) 103a072738eSCyrill Gorcunov 104c9cf4a01SCyrill Gorcunov /* 105c9cf4a01SCyrill Gorcunov * The bits we allow to pass for RAW events 106c9cf4a01SCyrill Gorcunov */ 107c9cf4a01SCyrill Gorcunov #define P4_CONFIG_MASK_ESCR \ 108c9cf4a01SCyrill Gorcunov P4_ESCR_EVENT_MASK | \ 109c9cf4a01SCyrill Gorcunov P4_ESCR_EVENTMASK_MASK | \ 110c9cf4a01SCyrill Gorcunov P4_ESCR_TAG_MASK | \ 111c9cf4a01SCyrill Gorcunov P4_ESCR_TAG_ENABLE 112c9cf4a01SCyrill Gorcunov 113c9cf4a01SCyrill Gorcunov #define P4_CONFIG_MASK_CCCR \ 114c9cf4a01SCyrill Gorcunov P4_CCCR_EDGE | \ 115c9cf4a01SCyrill Gorcunov P4_CCCR_THRESHOLD_MASK | \ 116c9cf4a01SCyrill Gorcunov P4_CCCR_COMPLEMENT | \ 117c9cf4a01SCyrill Gorcunov P4_CCCR_COMPARE | \ 118c9cf4a01SCyrill Gorcunov P4_CCCR_THREAD_ANY | \ 119c9cf4a01SCyrill Gorcunov P4_CCCR_RESERVED 120c9cf4a01SCyrill Gorcunov 121c9cf4a01SCyrill Gorcunov /* some dangerous bits are reserved for kernel internals */ 122c9cf4a01SCyrill Gorcunov #define P4_CONFIG_MASK \ 123c9cf4a01SCyrill Gorcunov (p4_config_pack_escr(P4_CONFIG_MASK_ESCR)) | \ 124c9cf4a01SCyrill Gorcunov (p4_config_pack_cccr(P4_CONFIG_MASK_CCCR)) 125c9cf4a01SCyrill Gorcunov 126a072738eSCyrill Gorcunov static inline bool p4_is_event_cascaded(u64 config) 127a072738eSCyrill Gorcunov { 128a072738eSCyrill Gorcunov u32 cccr = p4_config_unpack_cccr(config); 129a072738eSCyrill Gorcunov return !!(cccr & P4_CCCR_CASCADE); 130a072738eSCyrill Gorcunov } 131a072738eSCyrill Gorcunov 132a072738eSCyrill Gorcunov static inline int p4_ht_config_thread(u64 config) 133a072738eSCyrill Gorcunov { 134a072738eSCyrill Gorcunov return !!(config & P4_CONFIG_HT); 135a072738eSCyrill Gorcunov } 136a072738eSCyrill Gorcunov 137a072738eSCyrill Gorcunov static inline u64 p4_set_ht_bit(u64 config) 138a072738eSCyrill Gorcunov { 139a072738eSCyrill Gorcunov return config | P4_CONFIG_HT; 140a072738eSCyrill Gorcunov } 141a072738eSCyrill Gorcunov 142a072738eSCyrill Gorcunov static inline u64 p4_clear_ht_bit(u64 config) 143a072738eSCyrill Gorcunov { 144a072738eSCyrill Gorcunov return config & ~P4_CONFIG_HT; 145a072738eSCyrill Gorcunov } 146a072738eSCyrill Gorcunov 147a072738eSCyrill Gorcunov static inline int p4_ht_active(void) 148a072738eSCyrill Gorcunov { 149a072738eSCyrill Gorcunov #ifdef CONFIG_SMP 150a072738eSCyrill Gorcunov return smp_num_siblings > 1; 151a072738eSCyrill Gorcunov #endif 152a072738eSCyrill Gorcunov return 0; 153a072738eSCyrill Gorcunov } 154a072738eSCyrill Gorcunov 155a072738eSCyrill Gorcunov static inline int p4_ht_thread(int cpu) 156a072738eSCyrill Gorcunov { 157a072738eSCyrill Gorcunov #ifdef CONFIG_SMP 158a072738eSCyrill Gorcunov if (smp_num_siblings == 2) 159a072738eSCyrill Gorcunov return cpu != cpumask_first(__get_cpu_var(cpu_sibling_map)); 160a072738eSCyrill Gorcunov #endif 161a072738eSCyrill Gorcunov return 0; 162a072738eSCyrill Gorcunov } 163a072738eSCyrill Gorcunov 164a072738eSCyrill Gorcunov static inline int p4_should_swap_ts(u64 config, int cpu) 165a072738eSCyrill Gorcunov { 166a072738eSCyrill Gorcunov return p4_ht_config_thread(config) ^ p4_ht_thread(cpu); 167a072738eSCyrill Gorcunov } 168a072738eSCyrill Gorcunov 169a072738eSCyrill Gorcunov static inline u32 p4_default_cccr_conf(int cpu) 170a072738eSCyrill Gorcunov { 171a072738eSCyrill Gorcunov /* 172a072738eSCyrill Gorcunov * Note that P4_CCCR_THREAD_ANY is "required" on 173a072738eSCyrill Gorcunov * non-HT machines (on HT machines we count TS events 174a072738eSCyrill Gorcunov * regardless the state of second logical processor 175a072738eSCyrill Gorcunov */ 176a072738eSCyrill Gorcunov u32 cccr = P4_CCCR_THREAD_ANY; 177a072738eSCyrill Gorcunov 178a072738eSCyrill Gorcunov if (!p4_ht_thread(cpu)) 179a072738eSCyrill Gorcunov cccr |= P4_CCCR_OVF_PMI_T0; 180a072738eSCyrill Gorcunov else 181a072738eSCyrill Gorcunov cccr |= P4_CCCR_OVF_PMI_T1; 182a072738eSCyrill Gorcunov 183a072738eSCyrill Gorcunov return cccr; 184a072738eSCyrill Gorcunov } 185a072738eSCyrill Gorcunov 186a072738eSCyrill Gorcunov static inline u32 p4_default_escr_conf(int cpu, int exclude_os, int exclude_usr) 187a072738eSCyrill Gorcunov { 188a072738eSCyrill Gorcunov u32 escr = 0; 189a072738eSCyrill Gorcunov 190a072738eSCyrill Gorcunov if (!p4_ht_thread(cpu)) { 191a072738eSCyrill Gorcunov if (!exclude_os) 192d814f301SCyrill Gorcunov escr |= P4_ESCR_T0_OS; 193a072738eSCyrill Gorcunov if (!exclude_usr) 194d814f301SCyrill Gorcunov escr |= P4_ESCR_T0_USR; 195a072738eSCyrill Gorcunov } else { 196a072738eSCyrill Gorcunov if (!exclude_os) 197d814f301SCyrill Gorcunov escr |= P4_ESCR_T1_OS; 198a072738eSCyrill Gorcunov if (!exclude_usr) 199d814f301SCyrill Gorcunov escr |= P4_ESCR_T1_USR; 200a072738eSCyrill Gorcunov } 201a072738eSCyrill Gorcunov 202a072738eSCyrill Gorcunov return escr; 203a072738eSCyrill Gorcunov } 204a072738eSCyrill Gorcunov 20539ef13a4SCyrill Gorcunov /* 20639ef13a4SCyrill Gorcunov * This are the events which should be used in "Event Select" 20739ef13a4SCyrill Gorcunov * field of ESCR register, they are like unique keys which allow 20839ef13a4SCyrill Gorcunov * the kernel to determinate which CCCR and COUNTER should be 20939ef13a4SCyrill Gorcunov * used to track an event 21039ef13a4SCyrill Gorcunov */ 211d814f301SCyrill Gorcunov enum P4_EVENTS { 212d814f301SCyrill Gorcunov P4_EVENT_TC_DELIVER_MODE, 213d814f301SCyrill Gorcunov P4_EVENT_BPU_FETCH_REQUEST, 214d814f301SCyrill Gorcunov P4_EVENT_ITLB_REFERENCE, 215d814f301SCyrill Gorcunov P4_EVENT_MEMORY_CANCEL, 216d814f301SCyrill Gorcunov P4_EVENT_MEMORY_COMPLETE, 217d814f301SCyrill Gorcunov P4_EVENT_LOAD_PORT_REPLAY, 218d814f301SCyrill Gorcunov P4_EVENT_STORE_PORT_REPLAY, 219d814f301SCyrill Gorcunov P4_EVENT_MOB_LOAD_REPLAY, 220d814f301SCyrill Gorcunov P4_EVENT_PAGE_WALK_TYPE, 221d814f301SCyrill Gorcunov P4_EVENT_BSQ_CACHE_REFERENCE, 222d814f301SCyrill Gorcunov P4_EVENT_IOQ_ALLOCATION, 223d814f301SCyrill Gorcunov P4_EVENT_IOQ_ACTIVE_ENTRIES, 224d814f301SCyrill Gorcunov P4_EVENT_FSB_DATA_ACTIVITY, 225d814f301SCyrill Gorcunov P4_EVENT_BSQ_ALLOCATION, 226d814f301SCyrill Gorcunov P4_EVENT_BSQ_ACTIVE_ENTRIES, 227d814f301SCyrill Gorcunov P4_EVENT_SSE_INPUT_ASSIST, 228d814f301SCyrill Gorcunov P4_EVENT_PACKED_SP_UOP, 229d814f301SCyrill Gorcunov P4_EVENT_PACKED_DP_UOP, 230d814f301SCyrill Gorcunov P4_EVENT_SCALAR_SP_UOP, 231d814f301SCyrill Gorcunov P4_EVENT_SCALAR_DP_UOP, 232d814f301SCyrill Gorcunov P4_EVENT_64BIT_MMX_UOP, 233d814f301SCyrill Gorcunov P4_EVENT_128BIT_MMX_UOP, 234d814f301SCyrill Gorcunov P4_EVENT_X87_FP_UOP, 235d814f301SCyrill Gorcunov P4_EVENT_TC_MISC, 236d814f301SCyrill Gorcunov P4_EVENT_GLOBAL_POWER_EVENTS, 237d814f301SCyrill Gorcunov P4_EVENT_TC_MS_XFER, 238d814f301SCyrill Gorcunov P4_EVENT_UOP_QUEUE_WRITES, 239d814f301SCyrill Gorcunov P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE, 240d814f301SCyrill Gorcunov P4_EVENT_RETIRED_BRANCH_TYPE, 241d814f301SCyrill Gorcunov P4_EVENT_RESOURCE_STALL, 242d814f301SCyrill Gorcunov P4_EVENT_WC_BUFFER, 243d814f301SCyrill Gorcunov P4_EVENT_B2B_CYCLES, 244d814f301SCyrill Gorcunov P4_EVENT_BNR, 245d814f301SCyrill Gorcunov P4_EVENT_SNOOP, 246d814f301SCyrill Gorcunov P4_EVENT_RESPONSE, 247d814f301SCyrill Gorcunov P4_EVENT_FRONT_END_EVENT, 248d814f301SCyrill Gorcunov P4_EVENT_EXECUTION_EVENT, 249d814f301SCyrill Gorcunov P4_EVENT_REPLAY_EVENT, 250d814f301SCyrill Gorcunov P4_EVENT_INSTR_RETIRED, 251d814f301SCyrill Gorcunov P4_EVENT_UOPS_RETIRED, 252d814f301SCyrill Gorcunov P4_EVENT_UOP_TYPE, 253d814f301SCyrill Gorcunov P4_EVENT_BRANCH_RETIRED, 254d814f301SCyrill Gorcunov P4_EVENT_MISPRED_BRANCH_RETIRED, 255d814f301SCyrill Gorcunov P4_EVENT_X87_ASSIST, 256d814f301SCyrill Gorcunov P4_EVENT_MACHINE_CLEAR, 257d814f301SCyrill Gorcunov P4_EVENT_INSTR_COMPLETED, 258d814f301SCyrill Gorcunov }; 259d814f301SCyrill Gorcunov 260d814f301SCyrill Gorcunov #define P4_OPCODE(event) event##_OPCODE 261d814f301SCyrill Gorcunov #define P4_OPCODE_ESEL(opcode) ((opcode & 0x00ff) >> 0) 262d814f301SCyrill Gorcunov #define P4_OPCODE_EVNT(opcode) ((opcode & 0xff00) >> 8) 263d814f301SCyrill Gorcunov #define P4_OPCODE_PACK(event, sel) (((event) << 8) | sel) 264d814f301SCyrill Gorcunov 265a072738eSCyrill Gorcunov /* 266a072738eSCyrill Gorcunov * Comments below the event represent ESCR restriction 267a072738eSCyrill Gorcunov * for this event and counter index per ESCR 268a072738eSCyrill Gorcunov * 269a072738eSCyrill Gorcunov * MSR_P4_IQ_ESCR0 and MSR_P4_IQ_ESCR1 are available only on early 270a072738eSCyrill Gorcunov * processor builds (family 0FH, models 01H-02H). These MSRs 271a072738eSCyrill Gorcunov * are not available on later versions, so that we don't use 272a072738eSCyrill Gorcunov * them completely 273a072738eSCyrill Gorcunov * 274a072738eSCyrill Gorcunov * Also note that CCCR1 do not have P4_CCCR_ENABLE bit properly 275a072738eSCyrill Gorcunov * working so that we should not use this CCCR and respective 276a072738eSCyrill Gorcunov * counter as result 277a072738eSCyrill Gorcunov */ 278d814f301SCyrill Gorcunov enum P4_EVENT_OPCODES { 279d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_TC_DELIVER_MODE) = P4_OPCODE_PACK(0x01, 0x01), 280a072738eSCyrill Gorcunov /* 281a072738eSCyrill Gorcunov * MSR_P4_TC_ESCR0: 4, 5 282a072738eSCyrill Gorcunov * MSR_P4_TC_ESCR1: 6, 7 283a072738eSCyrill Gorcunov */ 284a072738eSCyrill Gorcunov 285d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_BPU_FETCH_REQUEST) = P4_OPCODE_PACK(0x03, 0x00), 286a072738eSCyrill Gorcunov /* 287a072738eSCyrill Gorcunov * MSR_P4_BPU_ESCR0: 0, 1 288a072738eSCyrill Gorcunov * MSR_P4_BPU_ESCR1: 2, 3 289a072738eSCyrill Gorcunov */ 290a072738eSCyrill Gorcunov 291d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_ITLB_REFERENCE) = P4_OPCODE_PACK(0x18, 0x03), 292a072738eSCyrill Gorcunov /* 293a072738eSCyrill Gorcunov * MSR_P4_ITLB_ESCR0: 0, 1 294a072738eSCyrill Gorcunov * MSR_P4_ITLB_ESCR1: 2, 3 295a072738eSCyrill Gorcunov */ 296a072738eSCyrill Gorcunov 297d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_MEMORY_CANCEL) = P4_OPCODE_PACK(0x02, 0x05), 298a072738eSCyrill Gorcunov /* 299a072738eSCyrill Gorcunov * MSR_P4_DAC_ESCR0: 8, 9 300a072738eSCyrill Gorcunov * MSR_P4_DAC_ESCR1: 10, 11 301a072738eSCyrill Gorcunov */ 302a072738eSCyrill Gorcunov 303d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_MEMORY_COMPLETE) = P4_OPCODE_PACK(0x08, 0x02), 304a072738eSCyrill Gorcunov /* 305a072738eSCyrill Gorcunov * MSR_P4_SAAT_ESCR0: 8, 9 306a072738eSCyrill Gorcunov * MSR_P4_SAAT_ESCR1: 10, 11 307a072738eSCyrill Gorcunov */ 308a072738eSCyrill Gorcunov 309d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_LOAD_PORT_REPLAY) = P4_OPCODE_PACK(0x04, 0x02), 310a072738eSCyrill Gorcunov /* 311a072738eSCyrill Gorcunov * MSR_P4_SAAT_ESCR0: 8, 9 312a072738eSCyrill Gorcunov * MSR_P4_SAAT_ESCR1: 10, 11 313a072738eSCyrill Gorcunov */ 314a072738eSCyrill Gorcunov 315d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_STORE_PORT_REPLAY) = P4_OPCODE_PACK(0x05, 0x02), 316a072738eSCyrill Gorcunov /* 317a072738eSCyrill Gorcunov * MSR_P4_SAAT_ESCR0: 8, 9 318a072738eSCyrill Gorcunov * MSR_P4_SAAT_ESCR1: 10, 11 319a072738eSCyrill Gorcunov */ 320a072738eSCyrill Gorcunov 321d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_MOB_LOAD_REPLAY) = P4_OPCODE_PACK(0x03, 0x02), 322a072738eSCyrill Gorcunov /* 323a072738eSCyrill Gorcunov * MSR_P4_MOB_ESCR0: 0, 1 324a072738eSCyrill Gorcunov * MSR_P4_MOB_ESCR1: 2, 3 325a072738eSCyrill Gorcunov */ 326a072738eSCyrill Gorcunov 327d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_PAGE_WALK_TYPE) = P4_OPCODE_PACK(0x01, 0x04), 328a072738eSCyrill Gorcunov /* 329a072738eSCyrill Gorcunov * MSR_P4_PMH_ESCR0: 0, 1 330a072738eSCyrill Gorcunov * MSR_P4_PMH_ESCR1: 2, 3 331a072738eSCyrill Gorcunov */ 332a072738eSCyrill Gorcunov 333d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_BSQ_CACHE_REFERENCE) = P4_OPCODE_PACK(0x0c, 0x07), 334a072738eSCyrill Gorcunov /* 335a072738eSCyrill Gorcunov * MSR_P4_BSU_ESCR0: 0, 1 336a072738eSCyrill Gorcunov * MSR_P4_BSU_ESCR1: 2, 3 337a072738eSCyrill Gorcunov */ 338a072738eSCyrill Gorcunov 339d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_IOQ_ALLOCATION) = P4_OPCODE_PACK(0x03, 0x06), 340a072738eSCyrill Gorcunov /* 341a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR0: 0, 1 342a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR1: 2, 3 343a072738eSCyrill Gorcunov */ 344a072738eSCyrill Gorcunov 345d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_IOQ_ACTIVE_ENTRIES) = P4_OPCODE_PACK(0x1a, 0x06), 346a072738eSCyrill Gorcunov /* 347a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR1: 2, 3 348a072738eSCyrill Gorcunov */ 349a072738eSCyrill Gorcunov 350d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_FSB_DATA_ACTIVITY) = P4_OPCODE_PACK(0x17, 0x06), 351a072738eSCyrill Gorcunov /* 352a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR0: 0, 1 353a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR1: 2, 3 354a072738eSCyrill Gorcunov */ 355a072738eSCyrill Gorcunov 356d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_BSQ_ALLOCATION) = P4_OPCODE_PACK(0x05, 0x07), 357a072738eSCyrill Gorcunov /* 358a072738eSCyrill Gorcunov * MSR_P4_BSU_ESCR0: 0, 1 359a072738eSCyrill Gorcunov */ 360a072738eSCyrill Gorcunov 361d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_BSQ_ACTIVE_ENTRIES) = P4_OPCODE_PACK(0x06, 0x07), 362a072738eSCyrill Gorcunov /* 3638ea7f544SLin Ming * NOTE: no ESCR name in docs, it's guessed 364a072738eSCyrill Gorcunov * MSR_P4_BSU_ESCR1: 2, 3 365a072738eSCyrill Gorcunov */ 366a072738eSCyrill Gorcunov 367d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_SSE_INPUT_ASSIST) = P4_OPCODE_PACK(0x34, 0x01), 368a072738eSCyrill Gorcunov /* 369e4495262SCyrill Gorcunov * MSR_P4_FIRM_ESCR0: 8, 9 370e4495262SCyrill Gorcunov * MSR_P4_FIRM_ESCR1: 10, 11 371a072738eSCyrill Gorcunov */ 372a072738eSCyrill Gorcunov 373d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_PACKED_SP_UOP) = P4_OPCODE_PACK(0x08, 0x01), 374a072738eSCyrill Gorcunov /* 375a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR0: 8, 9 376a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR1: 10, 11 377a072738eSCyrill Gorcunov */ 378a072738eSCyrill Gorcunov 379d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_PACKED_DP_UOP) = P4_OPCODE_PACK(0x0c, 0x01), 380a072738eSCyrill Gorcunov /* 381a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR0: 8, 9 382a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR1: 10, 11 383a072738eSCyrill Gorcunov */ 384a072738eSCyrill Gorcunov 385d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_SCALAR_SP_UOP) = P4_OPCODE_PACK(0x0a, 0x01), 386a072738eSCyrill Gorcunov /* 387a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR0: 8, 9 388a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR1: 10, 11 389a072738eSCyrill Gorcunov */ 390a072738eSCyrill Gorcunov 391d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_SCALAR_DP_UOP) = P4_OPCODE_PACK(0x0e, 0x01), 392a072738eSCyrill Gorcunov /* 393a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR0: 8, 9 394a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR1: 10, 11 395a072738eSCyrill Gorcunov */ 396a072738eSCyrill Gorcunov 397d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_64BIT_MMX_UOP) = P4_OPCODE_PACK(0x02, 0x01), 398a072738eSCyrill Gorcunov /* 399a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR0: 8, 9 400a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR1: 10, 11 401a072738eSCyrill Gorcunov */ 402a072738eSCyrill Gorcunov 403d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_128BIT_MMX_UOP) = P4_OPCODE_PACK(0x1a, 0x01), 404a072738eSCyrill Gorcunov /* 405a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR0: 8, 9 406a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR1: 10, 11 407a072738eSCyrill Gorcunov */ 408a072738eSCyrill Gorcunov 409d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_X87_FP_UOP) = P4_OPCODE_PACK(0x04, 0x01), 410a072738eSCyrill Gorcunov /* 411a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR0: 8, 9 412a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR1: 10, 11 413a072738eSCyrill Gorcunov */ 414a072738eSCyrill Gorcunov 415d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_TC_MISC) = P4_OPCODE_PACK(0x06, 0x01), 416a072738eSCyrill Gorcunov /* 417a072738eSCyrill Gorcunov * MSR_P4_TC_ESCR0: 4, 5 418a072738eSCyrill Gorcunov * MSR_P4_TC_ESCR1: 6, 7 419a072738eSCyrill Gorcunov */ 420a072738eSCyrill Gorcunov 421d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_GLOBAL_POWER_EVENTS) = P4_OPCODE_PACK(0x13, 0x06), 422a072738eSCyrill Gorcunov /* 423a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR0: 0, 1 424a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR1: 2, 3 425a072738eSCyrill Gorcunov */ 426a072738eSCyrill Gorcunov 427d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_TC_MS_XFER) = P4_OPCODE_PACK(0x05, 0x00), 428a072738eSCyrill Gorcunov /* 429a072738eSCyrill Gorcunov * MSR_P4_MS_ESCR0: 4, 5 430a072738eSCyrill Gorcunov * MSR_P4_MS_ESCR1: 6, 7 431a072738eSCyrill Gorcunov */ 432a072738eSCyrill Gorcunov 433d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_UOP_QUEUE_WRITES) = P4_OPCODE_PACK(0x09, 0x00), 434a072738eSCyrill Gorcunov /* 435a072738eSCyrill Gorcunov * MSR_P4_MS_ESCR0: 4, 5 436a072738eSCyrill Gorcunov * MSR_P4_MS_ESCR1: 6, 7 437a072738eSCyrill Gorcunov */ 438a072738eSCyrill Gorcunov 439d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE) = P4_OPCODE_PACK(0x05, 0x02), 440a072738eSCyrill Gorcunov /* 441a072738eSCyrill Gorcunov * MSR_P4_TBPU_ESCR0: 4, 5 4429c8c6badSCyrill Gorcunov * MSR_P4_TBPU_ESCR1: 6, 7 443a072738eSCyrill Gorcunov */ 444a072738eSCyrill Gorcunov 445d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_RETIRED_BRANCH_TYPE) = P4_OPCODE_PACK(0x04, 0x02), 446a072738eSCyrill Gorcunov /* 447a072738eSCyrill Gorcunov * MSR_P4_TBPU_ESCR0: 4, 5 4489c8c6badSCyrill Gorcunov * MSR_P4_TBPU_ESCR1: 6, 7 449a072738eSCyrill Gorcunov */ 450a072738eSCyrill Gorcunov 451d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_RESOURCE_STALL) = P4_OPCODE_PACK(0x01, 0x01), 452a072738eSCyrill Gorcunov /* 453a072738eSCyrill Gorcunov * MSR_P4_ALF_ESCR0: 12, 13, 16 454a072738eSCyrill Gorcunov * MSR_P4_ALF_ESCR1: 14, 15, 17 455a072738eSCyrill Gorcunov */ 456a072738eSCyrill Gorcunov 457d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_WC_BUFFER) = P4_OPCODE_PACK(0x05, 0x05), 458a072738eSCyrill Gorcunov /* 459a072738eSCyrill Gorcunov * MSR_P4_DAC_ESCR0: 8, 9 460a072738eSCyrill Gorcunov * MSR_P4_DAC_ESCR1: 10, 11 461a072738eSCyrill Gorcunov */ 462a072738eSCyrill Gorcunov 463d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_B2B_CYCLES) = P4_OPCODE_PACK(0x16, 0x03), 464a072738eSCyrill Gorcunov /* 465a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR0: 0, 1 466a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR1: 2, 3 467a072738eSCyrill Gorcunov */ 468a072738eSCyrill Gorcunov 469d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_BNR) = P4_OPCODE_PACK(0x08, 0x03), 470a072738eSCyrill Gorcunov /* 471a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR0: 0, 1 472a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR1: 2, 3 473a072738eSCyrill Gorcunov */ 474a072738eSCyrill Gorcunov 475d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_SNOOP) = P4_OPCODE_PACK(0x06, 0x03), 476a072738eSCyrill Gorcunov /* 477a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR0: 0, 1 478a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR1: 2, 3 479a072738eSCyrill Gorcunov */ 480a072738eSCyrill Gorcunov 481d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_RESPONSE) = P4_OPCODE_PACK(0x04, 0x03), 482a072738eSCyrill Gorcunov /* 483a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR0: 0, 1 484a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR1: 2, 3 485a072738eSCyrill Gorcunov */ 486a072738eSCyrill Gorcunov 487d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_FRONT_END_EVENT) = P4_OPCODE_PACK(0x08, 0x05), 488a072738eSCyrill Gorcunov /* 489a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR2: 12, 13, 16 490a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR3: 14, 15, 17 491a072738eSCyrill Gorcunov */ 492a072738eSCyrill Gorcunov 493d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_EXECUTION_EVENT) = P4_OPCODE_PACK(0x0c, 0x05), 494a072738eSCyrill Gorcunov /* 495a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR2: 12, 13, 16 496a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR3: 14, 15, 17 497a072738eSCyrill Gorcunov */ 498a072738eSCyrill Gorcunov 499d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_REPLAY_EVENT) = P4_OPCODE_PACK(0x09, 0x05), 500a072738eSCyrill Gorcunov /* 501a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR2: 12, 13, 16 502a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR3: 14, 15, 17 503a072738eSCyrill Gorcunov */ 504a072738eSCyrill Gorcunov 505d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_INSTR_RETIRED) = P4_OPCODE_PACK(0x02, 0x04), 506a072738eSCyrill Gorcunov /* 507e4495262SCyrill Gorcunov * MSR_P4_CRU_ESCR0: 12, 13, 16 508e4495262SCyrill Gorcunov * MSR_P4_CRU_ESCR1: 14, 15, 17 509a072738eSCyrill Gorcunov */ 510a072738eSCyrill Gorcunov 511d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_UOPS_RETIRED) = P4_OPCODE_PACK(0x01, 0x04), 512a072738eSCyrill Gorcunov /* 5138ea7f544SLin Ming * MSR_P4_CRU_ESCR0: 12, 13, 16 5148ea7f544SLin Ming * MSR_P4_CRU_ESCR1: 14, 15, 17 515a072738eSCyrill Gorcunov */ 516a072738eSCyrill Gorcunov 517d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_UOP_TYPE) = P4_OPCODE_PACK(0x02, 0x02), 518a072738eSCyrill Gorcunov /* 519a072738eSCyrill Gorcunov * MSR_P4_RAT_ESCR0: 12, 13, 16 520a072738eSCyrill Gorcunov * MSR_P4_RAT_ESCR1: 14, 15, 17 521a072738eSCyrill Gorcunov */ 522a072738eSCyrill Gorcunov 523d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_BRANCH_RETIRED) = P4_OPCODE_PACK(0x06, 0x05), 524a072738eSCyrill Gorcunov /* 525a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR2: 12, 13, 16 526a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR3: 14, 15, 17 527a072738eSCyrill Gorcunov */ 528a072738eSCyrill Gorcunov 529d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_MISPRED_BRANCH_RETIRED) = P4_OPCODE_PACK(0x03, 0x04), 530a072738eSCyrill Gorcunov /* 531a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR0: 12, 13, 16 532a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR1: 14, 15, 17 533a072738eSCyrill Gorcunov */ 534a072738eSCyrill Gorcunov 535d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_X87_ASSIST) = P4_OPCODE_PACK(0x03, 0x05), 536a072738eSCyrill Gorcunov /* 537a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR2: 12, 13, 16 538a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR3: 14, 15, 17 539a072738eSCyrill Gorcunov */ 540a072738eSCyrill Gorcunov 541d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_MACHINE_CLEAR) = P4_OPCODE_PACK(0x02, 0x05), 542a072738eSCyrill Gorcunov /* 543a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR2: 12, 13, 16 544a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR3: 14, 15, 17 545a072738eSCyrill Gorcunov */ 546a072738eSCyrill Gorcunov 547d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_INSTR_COMPLETED) = P4_OPCODE_PACK(0x07, 0x04), 548a072738eSCyrill Gorcunov /* 549a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR0: 12, 13, 16 550a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR1: 14, 15, 17 551a072738eSCyrill Gorcunov */ 552a072738eSCyrill Gorcunov }; 553a072738eSCyrill Gorcunov 554d814f301SCyrill Gorcunov /* 555d814f301SCyrill Gorcunov * a caller should use P4_ESCR_EMASK_NAME helper to 556d814f301SCyrill Gorcunov * pick the EventMask needed, for example 557d814f301SCyrill Gorcunov * 55839ef13a4SCyrill Gorcunov * P4_ESCR_EMASK_BIT(P4_EVENT_TC_DELIVER_MODE, DD) 559d814f301SCyrill Gorcunov */ 560d814f301SCyrill Gorcunov enum P4_ESCR_EMASKS { 561d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, DD, 0), 562d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, DB, 1), 563d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, DI, 2), 564d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, BD, 3), 565d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, BB, 4), 566d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, BI, 5), 567d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, ID, 6), 568d814f301SCyrill Gorcunov 569d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BPU_FETCH_REQUEST, TCMISS, 0), 570d814f301SCyrill Gorcunov 571d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_ITLB_REFERENCE, HIT, 0), 572d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_ITLB_REFERENCE, MISS, 1), 573d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_ITLB_REFERENCE, HIT_UK, 2), 574d814f301SCyrill Gorcunov 575d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_MEMORY_CANCEL, ST_RB_FULL, 2), 576d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_MEMORY_CANCEL, 64K_CONF, 3), 577d814f301SCyrill Gorcunov 578d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_MEMORY_COMPLETE, LSC, 0), 579d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_MEMORY_COMPLETE, SSC, 1), 580d814f301SCyrill Gorcunov 581d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_LOAD_PORT_REPLAY, SPLIT_LD, 1), 582d814f301SCyrill Gorcunov 583d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_STORE_PORT_REPLAY, SPLIT_ST, 1), 584d814f301SCyrill Gorcunov 585d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_MOB_LOAD_REPLAY, NO_STA, 1), 586d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_MOB_LOAD_REPLAY, NO_STD, 3), 587d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_MOB_LOAD_REPLAY, PARTIAL_DATA, 4), 588d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_MOB_LOAD_REPLAY, UNALGN_ADDR, 5), 589d814f301SCyrill Gorcunov 590d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_PAGE_WALK_TYPE, DTMISS, 0), 591d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_PAGE_WALK_TYPE, ITMISS, 1), 592d814f301SCyrill Gorcunov 593d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_HITS, 0), 594d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_HITE, 1), 595d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_HITM, 2), 596d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_HITS, 3), 597d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_HITE, 4), 598d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_HITM, 5), 599d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_MISS, 8), 600d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_MISS, 9), 601d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, WR_2ndL_MISS, 10), 602d814f301SCyrill Gorcunov 603d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, DEFAULT, 0), 604d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, ALL_READ, 5), 605d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, ALL_WRITE, 6), 606d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, MEM_UC, 7), 607d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, MEM_WC, 8), 608d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, MEM_WT, 9), 609d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, MEM_WP, 10), 610d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, MEM_WB, 11), 611d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, OWN, 13), 612d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, OTHER, 14), 613d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, PREFETCH, 15), 614d814f301SCyrill Gorcunov 615d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, DEFAULT, 0), 616d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, ALL_READ, 5), 617d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, ALL_WRITE, 6), 618d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, MEM_UC, 7), 619d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, MEM_WC, 8), 620d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, MEM_WT, 9), 621d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, MEM_WP, 10), 622d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, MEM_WB, 11), 623d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, OWN, 13), 624d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, OTHER, 14), 625d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, PREFETCH, 15), 626d814f301SCyrill Gorcunov 627d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_FSB_DATA_ACTIVITY, DRDY_DRV, 0), 628d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_FSB_DATA_ACTIVITY, DRDY_OWN, 1), 629d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_FSB_DATA_ACTIVITY, DRDY_OTHER, 2), 630d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_FSB_DATA_ACTIVITY, DBSY_DRV, 3), 631d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_FSB_DATA_ACTIVITY, DBSY_OWN, 4), 632d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_FSB_DATA_ACTIVITY, DBSY_OTHER, 5), 633d814f301SCyrill Gorcunov 634d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_TYPE0, 0), 635d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_TYPE1, 1), 636d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_LEN0, 2), 637d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_LEN1, 3), 638d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_IO_TYPE, 5), 639d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_LOCK_TYPE, 6), 640d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_CACHE_TYPE, 7), 641d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_SPLIT_TYPE, 8), 642d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_DEM_TYPE, 9), 643d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_ORD_TYPE, 10), 644d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, MEM_TYPE0, 11), 645d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, MEM_TYPE1, 12), 646d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, MEM_TYPE2, 13), 647d814f301SCyrill Gorcunov 648d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_TYPE0, 0), 649d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_TYPE1, 1), 650d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_LEN0, 2), 651d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_LEN1, 3), 652d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_IO_TYPE, 5), 653d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_LOCK_TYPE, 6), 654d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_CACHE_TYPE, 7), 655d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_SPLIT_TYPE, 8), 656d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_DEM_TYPE, 9), 657d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_ORD_TYPE, 10), 658d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, MEM_TYPE0, 11), 659d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, MEM_TYPE1, 12), 660d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, MEM_TYPE2, 13), 661d814f301SCyrill Gorcunov 662d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_SSE_INPUT_ASSIST, ALL, 15), 663d814f301SCyrill Gorcunov 664d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_PACKED_SP_UOP, ALL, 15), 665d814f301SCyrill Gorcunov 666d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_PACKED_DP_UOP, ALL, 15), 667d814f301SCyrill Gorcunov 668d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_SCALAR_SP_UOP, ALL, 15), 669d814f301SCyrill Gorcunov 670d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_SCALAR_DP_UOP, ALL, 15), 671d814f301SCyrill Gorcunov 672d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_64BIT_MMX_UOP, ALL, 15), 673d814f301SCyrill Gorcunov 674d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_128BIT_MMX_UOP, ALL, 15), 675d814f301SCyrill Gorcunov 676d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_X87_FP_UOP, ALL, 15), 677d814f301SCyrill Gorcunov 678d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_TC_MISC, FLUSH, 4), 679d814f301SCyrill Gorcunov 680d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_GLOBAL_POWER_EVENTS, RUNNING, 0), 681d814f301SCyrill Gorcunov 682d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_TC_MS_XFER, CISC, 0), 683d814f301SCyrill Gorcunov 684d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_UOP_QUEUE_WRITES, FROM_TC_BUILD, 0), 685d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_UOP_QUEUE_WRITES, FROM_TC_DELIVER, 1), 686d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_UOP_QUEUE_WRITES, FROM_ROM, 2), 687d814f301SCyrill Gorcunov 688d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE, CONDITIONAL, 1), 689d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE, CALL, 2), 690d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE, RETURN, 3), 691d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE, INDIRECT, 4), 692d814f301SCyrill Gorcunov 693d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_BRANCH_TYPE, CONDITIONAL, 1), 694d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_BRANCH_TYPE, CALL, 2), 695d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_BRANCH_TYPE, RETURN, 3), 696d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_BRANCH_TYPE, INDIRECT, 4), 697d814f301SCyrill Gorcunov 698d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_RESOURCE_STALL, SBFULL, 5), 699d814f301SCyrill Gorcunov 700d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_WC_BUFFER, WCB_EVICTS, 0), 701d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_WC_BUFFER, WCB_FULL_EVICTS, 1), 702d814f301SCyrill Gorcunov 703d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_FRONT_END_EVENT, NBOGUS, 0), 704d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_FRONT_END_EVENT, BOGUS, 1), 705d814f301SCyrill Gorcunov 706d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, NBOGUS0, 0), 707d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, NBOGUS1, 1), 708d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, NBOGUS2, 2), 709d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, NBOGUS3, 3), 710d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, BOGUS0, 4), 711d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, BOGUS1, 5), 712d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, BOGUS2, 6), 713d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, BOGUS3, 7), 714d814f301SCyrill Gorcunov 715d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_REPLAY_EVENT, NBOGUS, 0), 716d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_REPLAY_EVENT, BOGUS, 1), 717d814f301SCyrill Gorcunov 718d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_INSTR_RETIRED, NBOGUSNTAG, 0), 719d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_INSTR_RETIRED, NBOGUSTAG, 1), 720d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_INSTR_RETIRED, BOGUSNTAG, 2), 721d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_INSTR_RETIRED, BOGUSTAG, 3), 722d814f301SCyrill Gorcunov 723d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_UOPS_RETIRED, NBOGUS, 0), 724d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_UOPS_RETIRED, BOGUS, 1), 725d814f301SCyrill Gorcunov 726d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_UOP_TYPE, TAGLOADS, 1), 727d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_UOP_TYPE, TAGSTORES, 2), 728d814f301SCyrill Gorcunov 729d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BRANCH_RETIRED, MMNP, 0), 730d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BRANCH_RETIRED, MMNM, 1), 731d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BRANCH_RETIRED, MMTP, 2), 732d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BRANCH_RETIRED, MMTM, 3), 733d814f301SCyrill Gorcunov 734d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_MISPRED_BRANCH_RETIRED, NBOGUS, 0), 735d814f301SCyrill Gorcunov 736d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_X87_ASSIST, FPSU, 0), 737d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_X87_ASSIST, FPSO, 1), 738d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_X87_ASSIST, POAO, 2), 739d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_X87_ASSIST, POAU, 3), 740d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_X87_ASSIST, PREA, 4), 741d814f301SCyrill Gorcunov 742d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_MACHINE_CLEAR, CLEAR, 0), 743d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_MACHINE_CLEAR, MOCLEAR, 1), 744d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_MACHINE_CLEAR, SMCLEAR, 2), 745d814f301SCyrill Gorcunov 746d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_INSTR_COMPLETED, NBOGUS, 0), 747d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_INSTR_COMPLETED, BOGUS, 1), 748d814f301SCyrill Gorcunov }; 749d814f301SCyrill Gorcunov 75039ef13a4SCyrill Gorcunov /* 75139ef13a4SCyrill Gorcunov * Note we have UOP and PEBS bits reserved for now 75239ef13a4SCyrill Gorcunov * just in case if we will need them once 75339ef13a4SCyrill Gorcunov */ 75439ef13a4SCyrill Gorcunov #define P4_PEBS_CONFIG_ENABLE (1 << 7) 75539ef13a4SCyrill Gorcunov #define P4_PEBS_CONFIG_UOP_TAG (1 << 8) 75639ef13a4SCyrill Gorcunov #define P4_PEBS_CONFIG_METRIC_MASK 0x3f 75739ef13a4SCyrill Gorcunov #define P4_PEBS_CONFIG_MASK 0xff 75839ef13a4SCyrill Gorcunov 75939ef13a4SCyrill Gorcunov /* 76039ef13a4SCyrill Gorcunov * mem: Only counters MSR_IQ_COUNTER4 (16) and 76139ef13a4SCyrill Gorcunov * MSR_IQ_COUNTER5 (17) are allowed for PEBS sampling 76239ef13a4SCyrill Gorcunov */ 763d814f301SCyrill Gorcunov #define P4_PEBS_ENABLE 0x02000000U 76439ef13a4SCyrill Gorcunov #define P4_PEBS_ENABLE_UOP_TAG 0x01000000U 765d814f301SCyrill Gorcunov 76639ef13a4SCyrill Gorcunov #define p4_config_unpack_metric(v) (((u64)(v)) & P4_PEBS_CONFIG_METRIC_MASK) 76739ef13a4SCyrill Gorcunov #define p4_config_unpack_pebs(v) (((u64)(v)) & P4_PEBS_CONFIG_MASK) 768d814f301SCyrill Gorcunov 76939ef13a4SCyrill Gorcunov #define p4_config_pebs_has(v, mask) (p4_config_unpack_pebs(v) & (mask)) 770d814f301SCyrill Gorcunov 77139ef13a4SCyrill Gorcunov enum P4_PEBS_METRIC { 77239ef13a4SCyrill Gorcunov P4_PEBS_METRIC__none, 773d814f301SCyrill Gorcunov 77439ef13a4SCyrill Gorcunov P4_PEBS_METRIC__1stl_cache_load_miss_retired, 77539ef13a4SCyrill Gorcunov P4_PEBS_METRIC__2ndl_cache_load_miss_retired, 77639ef13a4SCyrill Gorcunov P4_PEBS_METRIC__dtlb_load_miss_retired, 77739ef13a4SCyrill Gorcunov P4_PEBS_METRIC__dtlb_store_miss_retired, 77839ef13a4SCyrill Gorcunov P4_PEBS_METRIC__dtlb_all_miss_retired, 77939ef13a4SCyrill Gorcunov P4_PEBS_METRIC__tagged_mispred_branch, 78039ef13a4SCyrill Gorcunov P4_PEBS_METRIC__mob_load_replay_retired, 78139ef13a4SCyrill Gorcunov P4_PEBS_METRIC__split_load_retired, 78239ef13a4SCyrill Gorcunov P4_PEBS_METRIC__split_store_retired, 783d814f301SCyrill Gorcunov 78439ef13a4SCyrill Gorcunov P4_PEBS_METRIC__max 785cb7d6b50SLin Ming }; 786cb7d6b50SLin Ming 787af86da53SCyrill Gorcunov /* 788af86da53SCyrill Gorcunov * Notes on internal configuration of ESCR+CCCR tuples 789af86da53SCyrill Gorcunov * 790af86da53SCyrill Gorcunov * Since P4 has quite the different architecture of 791af86da53SCyrill Gorcunov * performance registers in compare with "architectural" 792af86da53SCyrill Gorcunov * once and we have on 64 bits to keep configuration 793af86da53SCyrill Gorcunov * of performance event, the following trick is used. 794af86da53SCyrill Gorcunov * 795af86da53SCyrill Gorcunov * 1) Since both ESCR and CCCR registers have only low 796af86da53SCyrill Gorcunov * 32 bits valuable, we pack them into a single 64 bit 797af86da53SCyrill Gorcunov * configuration. Low 32 bits of such config correspond 798af86da53SCyrill Gorcunov * to low 32 bits of CCCR register and high 32 bits 799af86da53SCyrill Gorcunov * correspond to low 32 bits of ESCR register. 800af86da53SCyrill Gorcunov * 801af86da53SCyrill Gorcunov * 2) The meaning of every bit of such config field can 802af86da53SCyrill Gorcunov * be found in Intel SDM but it should be noted that 803af86da53SCyrill Gorcunov * we "borrow" some reserved bits for own usage and 804af86da53SCyrill Gorcunov * clean them or set to a proper value when we do 805af86da53SCyrill Gorcunov * a real write to hardware registers. 806af86da53SCyrill Gorcunov * 807af86da53SCyrill Gorcunov * 3) The format of bits of config is the following 808af86da53SCyrill Gorcunov * and should be either 0 or set to some predefined 809af86da53SCyrill Gorcunov * values: 810af86da53SCyrill Gorcunov * 811af86da53SCyrill Gorcunov * Low 32 bits 812af86da53SCyrill Gorcunov * ----------- 813af86da53SCyrill Gorcunov * 0-6: P4_PEBS_METRIC enum 814af86da53SCyrill Gorcunov * 7-11: reserved 815af86da53SCyrill Gorcunov * 12: reserved (Enable) 816af86da53SCyrill Gorcunov * 13-15: reserved (ESCR select) 817af86da53SCyrill Gorcunov * 16-17: Active Thread 818af86da53SCyrill Gorcunov * 18: Compare 819af86da53SCyrill Gorcunov * 19: Complement 820af86da53SCyrill Gorcunov * 20-23: Threshold 821af86da53SCyrill Gorcunov * 24: Edge 822af86da53SCyrill Gorcunov * 25: reserved (FORCE_OVF) 823af86da53SCyrill Gorcunov * 26: reserved (OVF_PMI_T0) 824af86da53SCyrill Gorcunov * 27: reserved (OVF_PMI_T1) 825af86da53SCyrill Gorcunov * 28-29: reserved 826af86da53SCyrill Gorcunov * 30: reserved (Cascade) 827af86da53SCyrill Gorcunov * 31: reserved (OVF) 828af86da53SCyrill Gorcunov * 829af86da53SCyrill Gorcunov * High 32 bits 830af86da53SCyrill Gorcunov * ------------ 831af86da53SCyrill Gorcunov * 0: reserved (T1_USR) 832af86da53SCyrill Gorcunov * 1: reserved (T1_OS) 833af86da53SCyrill Gorcunov * 2: reserved (T0_USR) 834af86da53SCyrill Gorcunov * 3: reserved (T0_OS) 835af86da53SCyrill Gorcunov * 4: Tag Enable 836af86da53SCyrill Gorcunov * 5-8: Tag Value 837af86da53SCyrill Gorcunov * 9-24: Event Mask (may use P4_ESCR_EMASK_BIT helper) 838af86da53SCyrill Gorcunov * 25-30: enum P4_EVENTS 839af86da53SCyrill Gorcunov * 31: reserved (HT thread) 840af86da53SCyrill Gorcunov */ 841af86da53SCyrill Gorcunov 842a072738eSCyrill Gorcunov #endif /* PERF_EVENT_P4_H */ 84339ef13a4SCyrill Gorcunov 844