1a072738eSCyrill Gorcunov /* 2a072738eSCyrill Gorcunov * Netburst Perfomance Events (P4, old Xeon) 3a072738eSCyrill Gorcunov */ 4a072738eSCyrill Gorcunov 5a072738eSCyrill Gorcunov #ifndef PERF_EVENT_P4_H 6a072738eSCyrill Gorcunov #define PERF_EVENT_P4_H 7a072738eSCyrill Gorcunov 8a072738eSCyrill Gorcunov #include <linux/cpu.h> 9a072738eSCyrill Gorcunov #include <linux/bitops.h> 10a072738eSCyrill Gorcunov 11a072738eSCyrill Gorcunov /* 12a072738eSCyrill Gorcunov * NetBurst has perfomance MSRs shared between 13a072738eSCyrill Gorcunov * threads if HT is turned on, ie for both logical 14a072738eSCyrill Gorcunov * processors (mem: in turn in Atom with HT support 15a072738eSCyrill Gorcunov * perf-MSRs are not shared and every thread has its 16a072738eSCyrill Gorcunov * own perf-MSRs set) 17a072738eSCyrill Gorcunov */ 18a072738eSCyrill Gorcunov #define ARCH_P4_TOTAL_ESCR (46) 19a072738eSCyrill Gorcunov #define ARCH_P4_RESERVED_ESCR (2) /* IQ_ESCR(0,1) not always present */ 20a072738eSCyrill Gorcunov #define ARCH_P4_MAX_ESCR (ARCH_P4_TOTAL_ESCR - ARCH_P4_RESERVED_ESCR) 21a072738eSCyrill Gorcunov #define ARCH_P4_MAX_CCCR (18) 22a072738eSCyrill Gorcunov 23*047a3772SCyrill Gorcunov #define ARCH_P4_CNTRVAL_BITS (40) 24*047a3772SCyrill Gorcunov #define ARCH_P4_CNTRVAL_MASK ((1ULL << ARCH_P4_CNTRVAL_BITS) - 1) 25*047a3772SCyrill Gorcunov 26d814f301SCyrill Gorcunov #define P4_ESCR_EVENT_MASK 0x7e000000U 27d814f301SCyrill Gorcunov #define P4_ESCR_EVENT_SHIFT 25 28d814f301SCyrill Gorcunov #define P4_ESCR_EVENTMASK_MASK 0x01fffe00U 29d814f301SCyrill Gorcunov #define P4_ESCR_EVENTMASK_SHIFT 9 30d814f301SCyrill Gorcunov #define P4_ESCR_TAG_MASK 0x000001e0U 31d814f301SCyrill Gorcunov #define P4_ESCR_TAG_SHIFT 5 32d814f301SCyrill Gorcunov #define P4_ESCR_TAG_ENABLE 0x00000010U 33d814f301SCyrill Gorcunov #define P4_ESCR_T0_OS 0x00000008U 34d814f301SCyrill Gorcunov #define P4_ESCR_T0_USR 0x00000004U 35d814f301SCyrill Gorcunov #define P4_ESCR_T1_OS 0x00000002U 36d814f301SCyrill Gorcunov #define P4_ESCR_T1_USR 0x00000001U 37d814f301SCyrill Gorcunov 38d814f301SCyrill Gorcunov #define P4_ESCR_EVENT(v) ((v) << P4_ESCR_EVENT_SHIFT) 39d814f301SCyrill Gorcunov #define P4_ESCR_EMASK(v) ((v) << P4_ESCR_EVENTMASK_SHIFT) 40d814f301SCyrill Gorcunov #define P4_ESCR_TAG(v) ((v) << P4_ESCR_TAG_SHIFT) 41a072738eSCyrill Gorcunov 42a072738eSCyrill Gorcunov #define P4_CCCR_OVF 0x80000000U 43a072738eSCyrill Gorcunov #define P4_CCCR_CASCADE 0x40000000U 44a072738eSCyrill Gorcunov #define P4_CCCR_OVF_PMI_T0 0x04000000U 45a072738eSCyrill Gorcunov #define P4_CCCR_OVF_PMI_T1 0x08000000U 46a072738eSCyrill Gorcunov #define P4_CCCR_FORCE_OVF 0x02000000U 47a072738eSCyrill Gorcunov #define P4_CCCR_EDGE 0x01000000U 48a072738eSCyrill Gorcunov #define P4_CCCR_THRESHOLD_MASK 0x00f00000U 49a072738eSCyrill Gorcunov #define P4_CCCR_THRESHOLD_SHIFT 20 50a072738eSCyrill Gorcunov #define P4_CCCR_COMPLEMENT 0x00080000U 51a072738eSCyrill Gorcunov #define P4_CCCR_COMPARE 0x00040000U 52a072738eSCyrill Gorcunov #define P4_CCCR_ESCR_SELECT_MASK 0x0000e000U 53a072738eSCyrill Gorcunov #define P4_CCCR_ESCR_SELECT_SHIFT 13 54a072738eSCyrill Gorcunov #define P4_CCCR_ENABLE 0x00001000U 55a072738eSCyrill Gorcunov #define P4_CCCR_THREAD_SINGLE 0x00010000U 56a072738eSCyrill Gorcunov #define P4_CCCR_THREAD_BOTH 0x00020000U 57a072738eSCyrill Gorcunov #define P4_CCCR_THREAD_ANY 0x00030000U 58f34edbc1SLin Ming #define P4_CCCR_RESERVED 0x00000fffU 59a072738eSCyrill Gorcunov 60d814f301SCyrill Gorcunov #define P4_CCCR_THRESHOLD(v) ((v) << P4_CCCR_THRESHOLD_SHIFT) 61d814f301SCyrill Gorcunov #define P4_CCCR_ESEL(v) ((v) << P4_CCCR_ESCR_SELECT_SHIFT) 62d814f301SCyrill Gorcunov 63d814f301SCyrill Gorcunov #define P4_GEN_ESCR_EMASK(class, name, bit) \ 64d814f301SCyrill Gorcunov class##__##name = ((1 << bit) << P4_ESCR_EVENTMASK_SHIFT) 65d814f301SCyrill Gorcunov #define P4_ESCR_EMASK_BIT(class, name) class##__##name 66a072738eSCyrill Gorcunov 67a072738eSCyrill Gorcunov /* 68a072738eSCyrill Gorcunov * config field is 64bit width and consists of 69a072738eSCyrill Gorcunov * HT << 63 | ESCR << 32 | CCCR 70a072738eSCyrill Gorcunov * where HT is HyperThreading bit (since ESCR 71a072738eSCyrill Gorcunov * has it reserved we may use it for own purpose) 72a072738eSCyrill Gorcunov * 73a072738eSCyrill Gorcunov * note that this is NOT the addresses of respective 74a072738eSCyrill Gorcunov * ESCR and CCCR but rather an only packed value should 75a072738eSCyrill Gorcunov * be unpacked and written to a proper addresses 76a072738eSCyrill Gorcunov * 7739ef13a4SCyrill Gorcunov * the base idea is to pack as much info as possible 78a072738eSCyrill Gorcunov */ 79a072738eSCyrill Gorcunov #define p4_config_pack_escr(v) (((u64)(v)) << 32) 80a072738eSCyrill Gorcunov #define p4_config_pack_cccr(v) (((u64)(v)) & 0xffffffffULL) 81a072738eSCyrill Gorcunov #define p4_config_unpack_escr(v) (((u64)(v)) >> 32) 82d814f301SCyrill Gorcunov #define p4_config_unpack_cccr(v) (((u64)(v)) & 0xffffffffULL) 83a072738eSCyrill Gorcunov 84a072738eSCyrill Gorcunov #define p4_config_unpack_emask(v) \ 85a072738eSCyrill Gorcunov ({ \ 86a072738eSCyrill Gorcunov u32 t = p4_config_unpack_escr((v)); \ 87d814f301SCyrill Gorcunov t = t & P4_ESCR_EVENTMASK_MASK; \ 88d814f301SCyrill Gorcunov t = t >> P4_ESCR_EVENTMASK_SHIFT; \ 89a072738eSCyrill Gorcunov t; \ 90a072738eSCyrill Gorcunov }) 91a072738eSCyrill Gorcunov 92d814f301SCyrill Gorcunov #define p4_config_unpack_event(v) \ 93d814f301SCyrill Gorcunov ({ \ 94d814f301SCyrill Gorcunov u32 t = p4_config_unpack_escr((v)); \ 95d814f301SCyrill Gorcunov t = t & P4_ESCR_EVENT_MASK; \ 96d814f301SCyrill Gorcunov t = t >> P4_ESCR_EVENT_SHIFT; \ 97d814f301SCyrill Gorcunov t; \ 98d814f301SCyrill Gorcunov }) 99d814f301SCyrill Gorcunov 100a072738eSCyrill Gorcunov #define P4_CONFIG_HT_SHIFT 63 101a072738eSCyrill Gorcunov #define P4_CONFIG_HT (1ULL << P4_CONFIG_HT_SHIFT) 102a072738eSCyrill Gorcunov 103c9cf4a01SCyrill Gorcunov /* 104c9cf4a01SCyrill Gorcunov * The bits we allow to pass for RAW events 105c9cf4a01SCyrill Gorcunov */ 106c9cf4a01SCyrill Gorcunov #define P4_CONFIG_MASK_ESCR \ 107c9cf4a01SCyrill Gorcunov P4_ESCR_EVENT_MASK | \ 108c9cf4a01SCyrill Gorcunov P4_ESCR_EVENTMASK_MASK | \ 109c9cf4a01SCyrill Gorcunov P4_ESCR_TAG_MASK | \ 110c9cf4a01SCyrill Gorcunov P4_ESCR_TAG_ENABLE 111c9cf4a01SCyrill Gorcunov 112c9cf4a01SCyrill Gorcunov #define P4_CONFIG_MASK_CCCR \ 113c9cf4a01SCyrill Gorcunov P4_CCCR_EDGE | \ 114c9cf4a01SCyrill Gorcunov P4_CCCR_THRESHOLD_MASK | \ 115c9cf4a01SCyrill Gorcunov P4_CCCR_COMPLEMENT | \ 116c9cf4a01SCyrill Gorcunov P4_CCCR_COMPARE | \ 117c9cf4a01SCyrill Gorcunov P4_CCCR_THREAD_ANY | \ 118c9cf4a01SCyrill Gorcunov P4_CCCR_RESERVED 119c9cf4a01SCyrill Gorcunov 120c9cf4a01SCyrill Gorcunov /* some dangerous bits are reserved for kernel internals */ 121c9cf4a01SCyrill Gorcunov #define P4_CONFIG_MASK \ 122c9cf4a01SCyrill Gorcunov (p4_config_pack_escr(P4_CONFIG_MASK_ESCR)) | \ 123c9cf4a01SCyrill Gorcunov (p4_config_pack_cccr(P4_CONFIG_MASK_CCCR)) 124c9cf4a01SCyrill Gorcunov 125a072738eSCyrill Gorcunov static inline bool p4_is_event_cascaded(u64 config) 126a072738eSCyrill Gorcunov { 127a072738eSCyrill Gorcunov u32 cccr = p4_config_unpack_cccr(config); 128a072738eSCyrill Gorcunov return !!(cccr & P4_CCCR_CASCADE); 129a072738eSCyrill Gorcunov } 130a072738eSCyrill Gorcunov 131a072738eSCyrill Gorcunov static inline int p4_ht_config_thread(u64 config) 132a072738eSCyrill Gorcunov { 133a072738eSCyrill Gorcunov return !!(config & P4_CONFIG_HT); 134a072738eSCyrill Gorcunov } 135a072738eSCyrill Gorcunov 136a072738eSCyrill Gorcunov static inline u64 p4_set_ht_bit(u64 config) 137a072738eSCyrill Gorcunov { 138a072738eSCyrill Gorcunov return config | P4_CONFIG_HT; 139a072738eSCyrill Gorcunov } 140a072738eSCyrill Gorcunov 141a072738eSCyrill Gorcunov static inline u64 p4_clear_ht_bit(u64 config) 142a072738eSCyrill Gorcunov { 143a072738eSCyrill Gorcunov return config & ~P4_CONFIG_HT; 144a072738eSCyrill Gorcunov } 145a072738eSCyrill Gorcunov 146a072738eSCyrill Gorcunov static inline int p4_ht_active(void) 147a072738eSCyrill Gorcunov { 148a072738eSCyrill Gorcunov #ifdef CONFIG_SMP 149a072738eSCyrill Gorcunov return smp_num_siblings > 1; 150a072738eSCyrill Gorcunov #endif 151a072738eSCyrill Gorcunov return 0; 152a072738eSCyrill Gorcunov } 153a072738eSCyrill Gorcunov 154a072738eSCyrill Gorcunov static inline int p4_ht_thread(int cpu) 155a072738eSCyrill Gorcunov { 156a072738eSCyrill Gorcunov #ifdef CONFIG_SMP 157a072738eSCyrill Gorcunov if (smp_num_siblings == 2) 158a072738eSCyrill Gorcunov return cpu != cpumask_first(__get_cpu_var(cpu_sibling_map)); 159a072738eSCyrill Gorcunov #endif 160a072738eSCyrill Gorcunov return 0; 161a072738eSCyrill Gorcunov } 162a072738eSCyrill Gorcunov 163a072738eSCyrill Gorcunov static inline int p4_should_swap_ts(u64 config, int cpu) 164a072738eSCyrill Gorcunov { 165a072738eSCyrill Gorcunov return p4_ht_config_thread(config) ^ p4_ht_thread(cpu); 166a072738eSCyrill Gorcunov } 167a072738eSCyrill Gorcunov 168a072738eSCyrill Gorcunov static inline u32 p4_default_cccr_conf(int cpu) 169a072738eSCyrill Gorcunov { 170a072738eSCyrill Gorcunov /* 171a072738eSCyrill Gorcunov * Note that P4_CCCR_THREAD_ANY is "required" on 172a072738eSCyrill Gorcunov * non-HT machines (on HT machines we count TS events 173a072738eSCyrill Gorcunov * regardless the state of second logical processor 174a072738eSCyrill Gorcunov */ 175a072738eSCyrill Gorcunov u32 cccr = P4_CCCR_THREAD_ANY; 176a072738eSCyrill Gorcunov 177a072738eSCyrill Gorcunov if (!p4_ht_thread(cpu)) 178a072738eSCyrill Gorcunov cccr |= P4_CCCR_OVF_PMI_T0; 179a072738eSCyrill Gorcunov else 180a072738eSCyrill Gorcunov cccr |= P4_CCCR_OVF_PMI_T1; 181a072738eSCyrill Gorcunov 182a072738eSCyrill Gorcunov return cccr; 183a072738eSCyrill Gorcunov } 184a072738eSCyrill Gorcunov 185a072738eSCyrill Gorcunov static inline u32 p4_default_escr_conf(int cpu, int exclude_os, int exclude_usr) 186a072738eSCyrill Gorcunov { 187a072738eSCyrill Gorcunov u32 escr = 0; 188a072738eSCyrill Gorcunov 189a072738eSCyrill Gorcunov if (!p4_ht_thread(cpu)) { 190a072738eSCyrill Gorcunov if (!exclude_os) 191d814f301SCyrill Gorcunov escr |= P4_ESCR_T0_OS; 192a072738eSCyrill Gorcunov if (!exclude_usr) 193d814f301SCyrill Gorcunov escr |= P4_ESCR_T0_USR; 194a072738eSCyrill Gorcunov } else { 195a072738eSCyrill Gorcunov if (!exclude_os) 196d814f301SCyrill Gorcunov escr |= P4_ESCR_T1_OS; 197a072738eSCyrill Gorcunov if (!exclude_usr) 198d814f301SCyrill Gorcunov escr |= P4_ESCR_T1_USR; 199a072738eSCyrill Gorcunov } 200a072738eSCyrill Gorcunov 201a072738eSCyrill Gorcunov return escr; 202a072738eSCyrill Gorcunov } 203a072738eSCyrill Gorcunov 20439ef13a4SCyrill Gorcunov /* 20539ef13a4SCyrill Gorcunov * This are the events which should be used in "Event Select" 20639ef13a4SCyrill Gorcunov * field of ESCR register, they are like unique keys which allow 20739ef13a4SCyrill Gorcunov * the kernel to determinate which CCCR and COUNTER should be 20839ef13a4SCyrill Gorcunov * used to track an event 20939ef13a4SCyrill Gorcunov */ 210d814f301SCyrill Gorcunov enum P4_EVENTS { 211d814f301SCyrill Gorcunov P4_EVENT_TC_DELIVER_MODE, 212d814f301SCyrill Gorcunov P4_EVENT_BPU_FETCH_REQUEST, 213d814f301SCyrill Gorcunov P4_EVENT_ITLB_REFERENCE, 214d814f301SCyrill Gorcunov P4_EVENT_MEMORY_CANCEL, 215d814f301SCyrill Gorcunov P4_EVENT_MEMORY_COMPLETE, 216d814f301SCyrill Gorcunov P4_EVENT_LOAD_PORT_REPLAY, 217d814f301SCyrill Gorcunov P4_EVENT_STORE_PORT_REPLAY, 218d814f301SCyrill Gorcunov P4_EVENT_MOB_LOAD_REPLAY, 219d814f301SCyrill Gorcunov P4_EVENT_PAGE_WALK_TYPE, 220d814f301SCyrill Gorcunov P4_EVENT_BSQ_CACHE_REFERENCE, 221d814f301SCyrill Gorcunov P4_EVENT_IOQ_ALLOCATION, 222d814f301SCyrill Gorcunov P4_EVENT_IOQ_ACTIVE_ENTRIES, 223d814f301SCyrill Gorcunov P4_EVENT_FSB_DATA_ACTIVITY, 224d814f301SCyrill Gorcunov P4_EVENT_BSQ_ALLOCATION, 225d814f301SCyrill Gorcunov P4_EVENT_BSQ_ACTIVE_ENTRIES, 226d814f301SCyrill Gorcunov P4_EVENT_SSE_INPUT_ASSIST, 227d814f301SCyrill Gorcunov P4_EVENT_PACKED_SP_UOP, 228d814f301SCyrill Gorcunov P4_EVENT_PACKED_DP_UOP, 229d814f301SCyrill Gorcunov P4_EVENT_SCALAR_SP_UOP, 230d814f301SCyrill Gorcunov P4_EVENT_SCALAR_DP_UOP, 231d814f301SCyrill Gorcunov P4_EVENT_64BIT_MMX_UOP, 232d814f301SCyrill Gorcunov P4_EVENT_128BIT_MMX_UOP, 233d814f301SCyrill Gorcunov P4_EVENT_X87_FP_UOP, 234d814f301SCyrill Gorcunov P4_EVENT_TC_MISC, 235d814f301SCyrill Gorcunov P4_EVENT_GLOBAL_POWER_EVENTS, 236d814f301SCyrill Gorcunov P4_EVENT_TC_MS_XFER, 237d814f301SCyrill Gorcunov P4_EVENT_UOP_QUEUE_WRITES, 238d814f301SCyrill Gorcunov P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE, 239d814f301SCyrill Gorcunov P4_EVENT_RETIRED_BRANCH_TYPE, 240d814f301SCyrill Gorcunov P4_EVENT_RESOURCE_STALL, 241d814f301SCyrill Gorcunov P4_EVENT_WC_BUFFER, 242d814f301SCyrill Gorcunov P4_EVENT_B2B_CYCLES, 243d814f301SCyrill Gorcunov P4_EVENT_BNR, 244d814f301SCyrill Gorcunov P4_EVENT_SNOOP, 245d814f301SCyrill Gorcunov P4_EVENT_RESPONSE, 246d814f301SCyrill Gorcunov P4_EVENT_FRONT_END_EVENT, 247d814f301SCyrill Gorcunov P4_EVENT_EXECUTION_EVENT, 248d814f301SCyrill Gorcunov P4_EVENT_REPLAY_EVENT, 249d814f301SCyrill Gorcunov P4_EVENT_INSTR_RETIRED, 250d814f301SCyrill Gorcunov P4_EVENT_UOPS_RETIRED, 251d814f301SCyrill Gorcunov P4_EVENT_UOP_TYPE, 252d814f301SCyrill Gorcunov P4_EVENT_BRANCH_RETIRED, 253d814f301SCyrill Gorcunov P4_EVENT_MISPRED_BRANCH_RETIRED, 254d814f301SCyrill Gorcunov P4_EVENT_X87_ASSIST, 255d814f301SCyrill Gorcunov P4_EVENT_MACHINE_CLEAR, 256d814f301SCyrill Gorcunov P4_EVENT_INSTR_COMPLETED, 257d814f301SCyrill Gorcunov }; 258d814f301SCyrill Gorcunov 259d814f301SCyrill Gorcunov #define P4_OPCODE(event) event##_OPCODE 260d814f301SCyrill Gorcunov #define P4_OPCODE_ESEL(opcode) ((opcode & 0x00ff) >> 0) 261d814f301SCyrill Gorcunov #define P4_OPCODE_EVNT(opcode) ((opcode & 0xff00) >> 8) 262d814f301SCyrill Gorcunov #define P4_OPCODE_PACK(event, sel) (((event) << 8) | sel) 263d814f301SCyrill Gorcunov 264a072738eSCyrill Gorcunov /* 265a072738eSCyrill Gorcunov * Comments below the event represent ESCR restriction 266a072738eSCyrill Gorcunov * for this event and counter index per ESCR 267a072738eSCyrill Gorcunov * 268a072738eSCyrill Gorcunov * MSR_P4_IQ_ESCR0 and MSR_P4_IQ_ESCR1 are available only on early 269a072738eSCyrill Gorcunov * processor builds (family 0FH, models 01H-02H). These MSRs 270a072738eSCyrill Gorcunov * are not available on later versions, so that we don't use 271a072738eSCyrill Gorcunov * them completely 272a072738eSCyrill Gorcunov * 273a072738eSCyrill Gorcunov * Also note that CCCR1 do not have P4_CCCR_ENABLE bit properly 274a072738eSCyrill Gorcunov * working so that we should not use this CCCR and respective 275a072738eSCyrill Gorcunov * counter as result 276a072738eSCyrill Gorcunov */ 277d814f301SCyrill Gorcunov enum P4_EVENT_OPCODES { 278d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_TC_DELIVER_MODE) = P4_OPCODE_PACK(0x01, 0x01), 279a072738eSCyrill Gorcunov /* 280a072738eSCyrill Gorcunov * MSR_P4_TC_ESCR0: 4, 5 281a072738eSCyrill Gorcunov * MSR_P4_TC_ESCR1: 6, 7 282a072738eSCyrill Gorcunov */ 283a072738eSCyrill Gorcunov 284d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_BPU_FETCH_REQUEST) = P4_OPCODE_PACK(0x03, 0x00), 285a072738eSCyrill Gorcunov /* 286a072738eSCyrill Gorcunov * MSR_P4_BPU_ESCR0: 0, 1 287a072738eSCyrill Gorcunov * MSR_P4_BPU_ESCR1: 2, 3 288a072738eSCyrill Gorcunov */ 289a072738eSCyrill Gorcunov 290d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_ITLB_REFERENCE) = P4_OPCODE_PACK(0x18, 0x03), 291a072738eSCyrill Gorcunov /* 292a072738eSCyrill Gorcunov * MSR_P4_ITLB_ESCR0: 0, 1 293a072738eSCyrill Gorcunov * MSR_P4_ITLB_ESCR1: 2, 3 294a072738eSCyrill Gorcunov */ 295a072738eSCyrill Gorcunov 296d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_MEMORY_CANCEL) = P4_OPCODE_PACK(0x02, 0x05), 297a072738eSCyrill Gorcunov /* 298a072738eSCyrill Gorcunov * MSR_P4_DAC_ESCR0: 8, 9 299a072738eSCyrill Gorcunov * MSR_P4_DAC_ESCR1: 10, 11 300a072738eSCyrill Gorcunov */ 301a072738eSCyrill Gorcunov 302d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_MEMORY_COMPLETE) = P4_OPCODE_PACK(0x08, 0x02), 303a072738eSCyrill Gorcunov /* 304a072738eSCyrill Gorcunov * MSR_P4_SAAT_ESCR0: 8, 9 305a072738eSCyrill Gorcunov * MSR_P4_SAAT_ESCR1: 10, 11 306a072738eSCyrill Gorcunov */ 307a072738eSCyrill Gorcunov 308d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_LOAD_PORT_REPLAY) = P4_OPCODE_PACK(0x04, 0x02), 309a072738eSCyrill Gorcunov /* 310a072738eSCyrill Gorcunov * MSR_P4_SAAT_ESCR0: 8, 9 311a072738eSCyrill Gorcunov * MSR_P4_SAAT_ESCR1: 10, 11 312a072738eSCyrill Gorcunov */ 313a072738eSCyrill Gorcunov 314d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_STORE_PORT_REPLAY) = P4_OPCODE_PACK(0x05, 0x02), 315a072738eSCyrill Gorcunov /* 316a072738eSCyrill Gorcunov * MSR_P4_SAAT_ESCR0: 8, 9 317a072738eSCyrill Gorcunov * MSR_P4_SAAT_ESCR1: 10, 11 318a072738eSCyrill Gorcunov */ 319a072738eSCyrill Gorcunov 320d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_MOB_LOAD_REPLAY) = P4_OPCODE_PACK(0x03, 0x02), 321a072738eSCyrill Gorcunov /* 322a072738eSCyrill Gorcunov * MSR_P4_MOB_ESCR0: 0, 1 323a072738eSCyrill Gorcunov * MSR_P4_MOB_ESCR1: 2, 3 324a072738eSCyrill Gorcunov */ 325a072738eSCyrill Gorcunov 326d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_PAGE_WALK_TYPE) = P4_OPCODE_PACK(0x01, 0x04), 327a072738eSCyrill Gorcunov /* 328a072738eSCyrill Gorcunov * MSR_P4_PMH_ESCR0: 0, 1 329a072738eSCyrill Gorcunov * MSR_P4_PMH_ESCR1: 2, 3 330a072738eSCyrill Gorcunov */ 331a072738eSCyrill Gorcunov 332d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_BSQ_CACHE_REFERENCE) = P4_OPCODE_PACK(0x0c, 0x07), 333a072738eSCyrill Gorcunov /* 334a072738eSCyrill Gorcunov * MSR_P4_BSU_ESCR0: 0, 1 335a072738eSCyrill Gorcunov * MSR_P4_BSU_ESCR1: 2, 3 336a072738eSCyrill Gorcunov */ 337a072738eSCyrill Gorcunov 338d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_IOQ_ALLOCATION) = P4_OPCODE_PACK(0x03, 0x06), 339a072738eSCyrill Gorcunov /* 340a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR0: 0, 1 341a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR1: 2, 3 342a072738eSCyrill Gorcunov */ 343a072738eSCyrill Gorcunov 344d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_IOQ_ACTIVE_ENTRIES) = P4_OPCODE_PACK(0x1a, 0x06), 345a072738eSCyrill Gorcunov /* 346a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR1: 2, 3 347a072738eSCyrill Gorcunov */ 348a072738eSCyrill Gorcunov 349d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_FSB_DATA_ACTIVITY) = P4_OPCODE_PACK(0x17, 0x06), 350a072738eSCyrill Gorcunov /* 351a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR0: 0, 1 352a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR1: 2, 3 353a072738eSCyrill Gorcunov */ 354a072738eSCyrill Gorcunov 355d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_BSQ_ALLOCATION) = P4_OPCODE_PACK(0x05, 0x07), 356a072738eSCyrill Gorcunov /* 357a072738eSCyrill Gorcunov * MSR_P4_BSU_ESCR0: 0, 1 358a072738eSCyrill Gorcunov */ 359a072738eSCyrill Gorcunov 360d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_BSQ_ACTIVE_ENTRIES) = P4_OPCODE_PACK(0x06, 0x07), 361a072738eSCyrill Gorcunov /* 3628ea7f544SLin Ming * NOTE: no ESCR name in docs, it's guessed 363a072738eSCyrill Gorcunov * MSR_P4_BSU_ESCR1: 2, 3 364a072738eSCyrill Gorcunov */ 365a072738eSCyrill Gorcunov 366d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_SSE_INPUT_ASSIST) = P4_OPCODE_PACK(0x34, 0x01), 367a072738eSCyrill Gorcunov /* 368e4495262SCyrill Gorcunov * MSR_P4_FIRM_ESCR0: 8, 9 369e4495262SCyrill Gorcunov * MSR_P4_FIRM_ESCR1: 10, 11 370a072738eSCyrill Gorcunov */ 371a072738eSCyrill Gorcunov 372d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_PACKED_SP_UOP) = P4_OPCODE_PACK(0x08, 0x01), 373a072738eSCyrill Gorcunov /* 374a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR0: 8, 9 375a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR1: 10, 11 376a072738eSCyrill Gorcunov */ 377a072738eSCyrill Gorcunov 378d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_PACKED_DP_UOP) = P4_OPCODE_PACK(0x0c, 0x01), 379a072738eSCyrill Gorcunov /* 380a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR0: 8, 9 381a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR1: 10, 11 382a072738eSCyrill Gorcunov */ 383a072738eSCyrill Gorcunov 384d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_SCALAR_SP_UOP) = P4_OPCODE_PACK(0x0a, 0x01), 385a072738eSCyrill Gorcunov /* 386a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR0: 8, 9 387a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR1: 10, 11 388a072738eSCyrill Gorcunov */ 389a072738eSCyrill Gorcunov 390d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_SCALAR_DP_UOP) = P4_OPCODE_PACK(0x0e, 0x01), 391a072738eSCyrill Gorcunov /* 392a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR0: 8, 9 393a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR1: 10, 11 394a072738eSCyrill Gorcunov */ 395a072738eSCyrill Gorcunov 396d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_64BIT_MMX_UOP) = P4_OPCODE_PACK(0x02, 0x01), 397a072738eSCyrill Gorcunov /* 398a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR0: 8, 9 399a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR1: 10, 11 400a072738eSCyrill Gorcunov */ 401a072738eSCyrill Gorcunov 402d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_128BIT_MMX_UOP) = P4_OPCODE_PACK(0x1a, 0x01), 403a072738eSCyrill Gorcunov /* 404a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR0: 8, 9 405a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR1: 10, 11 406a072738eSCyrill Gorcunov */ 407a072738eSCyrill Gorcunov 408d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_X87_FP_UOP) = P4_OPCODE_PACK(0x04, 0x01), 409a072738eSCyrill Gorcunov /* 410a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR0: 8, 9 411a072738eSCyrill Gorcunov * MSR_P4_FIRM_ESCR1: 10, 11 412a072738eSCyrill Gorcunov */ 413a072738eSCyrill Gorcunov 414d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_TC_MISC) = P4_OPCODE_PACK(0x06, 0x01), 415a072738eSCyrill Gorcunov /* 416a072738eSCyrill Gorcunov * MSR_P4_TC_ESCR0: 4, 5 417a072738eSCyrill Gorcunov * MSR_P4_TC_ESCR1: 6, 7 418a072738eSCyrill Gorcunov */ 419a072738eSCyrill Gorcunov 420d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_GLOBAL_POWER_EVENTS) = P4_OPCODE_PACK(0x13, 0x06), 421a072738eSCyrill Gorcunov /* 422a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR0: 0, 1 423a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR1: 2, 3 424a072738eSCyrill Gorcunov */ 425a072738eSCyrill Gorcunov 426d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_TC_MS_XFER) = P4_OPCODE_PACK(0x05, 0x00), 427a072738eSCyrill Gorcunov /* 428a072738eSCyrill Gorcunov * MSR_P4_MS_ESCR0: 4, 5 429a072738eSCyrill Gorcunov * MSR_P4_MS_ESCR1: 6, 7 430a072738eSCyrill Gorcunov */ 431a072738eSCyrill Gorcunov 432d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_UOP_QUEUE_WRITES) = P4_OPCODE_PACK(0x09, 0x00), 433a072738eSCyrill Gorcunov /* 434a072738eSCyrill Gorcunov * MSR_P4_MS_ESCR0: 4, 5 435a072738eSCyrill Gorcunov * MSR_P4_MS_ESCR1: 6, 7 436a072738eSCyrill Gorcunov */ 437a072738eSCyrill Gorcunov 438d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE) = P4_OPCODE_PACK(0x05, 0x02), 439a072738eSCyrill Gorcunov /* 440a072738eSCyrill Gorcunov * MSR_P4_TBPU_ESCR0: 4, 5 4419c8c6badSCyrill Gorcunov * MSR_P4_TBPU_ESCR1: 6, 7 442a072738eSCyrill Gorcunov */ 443a072738eSCyrill Gorcunov 444d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_RETIRED_BRANCH_TYPE) = P4_OPCODE_PACK(0x04, 0x02), 445a072738eSCyrill Gorcunov /* 446a072738eSCyrill Gorcunov * MSR_P4_TBPU_ESCR0: 4, 5 4479c8c6badSCyrill Gorcunov * MSR_P4_TBPU_ESCR1: 6, 7 448a072738eSCyrill Gorcunov */ 449a072738eSCyrill Gorcunov 450d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_RESOURCE_STALL) = P4_OPCODE_PACK(0x01, 0x01), 451a072738eSCyrill Gorcunov /* 452a072738eSCyrill Gorcunov * MSR_P4_ALF_ESCR0: 12, 13, 16 453a072738eSCyrill Gorcunov * MSR_P4_ALF_ESCR1: 14, 15, 17 454a072738eSCyrill Gorcunov */ 455a072738eSCyrill Gorcunov 456d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_WC_BUFFER) = P4_OPCODE_PACK(0x05, 0x05), 457a072738eSCyrill Gorcunov /* 458a072738eSCyrill Gorcunov * MSR_P4_DAC_ESCR0: 8, 9 459a072738eSCyrill Gorcunov * MSR_P4_DAC_ESCR1: 10, 11 460a072738eSCyrill Gorcunov */ 461a072738eSCyrill Gorcunov 462d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_B2B_CYCLES) = P4_OPCODE_PACK(0x16, 0x03), 463a072738eSCyrill Gorcunov /* 464a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR0: 0, 1 465a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR1: 2, 3 466a072738eSCyrill Gorcunov */ 467a072738eSCyrill Gorcunov 468d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_BNR) = P4_OPCODE_PACK(0x08, 0x03), 469a072738eSCyrill Gorcunov /* 470a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR0: 0, 1 471a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR1: 2, 3 472a072738eSCyrill Gorcunov */ 473a072738eSCyrill Gorcunov 474d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_SNOOP) = P4_OPCODE_PACK(0x06, 0x03), 475a072738eSCyrill Gorcunov /* 476a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR0: 0, 1 477a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR1: 2, 3 478a072738eSCyrill Gorcunov */ 479a072738eSCyrill Gorcunov 480d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_RESPONSE) = P4_OPCODE_PACK(0x04, 0x03), 481a072738eSCyrill Gorcunov /* 482a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR0: 0, 1 483a072738eSCyrill Gorcunov * MSR_P4_FSB_ESCR1: 2, 3 484a072738eSCyrill Gorcunov */ 485a072738eSCyrill Gorcunov 486d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_FRONT_END_EVENT) = P4_OPCODE_PACK(0x08, 0x05), 487a072738eSCyrill Gorcunov /* 488a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR2: 12, 13, 16 489a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR3: 14, 15, 17 490a072738eSCyrill Gorcunov */ 491a072738eSCyrill Gorcunov 492d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_EXECUTION_EVENT) = P4_OPCODE_PACK(0x0c, 0x05), 493a072738eSCyrill Gorcunov /* 494a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR2: 12, 13, 16 495a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR3: 14, 15, 17 496a072738eSCyrill Gorcunov */ 497a072738eSCyrill Gorcunov 498d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_REPLAY_EVENT) = P4_OPCODE_PACK(0x09, 0x05), 499a072738eSCyrill Gorcunov /* 500a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR2: 12, 13, 16 501a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR3: 14, 15, 17 502a072738eSCyrill Gorcunov */ 503a072738eSCyrill Gorcunov 504d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_INSTR_RETIRED) = P4_OPCODE_PACK(0x02, 0x04), 505a072738eSCyrill Gorcunov /* 506e4495262SCyrill Gorcunov * MSR_P4_CRU_ESCR0: 12, 13, 16 507e4495262SCyrill Gorcunov * MSR_P4_CRU_ESCR1: 14, 15, 17 508a072738eSCyrill Gorcunov */ 509a072738eSCyrill Gorcunov 510d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_UOPS_RETIRED) = P4_OPCODE_PACK(0x01, 0x04), 511a072738eSCyrill Gorcunov /* 5128ea7f544SLin Ming * MSR_P4_CRU_ESCR0: 12, 13, 16 5138ea7f544SLin Ming * MSR_P4_CRU_ESCR1: 14, 15, 17 514a072738eSCyrill Gorcunov */ 515a072738eSCyrill Gorcunov 516d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_UOP_TYPE) = P4_OPCODE_PACK(0x02, 0x02), 517a072738eSCyrill Gorcunov /* 518a072738eSCyrill Gorcunov * MSR_P4_RAT_ESCR0: 12, 13, 16 519a072738eSCyrill Gorcunov * MSR_P4_RAT_ESCR1: 14, 15, 17 520a072738eSCyrill Gorcunov */ 521a072738eSCyrill Gorcunov 522d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_BRANCH_RETIRED) = P4_OPCODE_PACK(0x06, 0x05), 523a072738eSCyrill Gorcunov /* 524a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR2: 12, 13, 16 525a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR3: 14, 15, 17 526a072738eSCyrill Gorcunov */ 527a072738eSCyrill Gorcunov 528d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_MISPRED_BRANCH_RETIRED) = P4_OPCODE_PACK(0x03, 0x04), 529a072738eSCyrill Gorcunov /* 530a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR0: 12, 13, 16 531a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR1: 14, 15, 17 532a072738eSCyrill Gorcunov */ 533a072738eSCyrill Gorcunov 534d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_X87_ASSIST) = P4_OPCODE_PACK(0x03, 0x05), 535a072738eSCyrill Gorcunov /* 536a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR2: 12, 13, 16 537a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR3: 14, 15, 17 538a072738eSCyrill Gorcunov */ 539a072738eSCyrill Gorcunov 540d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_MACHINE_CLEAR) = P4_OPCODE_PACK(0x02, 0x05), 541a072738eSCyrill Gorcunov /* 542a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR2: 12, 13, 16 543a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR3: 14, 15, 17 544a072738eSCyrill Gorcunov */ 545a072738eSCyrill Gorcunov 546d814f301SCyrill Gorcunov P4_OPCODE(P4_EVENT_INSTR_COMPLETED) = P4_OPCODE_PACK(0x07, 0x04), 547a072738eSCyrill Gorcunov /* 548a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR0: 12, 13, 16 549a072738eSCyrill Gorcunov * MSR_P4_CRU_ESCR1: 14, 15, 17 550a072738eSCyrill Gorcunov */ 551a072738eSCyrill Gorcunov }; 552a072738eSCyrill Gorcunov 553d814f301SCyrill Gorcunov /* 554d814f301SCyrill Gorcunov * a caller should use P4_ESCR_EMASK_NAME helper to 555d814f301SCyrill Gorcunov * pick the EventMask needed, for example 556d814f301SCyrill Gorcunov * 55739ef13a4SCyrill Gorcunov * P4_ESCR_EMASK_BIT(P4_EVENT_TC_DELIVER_MODE, DD) 558d814f301SCyrill Gorcunov */ 559d814f301SCyrill Gorcunov enum P4_ESCR_EMASKS { 560d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, DD, 0), 561d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, DB, 1), 562d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, DI, 2), 563d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, BD, 3), 564d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, BB, 4), 565d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, BI, 5), 566d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, ID, 6), 567d814f301SCyrill Gorcunov 568d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BPU_FETCH_REQUEST, TCMISS, 0), 569d814f301SCyrill Gorcunov 570d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_ITLB_REFERENCE, HIT, 0), 571d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_ITLB_REFERENCE, MISS, 1), 572d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_ITLB_REFERENCE, HIT_UK, 2), 573d814f301SCyrill Gorcunov 574d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_MEMORY_CANCEL, ST_RB_FULL, 2), 575d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_MEMORY_CANCEL, 64K_CONF, 3), 576d814f301SCyrill Gorcunov 577d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_MEMORY_COMPLETE, LSC, 0), 578d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_MEMORY_COMPLETE, SSC, 1), 579d814f301SCyrill Gorcunov 580d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_LOAD_PORT_REPLAY, SPLIT_LD, 1), 581d814f301SCyrill Gorcunov 582d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_STORE_PORT_REPLAY, SPLIT_ST, 1), 583d814f301SCyrill Gorcunov 584d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_MOB_LOAD_REPLAY, NO_STA, 1), 585d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_MOB_LOAD_REPLAY, NO_STD, 3), 586d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_MOB_LOAD_REPLAY, PARTIAL_DATA, 4), 587d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_MOB_LOAD_REPLAY, UNALGN_ADDR, 5), 588d814f301SCyrill Gorcunov 589d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_PAGE_WALK_TYPE, DTMISS, 0), 590d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_PAGE_WALK_TYPE, ITMISS, 1), 591d814f301SCyrill Gorcunov 592d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_HITS, 0), 593d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_HITE, 1), 594d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_HITM, 2), 595d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_HITS, 3), 596d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_HITE, 4), 597d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_HITM, 5), 598d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_MISS, 8), 599d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_MISS, 9), 600d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, WR_2ndL_MISS, 10), 601d814f301SCyrill Gorcunov 602d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, DEFAULT, 0), 603d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, ALL_READ, 5), 604d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, ALL_WRITE, 6), 605d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, MEM_UC, 7), 606d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, MEM_WC, 8), 607d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, MEM_WT, 9), 608d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, MEM_WP, 10), 609d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, MEM_WB, 11), 610d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, OWN, 13), 611d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, OTHER, 14), 612d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, PREFETCH, 15), 613d814f301SCyrill Gorcunov 614d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, DEFAULT, 0), 615d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, ALL_READ, 5), 616d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, ALL_WRITE, 6), 617d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, MEM_UC, 7), 618d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, MEM_WC, 8), 619d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, MEM_WT, 9), 620d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, MEM_WP, 10), 621d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, MEM_WB, 11), 622d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, OWN, 13), 623d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, OTHER, 14), 624d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, PREFETCH, 15), 625d814f301SCyrill Gorcunov 626d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_FSB_DATA_ACTIVITY, DRDY_DRV, 0), 627d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_FSB_DATA_ACTIVITY, DRDY_OWN, 1), 628d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_FSB_DATA_ACTIVITY, DRDY_OTHER, 2), 629d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_FSB_DATA_ACTIVITY, DBSY_DRV, 3), 630d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_FSB_DATA_ACTIVITY, DBSY_OWN, 4), 631d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_FSB_DATA_ACTIVITY, DBSY_OTHER, 5), 632d814f301SCyrill Gorcunov 633d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_TYPE0, 0), 634d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_TYPE1, 1), 635d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_LEN0, 2), 636d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_LEN1, 3), 637d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_IO_TYPE, 5), 638d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_LOCK_TYPE, 6), 639d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_CACHE_TYPE, 7), 640d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_SPLIT_TYPE, 8), 641d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_DEM_TYPE, 9), 642d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_ORD_TYPE, 10), 643d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, MEM_TYPE0, 11), 644d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, MEM_TYPE1, 12), 645d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, MEM_TYPE2, 13), 646d814f301SCyrill Gorcunov 647d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_TYPE0, 0), 648d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_TYPE1, 1), 649d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_LEN0, 2), 650d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_LEN1, 3), 651d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_IO_TYPE, 5), 652d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_LOCK_TYPE, 6), 653d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_CACHE_TYPE, 7), 654d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_SPLIT_TYPE, 8), 655d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_DEM_TYPE, 9), 656d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_ORD_TYPE, 10), 657d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, MEM_TYPE0, 11), 658d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, MEM_TYPE1, 12), 659d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, MEM_TYPE2, 13), 660d814f301SCyrill Gorcunov 661d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_SSE_INPUT_ASSIST, ALL, 15), 662d814f301SCyrill Gorcunov 663d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_PACKED_SP_UOP, ALL, 15), 664d814f301SCyrill Gorcunov 665d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_PACKED_DP_UOP, ALL, 15), 666d814f301SCyrill Gorcunov 667d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_SCALAR_SP_UOP, ALL, 15), 668d814f301SCyrill Gorcunov 669d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_SCALAR_DP_UOP, ALL, 15), 670d814f301SCyrill Gorcunov 671d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_64BIT_MMX_UOP, ALL, 15), 672d814f301SCyrill Gorcunov 673d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_128BIT_MMX_UOP, ALL, 15), 674d814f301SCyrill Gorcunov 675d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_X87_FP_UOP, ALL, 15), 676d814f301SCyrill Gorcunov 677d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_TC_MISC, FLUSH, 4), 678d814f301SCyrill Gorcunov 679d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_GLOBAL_POWER_EVENTS, RUNNING, 0), 680d814f301SCyrill Gorcunov 681d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_TC_MS_XFER, CISC, 0), 682d814f301SCyrill Gorcunov 683d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_UOP_QUEUE_WRITES, FROM_TC_BUILD, 0), 684d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_UOP_QUEUE_WRITES, FROM_TC_DELIVER, 1), 685d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_UOP_QUEUE_WRITES, FROM_ROM, 2), 686d814f301SCyrill Gorcunov 687d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE, CONDITIONAL, 1), 688d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE, CALL, 2), 689d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE, RETURN, 3), 690d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE, INDIRECT, 4), 691d814f301SCyrill Gorcunov 692d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_BRANCH_TYPE, CONDITIONAL, 1), 693d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_BRANCH_TYPE, CALL, 2), 694d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_BRANCH_TYPE, RETURN, 3), 695d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_BRANCH_TYPE, INDIRECT, 4), 696d814f301SCyrill Gorcunov 697d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_RESOURCE_STALL, SBFULL, 5), 698d814f301SCyrill Gorcunov 699d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_WC_BUFFER, WCB_EVICTS, 0), 700d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_WC_BUFFER, WCB_FULL_EVICTS, 1), 701d814f301SCyrill Gorcunov 702d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_FRONT_END_EVENT, NBOGUS, 0), 703d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_FRONT_END_EVENT, BOGUS, 1), 704d814f301SCyrill Gorcunov 705d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, NBOGUS0, 0), 706d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, NBOGUS1, 1), 707d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, NBOGUS2, 2), 708d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, NBOGUS3, 3), 709d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, BOGUS0, 4), 710d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, BOGUS1, 5), 711d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, BOGUS2, 6), 712d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, BOGUS3, 7), 713d814f301SCyrill Gorcunov 714d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_REPLAY_EVENT, NBOGUS, 0), 715d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_REPLAY_EVENT, BOGUS, 1), 716d814f301SCyrill Gorcunov 717d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_INSTR_RETIRED, NBOGUSNTAG, 0), 718d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_INSTR_RETIRED, NBOGUSTAG, 1), 719d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_INSTR_RETIRED, BOGUSNTAG, 2), 720d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_INSTR_RETIRED, BOGUSTAG, 3), 721d814f301SCyrill Gorcunov 722d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_UOPS_RETIRED, NBOGUS, 0), 723d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_UOPS_RETIRED, BOGUS, 1), 724d814f301SCyrill Gorcunov 725d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_UOP_TYPE, TAGLOADS, 1), 726d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_UOP_TYPE, TAGSTORES, 2), 727d814f301SCyrill Gorcunov 728d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BRANCH_RETIRED, MMNP, 0), 729d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BRANCH_RETIRED, MMNM, 1), 730d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BRANCH_RETIRED, MMTP, 2), 731d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_BRANCH_RETIRED, MMTM, 3), 732d814f301SCyrill Gorcunov 733d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_MISPRED_BRANCH_RETIRED, NBOGUS, 0), 734d814f301SCyrill Gorcunov 735d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_X87_ASSIST, FPSU, 0), 736d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_X87_ASSIST, FPSO, 1), 737d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_X87_ASSIST, POAO, 2), 738d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_X87_ASSIST, POAU, 3), 739d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_X87_ASSIST, PREA, 4), 740d814f301SCyrill Gorcunov 741d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_MACHINE_CLEAR, CLEAR, 0), 742d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_MACHINE_CLEAR, MOCLEAR, 1), 743d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_MACHINE_CLEAR, SMCLEAR, 2), 744d814f301SCyrill Gorcunov 745d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_INSTR_COMPLETED, NBOGUS, 0), 746d814f301SCyrill Gorcunov P4_GEN_ESCR_EMASK(P4_EVENT_INSTR_COMPLETED, BOGUS, 1), 747d814f301SCyrill Gorcunov }; 748d814f301SCyrill Gorcunov 74939ef13a4SCyrill Gorcunov /* 75039ef13a4SCyrill Gorcunov * Note we have UOP and PEBS bits reserved for now 75139ef13a4SCyrill Gorcunov * just in case if we will need them once 75239ef13a4SCyrill Gorcunov */ 75339ef13a4SCyrill Gorcunov #define P4_PEBS_CONFIG_ENABLE (1 << 7) 75439ef13a4SCyrill Gorcunov #define P4_PEBS_CONFIG_UOP_TAG (1 << 8) 75539ef13a4SCyrill Gorcunov #define P4_PEBS_CONFIG_METRIC_MASK 0x3f 75639ef13a4SCyrill Gorcunov #define P4_PEBS_CONFIG_MASK 0xff 75739ef13a4SCyrill Gorcunov 75839ef13a4SCyrill Gorcunov /* 75939ef13a4SCyrill Gorcunov * mem: Only counters MSR_IQ_COUNTER4 (16) and 76039ef13a4SCyrill Gorcunov * MSR_IQ_COUNTER5 (17) are allowed for PEBS sampling 76139ef13a4SCyrill Gorcunov */ 762d814f301SCyrill Gorcunov #define P4_PEBS_ENABLE 0x02000000U 76339ef13a4SCyrill Gorcunov #define P4_PEBS_ENABLE_UOP_TAG 0x01000000U 764d814f301SCyrill Gorcunov 76539ef13a4SCyrill Gorcunov #define p4_config_unpack_metric(v) (((u64)(v)) & P4_PEBS_CONFIG_METRIC_MASK) 76639ef13a4SCyrill Gorcunov #define p4_config_unpack_pebs(v) (((u64)(v)) & P4_PEBS_CONFIG_MASK) 767d814f301SCyrill Gorcunov 76839ef13a4SCyrill Gorcunov #define p4_config_pebs_has(v, mask) (p4_config_unpack_pebs(v) & (mask)) 769d814f301SCyrill Gorcunov 77039ef13a4SCyrill Gorcunov enum P4_PEBS_METRIC { 77139ef13a4SCyrill Gorcunov P4_PEBS_METRIC__none, 772d814f301SCyrill Gorcunov 77339ef13a4SCyrill Gorcunov P4_PEBS_METRIC__1stl_cache_load_miss_retired, 77439ef13a4SCyrill Gorcunov P4_PEBS_METRIC__2ndl_cache_load_miss_retired, 77539ef13a4SCyrill Gorcunov P4_PEBS_METRIC__dtlb_load_miss_retired, 77639ef13a4SCyrill Gorcunov P4_PEBS_METRIC__dtlb_store_miss_retired, 77739ef13a4SCyrill Gorcunov P4_PEBS_METRIC__dtlb_all_miss_retired, 77839ef13a4SCyrill Gorcunov P4_PEBS_METRIC__tagged_mispred_branch, 77939ef13a4SCyrill Gorcunov P4_PEBS_METRIC__mob_load_replay_retired, 78039ef13a4SCyrill Gorcunov P4_PEBS_METRIC__split_load_retired, 78139ef13a4SCyrill Gorcunov P4_PEBS_METRIC__split_store_retired, 782d814f301SCyrill Gorcunov 78339ef13a4SCyrill Gorcunov P4_PEBS_METRIC__max 784cb7d6b50SLin Ming }; 785cb7d6b50SLin Ming 786af86da53SCyrill Gorcunov /* 787af86da53SCyrill Gorcunov * Notes on internal configuration of ESCR+CCCR tuples 788af86da53SCyrill Gorcunov * 789af86da53SCyrill Gorcunov * Since P4 has quite the different architecture of 790af86da53SCyrill Gorcunov * performance registers in compare with "architectural" 791af86da53SCyrill Gorcunov * once and we have on 64 bits to keep configuration 792af86da53SCyrill Gorcunov * of performance event, the following trick is used. 793af86da53SCyrill Gorcunov * 794af86da53SCyrill Gorcunov * 1) Since both ESCR and CCCR registers have only low 795af86da53SCyrill Gorcunov * 32 bits valuable, we pack them into a single 64 bit 796af86da53SCyrill Gorcunov * configuration. Low 32 bits of such config correspond 797af86da53SCyrill Gorcunov * to low 32 bits of CCCR register and high 32 bits 798af86da53SCyrill Gorcunov * correspond to low 32 bits of ESCR register. 799af86da53SCyrill Gorcunov * 800af86da53SCyrill Gorcunov * 2) The meaning of every bit of such config field can 801af86da53SCyrill Gorcunov * be found in Intel SDM but it should be noted that 802af86da53SCyrill Gorcunov * we "borrow" some reserved bits for own usage and 803af86da53SCyrill Gorcunov * clean them or set to a proper value when we do 804af86da53SCyrill Gorcunov * a real write to hardware registers. 805af86da53SCyrill Gorcunov * 806af86da53SCyrill Gorcunov * 3) The format of bits of config is the following 807af86da53SCyrill Gorcunov * and should be either 0 or set to some predefined 808af86da53SCyrill Gorcunov * values: 809af86da53SCyrill Gorcunov * 810af86da53SCyrill Gorcunov * Low 32 bits 811af86da53SCyrill Gorcunov * ----------- 812af86da53SCyrill Gorcunov * 0-6: P4_PEBS_METRIC enum 813af86da53SCyrill Gorcunov * 7-11: reserved 814af86da53SCyrill Gorcunov * 12: reserved (Enable) 815af86da53SCyrill Gorcunov * 13-15: reserved (ESCR select) 816af86da53SCyrill Gorcunov * 16-17: Active Thread 817af86da53SCyrill Gorcunov * 18: Compare 818af86da53SCyrill Gorcunov * 19: Complement 819af86da53SCyrill Gorcunov * 20-23: Threshold 820af86da53SCyrill Gorcunov * 24: Edge 821af86da53SCyrill Gorcunov * 25: reserved (FORCE_OVF) 822af86da53SCyrill Gorcunov * 26: reserved (OVF_PMI_T0) 823af86da53SCyrill Gorcunov * 27: reserved (OVF_PMI_T1) 824af86da53SCyrill Gorcunov * 28-29: reserved 825af86da53SCyrill Gorcunov * 30: reserved (Cascade) 826af86da53SCyrill Gorcunov * 31: reserved (OVF) 827af86da53SCyrill Gorcunov * 828af86da53SCyrill Gorcunov * High 32 bits 829af86da53SCyrill Gorcunov * ------------ 830af86da53SCyrill Gorcunov * 0: reserved (T1_USR) 831af86da53SCyrill Gorcunov * 1: reserved (T1_OS) 832af86da53SCyrill Gorcunov * 2: reserved (T0_USR) 833af86da53SCyrill Gorcunov * 3: reserved (T0_OS) 834af86da53SCyrill Gorcunov * 4: Tag Enable 835af86da53SCyrill Gorcunov * 5-8: Tag Value 836af86da53SCyrill Gorcunov * 9-24: Event Mask (may use P4_ESCR_EMASK_BIT helper) 837af86da53SCyrill Gorcunov * 25-30: enum P4_EVENTS 838af86da53SCyrill Gorcunov * 31: reserved (HT thread) 839af86da53SCyrill Gorcunov */ 840af86da53SCyrill Gorcunov 841a072738eSCyrill Gorcunov #endif /* PERF_EVENT_P4_H */ 84239ef13a4SCyrill Gorcunov 843