1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _ASM_X86_PERF_EVENT_H 3 #define _ASM_X86_PERF_EVENT_H 4 5 #include <linux/static_call.h> 6 7 /* 8 * Performance event hw details: 9 */ 10 11 #define INTEL_PMC_MAX_GENERIC 32 12 #define INTEL_PMC_MAX_FIXED 16 13 #define INTEL_PMC_IDX_FIXED 32 14 15 #define X86_PMC_IDX_MAX 64 16 17 #define MSR_ARCH_PERFMON_PERFCTR0 0xc1 18 #define MSR_ARCH_PERFMON_PERFCTR1 0xc2 19 20 #define MSR_ARCH_PERFMON_EVENTSEL0 0x186 21 #define MSR_ARCH_PERFMON_EVENTSEL1 0x187 22 23 #define ARCH_PERFMON_EVENTSEL_EVENT 0x000000FFULL 24 #define ARCH_PERFMON_EVENTSEL_UMASK 0x0000FF00ULL 25 #define ARCH_PERFMON_EVENTSEL_USR (1ULL << 16) 26 #define ARCH_PERFMON_EVENTSEL_OS (1ULL << 17) 27 #define ARCH_PERFMON_EVENTSEL_EDGE (1ULL << 18) 28 #define ARCH_PERFMON_EVENTSEL_PIN_CONTROL (1ULL << 19) 29 #define ARCH_PERFMON_EVENTSEL_INT (1ULL << 20) 30 #define ARCH_PERFMON_EVENTSEL_ANY (1ULL << 21) 31 #define ARCH_PERFMON_EVENTSEL_ENABLE (1ULL << 22) 32 #define ARCH_PERFMON_EVENTSEL_INV (1ULL << 23) 33 #define ARCH_PERFMON_EVENTSEL_CMASK 0xFF000000ULL 34 #define ARCH_PERFMON_EVENTSEL_BR_CNTR (1ULL << 35) 35 #define ARCH_PERFMON_EVENTSEL_EQ (1ULL << 36) 36 #define ARCH_PERFMON_EVENTSEL_RDPMC_USER_DISABLE (1ULL << 37) 37 #define ARCH_PERFMON_EVENTSEL_UMASK2 (0xFFULL << 40) 38 39 #define INTEL_FIXED_BITS_STRIDE 4 40 #define INTEL_FIXED_0_KERNEL (1ULL << 0) 41 #define INTEL_FIXED_0_USER (1ULL << 1) 42 #define INTEL_FIXED_0_ANYTHREAD (1ULL << 2) 43 #define INTEL_FIXED_0_ENABLE_PMI (1ULL << 3) 44 #define INTEL_FIXED_0_RDPMC_USER_DISABLE (1ULL << 33) 45 #define INTEL_FIXED_3_METRICS_CLEAR (1ULL << 2) 46 47 #define HSW_IN_TX (1ULL << 32) 48 #define HSW_IN_TX_CHECKPOINTED (1ULL << 33) 49 #define ICL_EVENTSEL_ADAPTIVE (1ULL << 34) 50 #define ICL_FIXED_0_ADAPTIVE (1ULL << 32) 51 52 #define INTEL_FIXED_BITS_MASK \ 53 (INTEL_FIXED_0_KERNEL | INTEL_FIXED_0_USER | \ 54 INTEL_FIXED_0_ANYTHREAD | INTEL_FIXED_0_ENABLE_PMI | \ 55 ICL_FIXED_0_ADAPTIVE | INTEL_FIXED_0_RDPMC_USER_DISABLE) 56 57 #define intel_fixed_bits_by_idx(_idx, _bits) \ 58 ((_bits) << ((_idx) * INTEL_FIXED_BITS_STRIDE)) 59 60 #define AMD64_EVENTSEL_INT_CORE_ENABLE (1ULL << 36) 61 #define AMD64_EVENTSEL_GUESTONLY (1ULL << 40) 62 #define AMD64_EVENTSEL_HOSTONLY (1ULL << 41) 63 #define AMD64_EVENTSEL_HOST_GUEST_MASK \ 64 (AMD64_EVENTSEL_HOSTONLY | AMD64_EVENTSEL_GUESTONLY) 65 66 #define AMD64_EVENTSEL_INT_CORE_SEL_SHIFT 37 67 #define AMD64_EVENTSEL_INT_CORE_SEL_MASK \ 68 (0xFULL << AMD64_EVENTSEL_INT_CORE_SEL_SHIFT) 69 70 #define AMD64_EVENTSEL_EVENT \ 71 (ARCH_PERFMON_EVENTSEL_EVENT | (0x0FULL << 32)) 72 #define INTEL_ARCH_EVENT_MASK \ 73 (ARCH_PERFMON_EVENTSEL_UMASK | ARCH_PERFMON_EVENTSEL_EVENT) 74 75 #define AMD64_L3_SLICE_SHIFT 48 76 #define AMD64_L3_SLICE_MASK \ 77 (0xFULL << AMD64_L3_SLICE_SHIFT) 78 #define AMD64_L3_SLICEID_MASK \ 79 (0x7ULL << AMD64_L3_SLICE_SHIFT) 80 81 #define AMD64_L3_THREAD_SHIFT 56 82 #define AMD64_L3_THREAD_MASK \ 83 (0xFFULL << AMD64_L3_THREAD_SHIFT) 84 #define AMD64_L3_F19H_THREAD_MASK \ 85 (0x3ULL << AMD64_L3_THREAD_SHIFT) 86 87 #define AMD64_L3_EN_ALL_CORES BIT_ULL(47) 88 #define AMD64_L3_EN_ALL_SLICES BIT_ULL(46) 89 90 #define AMD64_L3_COREID_SHIFT 42 91 #define AMD64_L3_COREID_MASK \ 92 (0x7ULL << AMD64_L3_COREID_SHIFT) 93 94 #define X86_RAW_EVENT_MASK \ 95 (ARCH_PERFMON_EVENTSEL_EVENT | \ 96 ARCH_PERFMON_EVENTSEL_UMASK | \ 97 ARCH_PERFMON_EVENTSEL_EDGE | \ 98 ARCH_PERFMON_EVENTSEL_INV | \ 99 ARCH_PERFMON_EVENTSEL_CMASK) 100 #define X86_ALL_EVENT_FLAGS \ 101 (ARCH_PERFMON_EVENTSEL_EDGE | \ 102 ARCH_PERFMON_EVENTSEL_INV | \ 103 ARCH_PERFMON_EVENTSEL_CMASK | \ 104 ARCH_PERFMON_EVENTSEL_ANY | \ 105 ARCH_PERFMON_EVENTSEL_PIN_CONTROL | \ 106 HSW_IN_TX | \ 107 HSW_IN_TX_CHECKPOINTED) 108 #define AMD64_RAW_EVENT_MASK \ 109 (X86_RAW_EVENT_MASK | \ 110 AMD64_EVENTSEL_EVENT) 111 #define AMD64_RAW_EVENT_MASK_NB \ 112 (AMD64_EVENTSEL_EVENT | \ 113 ARCH_PERFMON_EVENTSEL_UMASK) 114 115 #define AMD64_PERFMON_V2_EVENTSEL_EVENT_NB \ 116 (AMD64_EVENTSEL_EVENT | \ 117 GENMASK_ULL(37, 36)) 118 119 #define AMD64_PERFMON_V2_EVENTSEL_UMASK_NB \ 120 (ARCH_PERFMON_EVENTSEL_UMASK | \ 121 GENMASK_ULL(27, 24)) 122 123 #define AMD64_PERFMON_V2_RAW_EVENT_MASK_NB \ 124 (AMD64_PERFMON_V2_EVENTSEL_EVENT_NB | \ 125 AMD64_PERFMON_V2_EVENTSEL_UMASK_NB) 126 127 #define AMD64_PERFMON_V2_ENABLE_UMC BIT_ULL(31) 128 #define AMD64_PERFMON_V2_EVENTSEL_EVENT_UMC GENMASK_ULL(7, 0) 129 #define AMD64_PERFMON_V2_EVENTSEL_RDWRMASK_UMC GENMASK_ULL(9, 8) 130 #define AMD64_PERFMON_V2_RAW_EVENT_MASK_UMC \ 131 (AMD64_PERFMON_V2_EVENTSEL_EVENT_UMC | \ 132 AMD64_PERFMON_V2_EVENTSEL_RDWRMASK_UMC) 133 134 #define AMD64_NUM_COUNTERS 4 135 #define AMD64_NUM_COUNTERS_CORE 6 136 #define AMD64_NUM_COUNTERS_NB 4 137 138 #define ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL 0x3c 139 #define ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK (0x00 << 8) 140 #define ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX 0 141 #define ARCH_PERFMON_UNHALTED_CORE_CYCLES_PRESENT \ 142 (1 << (ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX)) 143 144 #define ARCH_PERFMON_BRANCH_MISSES_RETIRED 6 145 #define ARCH_PERFMON_EVENTS_COUNT 7 146 147 #define PEBS_DATACFG_MEMINFO BIT_ULL(0) 148 #define PEBS_DATACFG_GP BIT_ULL(1) 149 #define PEBS_DATACFG_XMMS BIT_ULL(2) 150 #define PEBS_DATACFG_LBRS BIT_ULL(3) 151 #define PEBS_DATACFG_CNTR BIT_ULL(4) 152 #define PEBS_DATACFG_METRICS BIT_ULL(5) 153 #define PEBS_DATACFG_LBR_SHIFT 24 154 #define PEBS_DATACFG_CNTR_SHIFT 32 155 #define PEBS_DATACFG_CNTR_MASK GENMASK_ULL(15, 0) 156 #define PEBS_DATACFG_FIX_SHIFT 48 157 #define PEBS_DATACFG_FIX_MASK GENMASK_ULL(7, 0) 158 159 /* Steal the highest bit of pebs_data_cfg for SW usage */ 160 #define PEBS_UPDATE_DS_SW BIT_ULL(63) 161 162 /* 163 * Intel "Architectural Performance Monitoring" CPUID 164 * detection/enumeration details: 165 */ 166 union cpuid10_eax { 167 struct { 168 unsigned int version_id:8; 169 unsigned int num_counters:8; 170 unsigned int bit_width:8; 171 unsigned int mask_length:8; 172 } split; 173 unsigned int full; 174 }; 175 176 union cpuid10_ebx { 177 struct { 178 unsigned int no_unhalted_core_cycles:1; 179 unsigned int no_instructions_retired:1; 180 unsigned int no_unhalted_reference_cycles:1; 181 unsigned int no_llc_reference:1; 182 unsigned int no_llc_misses:1; 183 unsigned int no_branch_instruction_retired:1; 184 unsigned int no_branch_misses_retired:1; 185 } split; 186 unsigned int full; 187 }; 188 189 union cpuid10_edx { 190 struct { 191 unsigned int num_counters_fixed:5; 192 unsigned int bit_width_fixed:8; 193 unsigned int reserved1:2; 194 unsigned int anythread_deprecated:1; 195 unsigned int reserved2:16; 196 } split; 197 unsigned int full; 198 }; 199 200 /* 201 * Intel "Architectural Performance Monitoring extension" CPUID 202 * detection/enumeration details: 203 */ 204 #define ARCH_PERFMON_EXT_LEAF 0x00000023 205 #define ARCH_PERFMON_NUM_COUNTER_LEAF 0x1 206 #define ARCH_PERFMON_ACR_LEAF 0x2 207 #define ARCH_PERFMON_PEBS_CAP_LEAF 0x4 208 #define ARCH_PERFMON_PEBS_COUNTER_LEAF 0x5 209 210 union cpuid35_eax { 211 struct { 212 unsigned int leaf0:1; 213 /* Counters Sub-Leaf */ 214 unsigned int cntr_subleaf:1; 215 /* Auto Counter Reload Sub-Leaf */ 216 unsigned int acr_subleaf:1; 217 /* Events Sub-Leaf */ 218 unsigned int events_subleaf:1; 219 /* arch-PEBS Sub-Leaves */ 220 unsigned int pebs_caps_subleaf:1; 221 unsigned int pebs_cnts_subleaf:1; 222 unsigned int reserved:26; 223 } split; 224 unsigned int full; 225 }; 226 227 union cpuid35_ebx { 228 struct { 229 /* UnitMask2 Supported */ 230 unsigned int umask2:1; 231 /* EQ-bit Supported */ 232 unsigned int eq:1; 233 /* rdpmc user disable Supported */ 234 unsigned int rdpmc_user_disable:1; 235 unsigned int reserved:29; 236 } split; 237 unsigned int full; 238 }; 239 240 /* 241 * Intel Architectural LBR CPUID detection/enumeration details: 242 */ 243 union cpuid28_eax { 244 struct { 245 /* Supported LBR depth values */ 246 unsigned int lbr_depth_mask:8; 247 unsigned int reserved:22; 248 /* Deep C-state Reset */ 249 unsigned int lbr_deep_c_reset:1; 250 /* IP values contain LIP */ 251 unsigned int lbr_lip:1; 252 } split; 253 unsigned int full; 254 }; 255 256 union cpuid28_ebx { 257 struct { 258 /* CPL Filtering Supported */ 259 unsigned int lbr_cpl:1; 260 /* Branch Filtering Supported */ 261 unsigned int lbr_filter:1; 262 /* Call-stack Mode Supported */ 263 unsigned int lbr_call_stack:1; 264 } split; 265 unsigned int full; 266 }; 267 268 union cpuid28_ecx { 269 struct { 270 /* Mispredict Bit Supported */ 271 unsigned int lbr_mispred:1; 272 /* Timed LBRs Supported */ 273 unsigned int lbr_timed_lbr:1; 274 /* Branch Type Field Supported */ 275 unsigned int lbr_br_type:1; 276 unsigned int reserved:13; 277 /* Branch counters (Event Logging) Supported */ 278 unsigned int lbr_counters:4; 279 } split; 280 unsigned int full; 281 }; 282 283 /* 284 * AMD "Extended Performance Monitoring and Debug" CPUID 285 * detection/enumeration details: 286 */ 287 union cpuid_0x80000022_ebx { 288 struct { 289 /* Number of Core Performance Counters */ 290 unsigned int num_core_pmc:4; 291 /* Number of available LBR Stack Entries */ 292 unsigned int lbr_v2_stack_sz:6; 293 /* Number of Data Fabric Counters */ 294 unsigned int num_df_pmc:6; 295 /* Number of Unified Memory Controller Counters */ 296 unsigned int num_umc_pmc:6; 297 } split; 298 unsigned int full; 299 }; 300 301 struct x86_pmu_capability { 302 int version; 303 int num_counters_gp; 304 int num_counters_fixed; 305 int bit_width_gp; 306 int bit_width_fixed; 307 unsigned int events_mask; 308 int events_mask_len; 309 unsigned int pebs_ept :1; 310 unsigned int mediated :1; 311 }; 312 313 /* 314 * Fixed-purpose performance events: 315 */ 316 317 /* RDPMC offset for Fixed PMCs */ 318 #define INTEL_PMC_FIXED_RDPMC_BASE (1 << 30) 319 #define INTEL_PMC_FIXED_RDPMC_METRICS (1 << 29) 320 321 /* 322 * All the fixed-mode PMCs are configured via this single MSR: 323 */ 324 #define MSR_ARCH_PERFMON_FIXED_CTR_CTRL 0x38d 325 326 /* 327 * There is no event-code assigned to the fixed-mode PMCs. 328 * 329 * For a fixed-mode PMC, which has an equivalent event on a general-purpose 330 * PMC, the event-code of the equivalent event is used for the fixed-mode PMC, 331 * e.g., Instr_Retired.Any and CPU_CLK_Unhalted.Core. 332 * 333 * For a fixed-mode PMC, which doesn't have an equivalent event, a 334 * pseudo-encoding is used, e.g., CPU_CLK_Unhalted.Ref and TOPDOWN.SLOTS. 335 * The pseudo event-code for a fixed-mode PMC must be 0x00. 336 * The pseudo umask-code is 0xX. The X equals the index of the fixed 337 * counter + 1, e.g., the fixed counter 2 has the pseudo-encoding 0x0300. 338 * 339 * The counts are available in separate MSRs: 340 */ 341 342 /* Instr_Retired.Any: */ 343 #define MSR_ARCH_PERFMON_FIXED_CTR0 0x309 344 #define INTEL_PMC_IDX_FIXED_INSTRUCTIONS (INTEL_PMC_IDX_FIXED + 0) 345 346 /* CPU_CLK_Unhalted.Core: */ 347 #define MSR_ARCH_PERFMON_FIXED_CTR1 0x30a 348 #define INTEL_PMC_IDX_FIXED_CPU_CYCLES (INTEL_PMC_IDX_FIXED + 1) 349 350 /* CPU_CLK_Unhalted.Ref: event=0x00,umask=0x3 (pseudo-encoding) */ 351 #define MSR_ARCH_PERFMON_FIXED_CTR2 0x30b 352 #define INTEL_PMC_IDX_FIXED_REF_CYCLES (INTEL_PMC_IDX_FIXED + 2) 353 #define INTEL_PMC_MSK_FIXED_REF_CYCLES (1ULL << INTEL_PMC_IDX_FIXED_REF_CYCLES) 354 355 /* TOPDOWN.SLOTS: event=0x00,umask=0x4 (pseudo-encoding) */ 356 #define MSR_ARCH_PERFMON_FIXED_CTR3 0x30c 357 #define INTEL_PMC_IDX_FIXED_SLOTS (INTEL_PMC_IDX_FIXED + 3) 358 #define INTEL_PMC_MSK_FIXED_SLOTS (1ULL << INTEL_PMC_IDX_FIXED_SLOTS) 359 360 /* TOPDOWN_BAD_SPECULATION.ALL: fixed counter 4 (Atom only) */ 361 /* TOPDOWN_FE_BOUND.ALL: fixed counter 5 (Atom only) */ 362 /* TOPDOWN_RETIRING.ALL: fixed counter 6 (Atom only) */ 363 364 static inline bool use_fixed_pseudo_encoding(u64 code) 365 { 366 return !(code & 0xff); 367 } 368 369 /* 370 * We model BTS tracing as another fixed-mode PMC. 371 * 372 * We choose the value 47 for the fixed index of BTS, since lower 373 * values are used by actual fixed events and higher values are used 374 * to indicate other overflow conditions in the PERF_GLOBAL_STATUS msr. 375 */ 376 #define INTEL_PMC_IDX_FIXED_BTS (INTEL_PMC_IDX_FIXED + 15) 377 378 /* 379 * The PERF_METRICS MSR is modeled as several magic fixed-mode PMCs, one for 380 * each TopDown metric event. 381 * 382 * Internally the TopDown metric events are mapped to the FxCtr 3 (SLOTS). 383 */ 384 #define INTEL_PMC_IDX_METRIC_BASE (INTEL_PMC_IDX_FIXED + 16) 385 #define INTEL_PMC_IDX_TD_RETIRING (INTEL_PMC_IDX_METRIC_BASE + 0) 386 #define INTEL_PMC_IDX_TD_BAD_SPEC (INTEL_PMC_IDX_METRIC_BASE + 1) 387 #define INTEL_PMC_IDX_TD_FE_BOUND (INTEL_PMC_IDX_METRIC_BASE + 2) 388 #define INTEL_PMC_IDX_TD_BE_BOUND (INTEL_PMC_IDX_METRIC_BASE + 3) 389 #define INTEL_PMC_IDX_TD_HEAVY_OPS (INTEL_PMC_IDX_METRIC_BASE + 4) 390 #define INTEL_PMC_IDX_TD_BR_MISPREDICT (INTEL_PMC_IDX_METRIC_BASE + 5) 391 #define INTEL_PMC_IDX_TD_FETCH_LAT (INTEL_PMC_IDX_METRIC_BASE + 6) 392 #define INTEL_PMC_IDX_TD_MEM_BOUND (INTEL_PMC_IDX_METRIC_BASE + 7) 393 #define INTEL_PMC_IDX_METRIC_END INTEL_PMC_IDX_TD_MEM_BOUND 394 #define INTEL_PMC_MSK_TOPDOWN ((0xffull << INTEL_PMC_IDX_METRIC_BASE) | \ 395 INTEL_PMC_MSK_FIXED_SLOTS) 396 397 /* 398 * There is no event-code assigned to the TopDown events. 399 * 400 * For the slots event, use the pseudo code of the fixed counter 3. 401 * 402 * For the metric events, the pseudo event-code is 0x00. 403 * The pseudo umask-code starts from the middle of the pseudo event 404 * space, 0x80. 405 */ 406 #define INTEL_TD_SLOTS 0x0400 /* TOPDOWN.SLOTS */ 407 /* Level 1 metrics */ 408 #define INTEL_TD_METRIC_RETIRING 0x8000 /* Retiring metric */ 409 #define INTEL_TD_METRIC_BAD_SPEC 0x8100 /* Bad speculation metric */ 410 #define INTEL_TD_METRIC_FE_BOUND 0x8200 /* FE bound metric */ 411 #define INTEL_TD_METRIC_BE_BOUND 0x8300 /* BE bound metric */ 412 /* Level 2 metrics */ 413 #define INTEL_TD_METRIC_HEAVY_OPS 0x8400 /* Heavy Operations metric */ 414 #define INTEL_TD_METRIC_BR_MISPREDICT 0x8500 /* Branch Mispredict metric */ 415 #define INTEL_TD_METRIC_FETCH_LAT 0x8600 /* Fetch Latency metric */ 416 #define INTEL_TD_METRIC_MEM_BOUND 0x8700 /* Memory bound metric */ 417 418 #define INTEL_TD_METRIC_MAX INTEL_TD_METRIC_MEM_BOUND 419 #define INTEL_TD_METRIC_NUM 8 420 421 #define INTEL_TD_CFG_METRIC_CLEAR_BIT 0 422 #define INTEL_TD_CFG_METRIC_CLEAR BIT_ULL(INTEL_TD_CFG_METRIC_CLEAR_BIT) 423 424 static inline bool is_metric_idx(int idx) 425 { 426 return (unsigned)(idx - INTEL_PMC_IDX_METRIC_BASE) < INTEL_TD_METRIC_NUM; 427 } 428 429 static inline bool is_topdown_idx(int idx) 430 { 431 return is_metric_idx(idx) || idx == INTEL_PMC_IDX_FIXED_SLOTS; 432 } 433 434 #define INTEL_PMC_OTHER_TOPDOWN_BITS(bit) \ 435 (~(0x1ull << bit) & INTEL_PMC_MSK_TOPDOWN) 436 437 #define GLOBAL_STATUS_COND_CHG BIT_ULL(63) 438 #define GLOBAL_STATUS_BUFFER_OVF_BIT 62 439 #define GLOBAL_STATUS_BUFFER_OVF BIT_ULL(GLOBAL_STATUS_BUFFER_OVF_BIT) 440 #define GLOBAL_STATUS_UNC_OVF BIT_ULL(61) 441 #define GLOBAL_STATUS_ASIF BIT_ULL(60) 442 #define GLOBAL_STATUS_COUNTERS_FROZEN BIT_ULL(59) 443 #define GLOBAL_STATUS_LBRS_FROZEN_BIT 58 444 #define GLOBAL_STATUS_LBRS_FROZEN BIT_ULL(GLOBAL_STATUS_LBRS_FROZEN_BIT) 445 #define GLOBAL_STATUS_TRACE_TOPAPMI_BIT 55 446 #define GLOBAL_STATUS_TRACE_TOPAPMI BIT_ULL(GLOBAL_STATUS_TRACE_TOPAPMI_BIT) 447 #define GLOBAL_STATUS_ARCH_PEBS_THRESHOLD_BIT 54 448 #define GLOBAL_STATUS_ARCH_PEBS_THRESHOLD BIT_ULL(GLOBAL_STATUS_ARCH_PEBS_THRESHOLD_BIT) 449 #define GLOBAL_STATUS_PERF_METRICS_OVF_BIT 48 450 451 #define GLOBAL_CTRL_EN_PERF_METRICS BIT_ULL(48) 452 /* 453 * We model guest LBR event tracing as another fixed-mode PMC like BTS. 454 * 455 * We choose bit 58 because it's used to indicate LBR stack frozen state 456 * for architectural perfmon v4, also we unconditionally mask that bit in 457 * the handle_pmi_common(), so it'll never be set in the overflow handling. 458 * 459 * With this fake counter assigned, the guest LBR event user (such as KVM), 460 * can program the LBR registers on its own, and we don't actually do anything 461 * with then in the host context. 462 */ 463 #define INTEL_PMC_IDX_FIXED_VLBR (GLOBAL_STATUS_LBRS_FROZEN_BIT) 464 465 /* 466 * Pseudo-encoding the guest LBR event as event=0x00,umask=0x1b, 467 * since it would claim bit 58 which is effectively Fixed26. 468 */ 469 #define INTEL_FIXED_VLBR_EVENT 0x1b00 470 471 /* 472 * Adaptive PEBS v4 473 */ 474 475 struct pebs_basic { 476 u64 format_group:32, 477 retire_latency:16, 478 format_size:16; 479 u64 ip; 480 u64 applicable_counters; 481 u64 tsc; 482 }; 483 484 struct pebs_meminfo { 485 u64 address; 486 u64 aux; 487 union { 488 /* pre Alder Lake */ 489 u64 mem_latency; 490 /* Alder Lake and later */ 491 struct { 492 u64 instr_latency:16; 493 u64 pad2:16; 494 u64 cache_latency:16; 495 u64 pad3:16; 496 }; 497 }; 498 u64 tsx_tuning; 499 }; 500 501 struct pebs_gprs { 502 u64 flags, ip, ax, cx, dx, bx, sp, bp, si, di; 503 u64 r8, r9, r10, r11, r12, r13, r14, r15; 504 }; 505 506 struct pebs_xmm { 507 u64 xmm[16*2]; /* two entries for each register */ 508 }; 509 510 struct pebs_cntr_header { 511 u32 cntr; 512 u32 fixed; 513 u32 metrics; 514 u32 reserved; 515 }; 516 517 #define INTEL_CNTR_METRICS 0x3 518 519 /* 520 * Arch PEBS 521 */ 522 union arch_pebs_index { 523 struct { 524 u64 rsvd:4, 525 wr:23, 526 rsvd2:4, 527 full:1, 528 en:1, 529 rsvd3:3, 530 thresh:23, 531 rsvd4:5; 532 }; 533 u64 whole; 534 }; 535 536 struct arch_pebs_header { 537 union { 538 u64 format; 539 struct { 540 u64 size:16, /* Record size */ 541 rsvd:14, 542 mode:1, /* 64BIT_MODE */ 543 cont:1, 544 rsvd2:3, 545 cntr:5, 546 lbr:2, 547 rsvd3:7, 548 xmm:1, 549 ymmh:1, 550 rsvd4:2, 551 opmask:1, 552 zmmh:1, 553 h16zmm:1, 554 rsvd5:5, 555 gpr:1, 556 aux:1, 557 basic:1; 558 }; 559 }; 560 u64 rsvd6; 561 }; 562 563 struct arch_pebs_basic { 564 u64 ip; 565 u64 applicable_counters; 566 u64 tsc; 567 u64 retire :16, /* Retire Latency */ 568 valid :1, 569 rsvd :47; 570 u64 rsvd2; 571 u64 rsvd3; 572 }; 573 574 struct arch_pebs_aux { 575 u64 address; 576 u64 rsvd; 577 u64 rsvd2; 578 u64 rsvd3; 579 u64 rsvd4; 580 u64 aux; 581 u64 instr_latency :16, 582 pad2 :16, 583 cache_latency :16, 584 pad3 :16; 585 u64 tsx_tuning; 586 }; 587 588 struct arch_pebs_gprs { 589 u64 flags, ip, ax, cx, dx, bx, sp, bp, si, di; 590 u64 r8, r9, r10, r11, r12, r13, r14, r15, ssp; 591 u64 rsvd; 592 }; 593 594 struct arch_pebs_xer_header { 595 u64 xstate; 596 u64 rsvd; 597 }; 598 599 #define ARCH_PEBS_LBR_NAN 0x0 600 #define ARCH_PEBS_LBR_NUM_8 0x1 601 #define ARCH_PEBS_LBR_NUM_16 0x2 602 #define ARCH_PEBS_LBR_NUM_VAR 0x3 603 #define ARCH_PEBS_BASE_LBR_ENTRIES 8 604 struct arch_pebs_lbr_header { 605 u64 rsvd; 606 u64 ctl; 607 u64 depth; 608 u64 ler_from; 609 u64 ler_to; 610 u64 ler_info; 611 }; 612 613 struct arch_pebs_cntr_header { 614 u32 cntr; 615 u32 fixed; 616 u32 metrics; 617 u32 reserved; 618 }; 619 620 /* 621 * AMD Extended Performance Monitoring and Debug cpuid feature detection 622 */ 623 #define EXT_PERFMON_DEBUG_FEATURES 0x80000022 624 625 /* 626 * IBS cpuid feature detection 627 */ 628 629 #define IBS_CPUID_FEATURES 0x8000001b 630 631 /* 632 * Same bit mask as for IBS cpuid feature flags (Fn8000_001B_EAX), but 633 * bit 0 is used to indicate the existence of IBS. 634 */ 635 #define IBS_CAPS_AVAIL (1U<<0) 636 #define IBS_CAPS_FETCHSAM (1U<<1) 637 #define IBS_CAPS_OPSAM (1U<<2) 638 #define IBS_CAPS_RDWROPCNT (1U<<3) 639 #define IBS_CAPS_OPCNT (1U<<4) 640 #define IBS_CAPS_BRNTRGT (1U<<5) 641 #define IBS_CAPS_OPCNTEXT (1U<<6) 642 #define IBS_CAPS_RIPINVALIDCHK (1U<<7) 643 #define IBS_CAPS_OPBRNFUSE (1U<<8) 644 #define IBS_CAPS_FETCHCTLEXTD (1U<<9) 645 #define IBS_CAPS_OPDATA4 (1U<<10) 646 #define IBS_CAPS_ZEN4 (1U<<11) 647 #define IBS_CAPS_OPLDLAT (1U<<12) 648 #define IBS_CAPS_DIS (1U<<13) 649 #define IBS_CAPS_FETCHLAT (1U<<14) 650 #define IBS_CAPS_BIT63_FILTER (1U<<15) 651 #define IBS_CAPS_STRMST_RMTSOCKET (1U<<16) 652 #define IBS_CAPS_OPDTLBPGSIZE (1U<<19) 653 654 #define IBS_CAPS_DEFAULT (IBS_CAPS_AVAIL \ 655 | IBS_CAPS_FETCHSAM \ 656 | IBS_CAPS_OPSAM) 657 658 /* 659 * IBS APIC setup 660 */ 661 #define IBSCTL 0x1cc 662 #define IBSCTL_LVT_OFFSET_VALID (1ULL<<8) 663 #define IBSCTL_LVT_OFFSET_MASK 0x0F 664 665 /* IBS fetch bits/masks */ 666 #define IBS_FETCH_L3MISSONLY (1ULL << 59) 667 #define IBS_FETCH_RAND_EN (1ULL << 57) 668 #define IBS_FETCH_VAL (1ULL << 49) 669 #define IBS_FETCH_ENABLE (1ULL << 48) 670 #define IBS_FETCH_CNT 0xFFFF0000ULL 671 #define IBS_FETCH_MAX_CNT 0x0000FFFFULL 672 673 #define IBS_FETCH_2_DIS (1ULL << 0) 674 #define IBS_FETCH_2_FETCHLAT_FILTER (0xFULL << 1) 675 #define IBS_FETCH_2_FETCHLAT_FILTER_SHIFT (1) 676 #define IBS_FETCH_2_EXCL_RIP_63_EQ_1 (1ULL << 5) 677 #define IBS_FETCH_2_EXCL_RIP_63_EQ_0 (1ULL << 6) 678 679 /* 680 * IBS op bits/masks 681 * The lower 7 bits of the current count are random bits 682 * preloaded by hardware and ignored in software 683 */ 684 #define IBS_OP_LDLAT_EN (1ULL << 63) 685 #define IBS_OP_LDLAT_THRSH (0xFULL << 59) 686 #define IBS_OP_LDLAT_THRSH_SHIFT (59) 687 #define IBS_OP_CUR_CNT (0xFFF80ULL << 32) 688 #define IBS_OP_CUR_CNT_RAND (0x0007FULL << 32) 689 #define IBS_OP_CUR_CNT_EXT_MASK (0x7FULL << 52) 690 #define IBS_OP_CNT_CTL (1ULL << 19) 691 #define IBS_OP_VAL (1ULL << 18) 692 #define IBS_OP_ENABLE (1ULL << 17) 693 #define IBS_OP_L3MISSONLY (1ULL << 16) 694 #define IBS_OP_MAX_CNT 0x0000FFFFULL 695 #define IBS_OP_MAX_CNT_EXT 0x007FFFFFULL /* not a register bit mask */ 696 #define IBS_OP_MAX_CNT_EXT_MASK (0x7FULL << 20) /* separate upper 7 bits */ 697 #define IBS_RIP_INVALID (1ULL << 38) 698 699 #define IBS_OP_2_DIS (1ULL << 0) 700 #define IBS_OP_2_EXCL_RIP_63_EQ_0 (1ULL << 1) 701 #define IBS_OP_2_EXCL_RIP_63_EQ_1 (1ULL << 2) 702 #define IBS_OP_2_STRM_ST_FILTER (1ULL << 3) 703 #define IBS_OP_2_STRM_ST_FILTER_SHIFT (3) 704 705 #ifdef CONFIG_X86_LOCAL_APIC 706 extern u32 get_ibs_caps(void); 707 extern int forward_event_to_ibs(struct perf_event *event); 708 #else 709 static inline u32 get_ibs_caps(void) { return 0; } 710 static inline int forward_event_to_ibs(struct perf_event *event) { return -ENOENT; } 711 #endif 712 713 #ifdef CONFIG_PERF_EVENTS 714 extern void perf_events_lapic_init(void); 715 716 /* 717 * Abuse bits {3,5} of the cpu eflags register. These flags are otherwise 718 * unused and ABI specified to be 0, so nobody should care what we do with 719 * them. 720 * 721 * EXACT - the IP points to the exact instruction that triggered the 722 * event (HW bugs exempt). 723 * VM - original X86_VM_MASK; see set_linear_ip(). 724 */ 725 #define PERF_EFLAGS_EXACT (1UL << 3) 726 #define PERF_EFLAGS_VM (1UL << 5) 727 728 struct pt_regs; 729 struct x86_perf_regs { 730 struct pt_regs regs; 731 u64 *xmm_regs; 732 }; 733 734 extern unsigned long perf_arch_instruction_pointer(struct pt_regs *regs); 735 extern unsigned long perf_arch_misc_flags(struct pt_regs *regs); 736 extern unsigned long perf_arch_guest_misc_flags(struct pt_regs *regs); 737 #define perf_arch_misc_flags(regs) perf_arch_misc_flags(regs) 738 #define perf_arch_guest_misc_flags(regs) perf_arch_guest_misc_flags(regs) 739 740 #include <asm/stacktrace.h> 741 742 /* 743 * We abuse bit 3 from flags to pass exact information, see 744 * perf_arch_misc_flags() and the comment with PERF_EFLAGS_EXACT. 745 */ 746 #define perf_arch_fetch_caller_regs(regs, __ip) { \ 747 (regs)->ip = (__ip); \ 748 (regs)->sp = (unsigned long)__builtin_frame_address(0); \ 749 (regs)->cs = __KERNEL_CS; \ 750 regs->flags = 0; \ 751 } 752 753 struct perf_guest_switch_msr { 754 unsigned msr; 755 u64 host, guest; 756 }; 757 758 struct x86_pmu_lbr { 759 unsigned int nr; 760 unsigned int from; 761 unsigned int to; 762 unsigned int info; 763 bool has_callstack; 764 }; 765 766 extern void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap); 767 extern u64 perf_get_hw_event_config(int hw_event); 768 extern void perf_check_microcode(void); 769 extern void perf_clear_dirty_counters(void); 770 extern int x86_perf_rdpmc_index(struct perf_event *event); 771 #else 772 static inline void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap) 773 { 774 memset(cap, 0, sizeof(*cap)); 775 } 776 777 static inline u64 perf_get_hw_event_config(int hw_event) 778 { 779 return 0; 780 } 781 782 static inline void perf_events_lapic_init(void) { } 783 static inline void perf_check_microcode(void) { } 784 #endif 785 786 #ifdef CONFIG_PERF_GUEST_MEDIATED_PMU 787 extern void perf_load_guest_lvtpc(u32 guest_lvtpc); 788 extern void perf_put_guest_lvtpc(void); 789 #endif 790 791 #if defined(CONFIG_PERF_EVENTS) && defined(CONFIG_CPU_SUP_INTEL) 792 extern struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr, void *data); 793 extern void x86_perf_get_lbr(struct x86_pmu_lbr *lbr); 794 #else 795 struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr, void *data); 796 static inline void x86_perf_get_lbr(struct x86_pmu_lbr *lbr) 797 { 798 memset(lbr, 0, sizeof(*lbr)); 799 } 800 #endif 801 802 #ifdef CONFIG_CPU_SUP_INTEL 803 extern void intel_pt_handle_vmx(int on); 804 #else 805 static inline void intel_pt_handle_vmx(int on) 806 { 807 808 } 809 #endif 810 811 #if defined(CONFIG_PERF_EVENTS) && defined(CONFIG_CPU_SUP_AMD) 812 extern void amd_pmu_enable_virt(void); 813 extern void amd_pmu_disable_virt(void); 814 815 #if defined(CONFIG_PERF_EVENTS_AMD_BRS) 816 817 #define PERF_NEEDS_LOPWR_CB 1 818 819 /* 820 * architectural low power callback impacts 821 * drivers/acpi/processor_idle.c 822 * drivers/acpi/acpi_pad.c 823 */ 824 extern void perf_amd_brs_lopwr_cb(bool lopwr_in); 825 826 DECLARE_STATIC_CALL(perf_lopwr_cb, perf_amd_brs_lopwr_cb); 827 828 static __always_inline void perf_lopwr_cb(bool lopwr_in) 829 { 830 static_call_mod(perf_lopwr_cb)(lopwr_in); 831 } 832 833 #endif /* PERF_NEEDS_LOPWR_CB */ 834 835 #else 836 static inline void amd_pmu_enable_virt(void) { } 837 static inline void amd_pmu_disable_virt(void) { } 838 #endif 839 840 #define arch_perf_out_copy_user copy_from_user_nmi 841 842 #endif /* _ASM_X86_PERF_EVENT_H */ 843