1 #ifndef _ASM_X86_PERCPU_H 2 #define _ASM_X86_PERCPU_H 3 4 #ifdef CONFIG_X86_64 5 #define __percpu_seg gs 6 #define __percpu_mov_op movq 7 #else 8 #define __percpu_seg fs 9 #define __percpu_mov_op movl 10 #endif 11 12 #ifdef __ASSEMBLY__ 13 14 /* 15 * PER_CPU finds an address of a per-cpu variable. 16 * 17 * Args: 18 * var - variable name 19 * reg - 32bit register 20 * 21 * The resulting address is stored in the "reg" argument. 22 * 23 * Example: 24 * PER_CPU(cpu_gdt_descr, %ebx) 25 */ 26 #ifdef CONFIG_SMP 27 #define PER_CPU(var, reg) \ 28 __percpu_mov_op %__percpu_seg:this_cpu_off, reg; \ 29 lea var(reg), reg 30 #define PER_CPU_VAR(var) %__percpu_seg:var 31 #else /* ! SMP */ 32 #define PER_CPU(var, reg) __percpu_mov_op $var, reg 33 #define PER_CPU_VAR(var) var 34 #endif /* SMP */ 35 36 #ifdef CONFIG_X86_64_SMP 37 #define INIT_PER_CPU_VAR(var) init_per_cpu__##var 38 #else 39 #define INIT_PER_CPU_VAR(var) var 40 #endif 41 42 #else /* ...!ASSEMBLY */ 43 44 #include <linux/kernel.h> 45 #include <linux/stringify.h> 46 47 #ifdef CONFIG_SMP 48 #define __percpu_arg(x) "%%"__stringify(__percpu_seg)":%P" #x 49 #define __my_cpu_offset percpu_read(this_cpu_off) 50 51 /* 52 * Compared to the generic __my_cpu_offset version, the following 53 * saves one instruction and avoids clobbering a temp register. 54 */ 55 #define __this_cpu_ptr(ptr) \ 56 ({ \ 57 unsigned long tcp_ptr__; \ 58 __verify_pcpu_ptr(ptr); \ 59 asm volatile("add " __percpu_arg(1) ", %0" \ 60 : "=r" (tcp_ptr__) \ 61 : "m" (this_cpu_off), "0" (ptr)); \ 62 (typeof(*(ptr)) __kernel __force *)tcp_ptr__; \ 63 }) 64 #else 65 #define __percpu_arg(x) "%P" #x 66 #endif 67 68 /* 69 * Initialized pointers to per-cpu variables needed for the boot 70 * processor need to use these macros to get the proper address 71 * offset from __per_cpu_load on SMP. 72 * 73 * There also must be an entry in vmlinux_64.lds.S 74 */ 75 #define DECLARE_INIT_PER_CPU(var) \ 76 extern typeof(var) init_per_cpu_var(var) 77 78 #ifdef CONFIG_X86_64_SMP 79 #define init_per_cpu_var(var) init_per_cpu__##var 80 #else 81 #define init_per_cpu_var(var) var 82 #endif 83 84 /* For arch-specific code, we can use direct single-insn ops (they 85 * don't give an lvalue though). */ 86 extern void __bad_percpu_size(void); 87 88 #define percpu_to_op(op, var, val) \ 89 do { \ 90 typedef typeof(var) pto_T__; \ 91 if (0) { \ 92 pto_T__ pto_tmp__; \ 93 pto_tmp__ = (val); \ 94 (void)pto_tmp__; \ 95 } \ 96 switch (sizeof(var)) { \ 97 case 1: \ 98 asm(op "b %1,"__percpu_arg(0) \ 99 : "+m" (var) \ 100 : "qi" ((pto_T__)(val))); \ 101 break; \ 102 case 2: \ 103 asm(op "w %1,"__percpu_arg(0) \ 104 : "+m" (var) \ 105 : "ri" ((pto_T__)(val))); \ 106 break; \ 107 case 4: \ 108 asm(op "l %1,"__percpu_arg(0) \ 109 : "+m" (var) \ 110 : "ri" ((pto_T__)(val))); \ 111 break; \ 112 case 8: \ 113 asm(op "q %1,"__percpu_arg(0) \ 114 : "+m" (var) \ 115 : "re" ((pto_T__)(val))); \ 116 break; \ 117 default: __bad_percpu_size(); \ 118 } \ 119 } while (0) 120 121 /* 122 * Generate a percpu add to memory instruction and optimize code 123 * if one is added or subtracted. 124 */ 125 #define percpu_add_op(var, val) \ 126 do { \ 127 typedef typeof(var) pao_T__; \ 128 const int pao_ID__ = (__builtin_constant_p(val) && \ 129 ((val) == 1 || (val) == -1)) ? (val) : 0; \ 130 if (0) { \ 131 pao_T__ pao_tmp__; \ 132 pao_tmp__ = (val); \ 133 (void)pao_tmp__; \ 134 } \ 135 switch (sizeof(var)) { \ 136 case 1: \ 137 if (pao_ID__ == 1) \ 138 asm("incb "__percpu_arg(0) : "+m" (var)); \ 139 else if (pao_ID__ == -1) \ 140 asm("decb "__percpu_arg(0) : "+m" (var)); \ 141 else \ 142 asm("addb %1, "__percpu_arg(0) \ 143 : "+m" (var) \ 144 : "qi" ((pao_T__)(val))); \ 145 break; \ 146 case 2: \ 147 if (pao_ID__ == 1) \ 148 asm("incw "__percpu_arg(0) : "+m" (var)); \ 149 else if (pao_ID__ == -1) \ 150 asm("decw "__percpu_arg(0) : "+m" (var)); \ 151 else \ 152 asm("addw %1, "__percpu_arg(0) \ 153 : "+m" (var) \ 154 : "ri" ((pao_T__)(val))); \ 155 break; \ 156 case 4: \ 157 if (pao_ID__ == 1) \ 158 asm("incl "__percpu_arg(0) : "+m" (var)); \ 159 else if (pao_ID__ == -1) \ 160 asm("decl "__percpu_arg(0) : "+m" (var)); \ 161 else \ 162 asm("addl %1, "__percpu_arg(0) \ 163 : "+m" (var) \ 164 : "ri" ((pao_T__)(val))); \ 165 break; \ 166 case 8: \ 167 if (pao_ID__ == 1) \ 168 asm("incq "__percpu_arg(0) : "+m" (var)); \ 169 else if (pao_ID__ == -1) \ 170 asm("decq "__percpu_arg(0) : "+m" (var)); \ 171 else \ 172 asm("addq %1, "__percpu_arg(0) \ 173 : "+m" (var) \ 174 : "re" ((pao_T__)(val))); \ 175 break; \ 176 default: __bad_percpu_size(); \ 177 } \ 178 } while (0) 179 180 #define percpu_from_op(op, var, constraint) \ 181 ({ \ 182 typeof(var) pfo_ret__; \ 183 switch (sizeof(var)) { \ 184 case 1: \ 185 asm(op "b "__percpu_arg(1)",%0" \ 186 : "=q" (pfo_ret__) \ 187 : constraint); \ 188 break; \ 189 case 2: \ 190 asm(op "w "__percpu_arg(1)",%0" \ 191 : "=r" (pfo_ret__) \ 192 : constraint); \ 193 break; \ 194 case 4: \ 195 asm(op "l "__percpu_arg(1)",%0" \ 196 : "=r" (pfo_ret__) \ 197 : constraint); \ 198 break; \ 199 case 8: \ 200 asm(op "q "__percpu_arg(1)",%0" \ 201 : "=r" (pfo_ret__) \ 202 : constraint); \ 203 break; \ 204 default: __bad_percpu_size(); \ 205 } \ 206 pfo_ret__; \ 207 }) 208 209 #define percpu_unary_op(op, var) \ 210 ({ \ 211 switch (sizeof(var)) { \ 212 case 1: \ 213 asm(op "b "__percpu_arg(0) \ 214 : "+m" (var)); \ 215 break; \ 216 case 2: \ 217 asm(op "w "__percpu_arg(0) \ 218 : "+m" (var)); \ 219 break; \ 220 case 4: \ 221 asm(op "l "__percpu_arg(0) \ 222 : "+m" (var)); \ 223 break; \ 224 case 8: \ 225 asm(op "q "__percpu_arg(0) \ 226 : "+m" (var)); \ 227 break; \ 228 default: __bad_percpu_size(); \ 229 } \ 230 }) 231 232 /* 233 * Add return operation 234 */ 235 #define percpu_add_return_op(var, val) \ 236 ({ \ 237 typeof(var) paro_ret__ = val; \ 238 switch (sizeof(var)) { \ 239 case 1: \ 240 asm("xaddb %0, "__percpu_arg(1) \ 241 : "+q" (paro_ret__), "+m" (var) \ 242 : : "memory"); \ 243 break; \ 244 case 2: \ 245 asm("xaddw %0, "__percpu_arg(1) \ 246 : "+r" (paro_ret__), "+m" (var) \ 247 : : "memory"); \ 248 break; \ 249 case 4: \ 250 asm("xaddl %0, "__percpu_arg(1) \ 251 : "+r" (paro_ret__), "+m" (var) \ 252 : : "memory"); \ 253 break; \ 254 case 8: \ 255 asm("xaddq %0, "__percpu_arg(1) \ 256 : "+re" (paro_ret__), "+m" (var) \ 257 : : "memory"); \ 258 break; \ 259 default: __bad_percpu_size(); \ 260 } \ 261 paro_ret__ += val; \ 262 paro_ret__; \ 263 }) 264 265 /* 266 * xchg is implemented using cmpxchg without a lock prefix. xchg is 267 * expensive due to the implied lock prefix. The processor cannot prefetch 268 * cachelines if xchg is used. 269 */ 270 #define percpu_xchg_op(var, nval) \ 271 ({ \ 272 typeof(var) pxo_ret__; \ 273 typeof(var) pxo_new__ = (nval); \ 274 switch (sizeof(var)) { \ 275 case 1: \ 276 asm("\n\tmov "__percpu_arg(1)",%%al" \ 277 "\n1:\tcmpxchgb %2, "__percpu_arg(1) \ 278 "\n\tjnz 1b" \ 279 : "=&a" (pxo_ret__), "+m" (var) \ 280 : "q" (pxo_new__) \ 281 : "memory"); \ 282 break; \ 283 case 2: \ 284 asm("\n\tmov "__percpu_arg(1)",%%ax" \ 285 "\n1:\tcmpxchgw %2, "__percpu_arg(1) \ 286 "\n\tjnz 1b" \ 287 : "=&a" (pxo_ret__), "+m" (var) \ 288 : "r" (pxo_new__) \ 289 : "memory"); \ 290 break; \ 291 case 4: \ 292 asm("\n\tmov "__percpu_arg(1)",%%eax" \ 293 "\n1:\tcmpxchgl %2, "__percpu_arg(1) \ 294 "\n\tjnz 1b" \ 295 : "=&a" (pxo_ret__), "+m" (var) \ 296 : "r" (pxo_new__) \ 297 : "memory"); \ 298 break; \ 299 case 8: \ 300 asm("\n\tmov "__percpu_arg(1)",%%rax" \ 301 "\n1:\tcmpxchgq %2, "__percpu_arg(1) \ 302 "\n\tjnz 1b" \ 303 : "=&a" (pxo_ret__), "+m" (var) \ 304 : "r" (pxo_new__) \ 305 : "memory"); \ 306 break; \ 307 default: __bad_percpu_size(); \ 308 } \ 309 pxo_ret__; \ 310 }) 311 312 /* 313 * cmpxchg has no such implied lock semantics as a result it is much 314 * more efficient for cpu local operations. 315 */ 316 #define percpu_cmpxchg_op(var, oval, nval) \ 317 ({ \ 318 typeof(var) pco_ret__; \ 319 typeof(var) pco_old__ = (oval); \ 320 typeof(var) pco_new__ = (nval); \ 321 switch (sizeof(var)) { \ 322 case 1: \ 323 asm("cmpxchgb %2, "__percpu_arg(1) \ 324 : "=a" (pco_ret__), "+m" (var) \ 325 : "q" (pco_new__), "0" (pco_old__) \ 326 : "memory"); \ 327 break; \ 328 case 2: \ 329 asm("cmpxchgw %2, "__percpu_arg(1) \ 330 : "=a" (pco_ret__), "+m" (var) \ 331 : "r" (pco_new__), "0" (pco_old__) \ 332 : "memory"); \ 333 break; \ 334 case 4: \ 335 asm("cmpxchgl %2, "__percpu_arg(1) \ 336 : "=a" (pco_ret__), "+m" (var) \ 337 : "r" (pco_new__), "0" (pco_old__) \ 338 : "memory"); \ 339 break; \ 340 case 8: \ 341 asm("cmpxchgq %2, "__percpu_arg(1) \ 342 : "=a" (pco_ret__), "+m" (var) \ 343 : "r" (pco_new__), "0" (pco_old__) \ 344 : "memory"); \ 345 break; \ 346 default: __bad_percpu_size(); \ 347 } \ 348 pco_ret__; \ 349 }) 350 351 /* 352 * percpu_read() makes gcc load the percpu variable every time it is 353 * accessed while percpu_read_stable() allows the value to be cached. 354 * percpu_read_stable() is more efficient and can be used if its value 355 * is guaranteed to be valid across cpus. The current users include 356 * get_current() and get_thread_info() both of which are actually 357 * per-thread variables implemented as per-cpu variables and thus 358 * stable for the duration of the respective task. 359 */ 360 #define percpu_read(var) percpu_from_op("mov", var, "m" (var)) 361 #define percpu_read_stable(var) percpu_from_op("mov", var, "p" (&(var))) 362 #define percpu_write(var, val) percpu_to_op("mov", var, val) 363 #define percpu_add(var, val) percpu_add_op(var, val) 364 #define percpu_sub(var, val) percpu_add_op(var, -(val)) 365 #define percpu_and(var, val) percpu_to_op("and", var, val) 366 #define percpu_or(var, val) percpu_to_op("or", var, val) 367 #define percpu_xor(var, val) percpu_to_op("xor", var, val) 368 #define percpu_inc(var) percpu_unary_op("inc", var) 369 370 #define __this_cpu_read_1(pcp) percpu_from_op("mov", (pcp), "m"(pcp)) 371 #define __this_cpu_read_2(pcp) percpu_from_op("mov", (pcp), "m"(pcp)) 372 #define __this_cpu_read_4(pcp) percpu_from_op("mov", (pcp), "m"(pcp)) 373 374 #define __this_cpu_write_1(pcp, val) percpu_to_op("mov", (pcp), val) 375 #define __this_cpu_write_2(pcp, val) percpu_to_op("mov", (pcp), val) 376 #define __this_cpu_write_4(pcp, val) percpu_to_op("mov", (pcp), val) 377 #define __this_cpu_add_1(pcp, val) percpu_add_op((pcp), val) 378 #define __this_cpu_add_2(pcp, val) percpu_add_op((pcp), val) 379 #define __this_cpu_add_4(pcp, val) percpu_add_op((pcp), val) 380 #define __this_cpu_and_1(pcp, val) percpu_to_op("and", (pcp), val) 381 #define __this_cpu_and_2(pcp, val) percpu_to_op("and", (pcp), val) 382 #define __this_cpu_and_4(pcp, val) percpu_to_op("and", (pcp), val) 383 #define __this_cpu_or_1(pcp, val) percpu_to_op("or", (pcp), val) 384 #define __this_cpu_or_2(pcp, val) percpu_to_op("or", (pcp), val) 385 #define __this_cpu_or_4(pcp, val) percpu_to_op("or", (pcp), val) 386 #define __this_cpu_xor_1(pcp, val) percpu_to_op("xor", (pcp), val) 387 #define __this_cpu_xor_2(pcp, val) percpu_to_op("xor", (pcp), val) 388 #define __this_cpu_xor_4(pcp, val) percpu_to_op("xor", (pcp), val) 389 /* 390 * Generic fallback operations for __this_cpu_xchg_[1-4] are okay and much 391 * faster than an xchg with forced lock semantics. 392 */ 393 #define __this_cpu_xchg_8(pcp, nval) percpu_xchg_op(pcp, nval) 394 #define __this_cpu_cmpxchg_8(pcp, oval, nval) percpu_cmpxchg_op(pcp, oval, nval) 395 396 #define this_cpu_read_1(pcp) percpu_from_op("mov", (pcp), "m"(pcp)) 397 #define this_cpu_read_2(pcp) percpu_from_op("mov", (pcp), "m"(pcp)) 398 #define this_cpu_read_4(pcp) percpu_from_op("mov", (pcp), "m"(pcp)) 399 #define this_cpu_write_1(pcp, val) percpu_to_op("mov", (pcp), val) 400 #define this_cpu_write_2(pcp, val) percpu_to_op("mov", (pcp), val) 401 #define this_cpu_write_4(pcp, val) percpu_to_op("mov", (pcp), val) 402 #define this_cpu_add_1(pcp, val) percpu_add_op((pcp), val) 403 #define this_cpu_add_2(pcp, val) percpu_add_op((pcp), val) 404 #define this_cpu_add_4(pcp, val) percpu_add_op((pcp), val) 405 #define this_cpu_and_1(pcp, val) percpu_to_op("and", (pcp), val) 406 #define this_cpu_and_2(pcp, val) percpu_to_op("and", (pcp), val) 407 #define this_cpu_and_4(pcp, val) percpu_to_op("and", (pcp), val) 408 #define this_cpu_or_1(pcp, val) percpu_to_op("or", (pcp), val) 409 #define this_cpu_or_2(pcp, val) percpu_to_op("or", (pcp), val) 410 #define this_cpu_or_4(pcp, val) percpu_to_op("or", (pcp), val) 411 #define this_cpu_xor_1(pcp, val) percpu_to_op("xor", (pcp), val) 412 #define this_cpu_xor_2(pcp, val) percpu_to_op("xor", (pcp), val) 413 #define this_cpu_xor_4(pcp, val) percpu_to_op("xor", (pcp), val) 414 #define this_cpu_xchg_1(pcp, nval) percpu_xchg_op(pcp, nval) 415 #define this_cpu_xchg_2(pcp, nval) percpu_xchg_op(pcp, nval) 416 #define this_cpu_xchg_4(pcp, nval) percpu_xchg_op(pcp, nval) 417 418 #define irqsafe_cpu_add_1(pcp, val) percpu_add_op((pcp), val) 419 #define irqsafe_cpu_add_2(pcp, val) percpu_add_op((pcp), val) 420 #define irqsafe_cpu_add_4(pcp, val) percpu_add_op((pcp), val) 421 #define irqsafe_cpu_and_1(pcp, val) percpu_to_op("and", (pcp), val) 422 #define irqsafe_cpu_and_2(pcp, val) percpu_to_op("and", (pcp), val) 423 #define irqsafe_cpu_and_4(pcp, val) percpu_to_op("and", (pcp), val) 424 #define irqsafe_cpu_or_1(pcp, val) percpu_to_op("or", (pcp), val) 425 #define irqsafe_cpu_or_2(pcp, val) percpu_to_op("or", (pcp), val) 426 #define irqsafe_cpu_or_4(pcp, val) percpu_to_op("or", (pcp), val) 427 #define irqsafe_cpu_xor_1(pcp, val) percpu_to_op("xor", (pcp), val) 428 #define irqsafe_cpu_xor_2(pcp, val) percpu_to_op("xor", (pcp), val) 429 #define irqsafe_cpu_xor_4(pcp, val) percpu_to_op("xor", (pcp), val) 430 #define irqsafe_cpu_xchg_1(pcp, nval) percpu_xchg_op(pcp, nval) 431 #define irqsafe_cpu_xchg_2(pcp, nval) percpu_xchg_op(pcp, nval) 432 #define irqsafe_cpu_xchg_4(pcp, nval) percpu_xchg_op(pcp, nval) 433 434 #ifndef CONFIG_M386 435 #define __this_cpu_add_return_1(pcp, val) percpu_add_return_op(pcp, val) 436 #define __this_cpu_add_return_2(pcp, val) percpu_add_return_op(pcp, val) 437 #define __this_cpu_add_return_4(pcp, val) percpu_add_return_op(pcp, val) 438 #define __this_cpu_cmpxchg_1(pcp, oval, nval) percpu_cmpxchg_op(pcp, oval, nval) 439 #define __this_cpu_cmpxchg_2(pcp, oval, nval) percpu_cmpxchg_op(pcp, oval, nval) 440 #define __this_cpu_cmpxchg_4(pcp, oval, nval) percpu_cmpxchg_op(pcp, oval, nval) 441 442 #define this_cpu_add_return_1(pcp, val) percpu_add_return_op(pcp, val) 443 #define this_cpu_add_return_2(pcp, val) percpu_add_return_op(pcp, val) 444 #define this_cpu_add_return_4(pcp, val) percpu_add_return_op(pcp, val) 445 #define this_cpu_cmpxchg_1(pcp, oval, nval) percpu_cmpxchg_op(pcp, oval, nval) 446 #define this_cpu_cmpxchg_2(pcp, oval, nval) percpu_cmpxchg_op(pcp, oval, nval) 447 #define this_cpu_cmpxchg_4(pcp, oval, nval) percpu_cmpxchg_op(pcp, oval, nval) 448 449 #define irqsafe_cpu_cmpxchg_1(pcp, oval, nval) percpu_cmpxchg_op(pcp, oval, nval) 450 #define irqsafe_cpu_cmpxchg_2(pcp, oval, nval) percpu_cmpxchg_op(pcp, oval, nval) 451 #define irqsafe_cpu_cmpxchg_4(pcp, oval, nval) percpu_cmpxchg_op(pcp, oval, nval) 452 #endif /* !CONFIG_M386 */ 453 454 #ifdef CONFIG_X86_CMPXCHG64 455 #define percpu_cmpxchg8b_double(pcp1, o1, o2, n1, n2) \ 456 ({ \ 457 char __ret; \ 458 typeof(o1) __o1 = o1; \ 459 typeof(o1) __n1 = n1; \ 460 typeof(o2) __o2 = o2; \ 461 typeof(o2) __n2 = n2; \ 462 typeof(o2) __dummy = n2; \ 463 asm volatile("cmpxchg8b "__percpu_arg(1)"\n\tsetz %0\n\t" \ 464 : "=a"(__ret), "=m" (pcp1), "=d"(__dummy) \ 465 : "b"(__n1), "c"(__n2), "a"(__o1), "d"(__o2)); \ 466 __ret; \ 467 }) 468 469 #define __this_cpu_cmpxchg_double_4(pcp1, pcp2, o1, o2, n1, n2) percpu_cmpxchg8b_double(pcp1, o1, o2, n1, n2) 470 #define this_cpu_cmpxchg_double_4(pcp1, pcp2, o1, o2, n1, n2) percpu_cmpxchg8b_double(pcp1, o1, o2, n1, n2) 471 #define irqsafe_cpu_cmpxchg_double_4(pcp1, pcp2, o1, o2, n1, n2) percpu_cmpxchg8b_double(pcp1, o1, o2, n1, n2) 472 #endif /* CONFIG_X86_CMPXCHG64 */ 473 474 /* 475 * Per cpu atomic 64 bit operations are only available under 64 bit. 476 * 32 bit must fall back to generic operations. 477 */ 478 #ifdef CONFIG_X86_64 479 #define __this_cpu_read_8(pcp) percpu_from_op("mov", (pcp), "m"(pcp)) 480 #define __this_cpu_write_8(pcp, val) percpu_to_op("mov", (pcp), val) 481 #define __this_cpu_add_8(pcp, val) percpu_add_op((pcp), val) 482 #define __this_cpu_and_8(pcp, val) percpu_to_op("and", (pcp), val) 483 #define __this_cpu_or_8(pcp, val) percpu_to_op("or", (pcp), val) 484 #define __this_cpu_xor_8(pcp, val) percpu_to_op("xor", (pcp), val) 485 #define __this_cpu_add_return_8(pcp, val) percpu_add_return_op(pcp, val) 486 487 #define this_cpu_read_8(pcp) percpu_from_op("mov", (pcp), "m"(pcp)) 488 #define this_cpu_write_8(pcp, val) percpu_to_op("mov", (pcp), val) 489 #define this_cpu_add_8(pcp, val) percpu_add_op((pcp), val) 490 #define this_cpu_and_8(pcp, val) percpu_to_op("and", (pcp), val) 491 #define this_cpu_or_8(pcp, val) percpu_to_op("or", (pcp), val) 492 #define this_cpu_xor_8(pcp, val) percpu_to_op("xor", (pcp), val) 493 #define this_cpu_add_return_8(pcp, val) percpu_add_return_op(pcp, val) 494 #define this_cpu_xchg_8(pcp, nval) percpu_xchg_op(pcp, nval) 495 #define this_cpu_cmpxchg_8(pcp, oval, nval) percpu_cmpxchg_op(pcp, oval, nval) 496 497 #define irqsafe_cpu_add_8(pcp, val) percpu_add_op((pcp), val) 498 #define irqsafe_cpu_and_8(pcp, val) percpu_to_op("and", (pcp), val) 499 #define irqsafe_cpu_or_8(pcp, val) percpu_to_op("or", (pcp), val) 500 #define irqsafe_cpu_xor_8(pcp, val) percpu_to_op("xor", (pcp), val) 501 #define irqsafe_cpu_xchg_8(pcp, nval) percpu_xchg_op(pcp, nval) 502 #define irqsafe_cpu_cmpxchg_8(pcp, oval, nval) percpu_cmpxchg_op(pcp, oval, nval) 503 504 /* 505 * Pretty complex macro to generate cmpxchg16 instruction. The instruction 506 * is not supported on early AMD64 processors so we must be able to emulate 507 * it in software. The address used in the cmpxchg16 instruction must be 508 * aligned to a 16 byte boundary. 509 */ 510 #define percpu_cmpxchg16b_double(pcp1, o1, o2, n1, n2) \ 511 ({ \ 512 char __ret; \ 513 typeof(o1) __o1 = o1; \ 514 typeof(o1) __n1 = n1; \ 515 typeof(o2) __o2 = o2; \ 516 typeof(o2) __n2 = n2; \ 517 typeof(o2) __dummy; \ 518 alternative_io("call this_cpu_cmpxchg16b_emu\n\t" P6_NOP4, \ 519 "cmpxchg16b %%gs:(%%rsi)\n\tsetz %0\n\t", \ 520 X86_FEATURE_CX16, \ 521 ASM_OUTPUT2("=a"(__ret), "=d"(__dummy)), \ 522 "S" (&pcp1), "b"(__n1), "c"(__n2), \ 523 "a"(__o1), "d"(__o2)); \ 524 __ret; \ 525 }) 526 527 #define __this_cpu_cmpxchg_double_8(pcp1, pcp2, o1, o2, n1, n2) percpu_cmpxchg16b_double(pcp1, o1, o2, n1, n2) 528 #define this_cpu_cmpxchg_double_8(pcp1, pcp2, o1, o2, n1, n2) percpu_cmpxchg16b_double(pcp1, o1, o2, n1, n2) 529 #define irqsafe_cpu_cmpxchg_double_8(pcp1, pcp2, o1, o2, n1, n2) percpu_cmpxchg16b_double(pcp1, o1, o2, n1, n2) 530 531 #endif 532 533 /* This is not atomic against other CPUs -- CPU preemption needs to be off */ 534 #define x86_test_and_clear_bit_percpu(bit, var) \ 535 ({ \ 536 int old__; \ 537 asm volatile("btr %2,"__percpu_arg(1)"\n\tsbbl %0,%0" \ 538 : "=r" (old__), "+m" (var) \ 539 : "dIr" (bit)); \ 540 old__; \ 541 }) 542 543 #include <asm-generic/percpu.h> 544 545 /* We can use this directly for local CPU (faster). */ 546 DECLARE_PER_CPU(unsigned long, this_cpu_off); 547 548 #endif /* !__ASSEMBLY__ */ 549 550 #ifdef CONFIG_SMP 551 552 /* 553 * Define the "EARLY_PER_CPU" macros. These are used for some per_cpu 554 * variables that are initialized and accessed before there are per_cpu 555 * areas allocated. 556 */ 557 558 #define DEFINE_EARLY_PER_CPU(_type, _name, _initvalue) \ 559 DEFINE_PER_CPU(_type, _name) = _initvalue; \ 560 __typeof__(_type) _name##_early_map[NR_CPUS] __initdata = \ 561 { [0 ... NR_CPUS-1] = _initvalue }; \ 562 __typeof__(_type) *_name##_early_ptr __refdata = _name##_early_map 563 564 #define EXPORT_EARLY_PER_CPU_SYMBOL(_name) \ 565 EXPORT_PER_CPU_SYMBOL(_name) 566 567 #define DECLARE_EARLY_PER_CPU(_type, _name) \ 568 DECLARE_PER_CPU(_type, _name); \ 569 extern __typeof__(_type) *_name##_early_ptr; \ 570 extern __typeof__(_type) _name##_early_map[] 571 572 #define early_per_cpu_ptr(_name) (_name##_early_ptr) 573 #define early_per_cpu_map(_name, _idx) (_name##_early_map[_idx]) 574 #define early_per_cpu(_name, _cpu) \ 575 *(early_per_cpu_ptr(_name) ? \ 576 &early_per_cpu_ptr(_name)[_cpu] : \ 577 &per_cpu(_name, _cpu)) 578 579 #else /* !CONFIG_SMP */ 580 #define DEFINE_EARLY_PER_CPU(_type, _name, _initvalue) \ 581 DEFINE_PER_CPU(_type, _name) = _initvalue 582 583 #define EXPORT_EARLY_PER_CPU_SYMBOL(_name) \ 584 EXPORT_PER_CPU_SYMBOL(_name) 585 586 #define DECLARE_EARLY_PER_CPU(_type, _name) \ 587 DECLARE_PER_CPU(_type, _name) 588 589 #define early_per_cpu(_name, _cpu) per_cpu(_name, _cpu) 590 #define early_per_cpu_ptr(_name) NULL 591 /* no early_per_cpu_map() */ 592 593 #endif /* !CONFIG_SMP */ 594 595 #endif /* _ASM_X86_PERCPU_H */ 596