1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Low-Level PCI Access for i386 machines. 4 * 5 * (c) 1999 Martin Mares <mj@ucw.cz> 6 */ 7 8 #include <linux/errno.h> 9 #include <linux/init.h> 10 #include <linux/ioport.h> 11 #include <linux/spinlock.h> 12 13 #undef DEBUG 14 15 #ifdef DEBUG 16 #define DBG(fmt, ...) printk(fmt, ##__VA_ARGS__) 17 #else 18 #define DBG(fmt, ...) \ 19 do { \ 20 if (0) \ 21 printk(fmt, ##__VA_ARGS__); \ 22 } while (0) 23 #endif 24 25 #define PCI_PROBE_BIOS 0x0001 26 #define PCI_PROBE_CONF1 0x0002 27 #define PCI_PROBE_CONF2 0x0004 28 #define PCI_PROBE_MMCONF 0x0008 29 #define PCI_PROBE_MASK 0x000f 30 #define PCI_PROBE_NOEARLY 0x0010 31 32 #define PCI_NO_CHECKS 0x0400 33 #define PCI_USE_PIRQ_MASK 0x0800 34 #define PCI_ASSIGN_ROMS 0x1000 35 #define PCI_BIOS_IRQ_SCAN 0x2000 36 #define PCI_ASSIGN_ALL_BUSSES 0x4000 37 #define PCI_CAN_SKIP_ISA_ALIGN 0x8000 38 #define PCI_USE__CRS 0x10000 39 #define PCI_CHECK_ENABLE_AMD_MMCONF 0x20000 40 #define PCI_HAS_IO_ECS 0x40000 41 #define PCI_NOASSIGN_ROMS 0x80000 42 #define PCI_ROOT_NO_CRS 0x100000 43 #define PCI_NOASSIGN_BARS 0x200000 44 #define PCI_BIG_ROOT_WINDOW 0x400000 45 46 extern unsigned int pci_probe; 47 extern unsigned long pirq_table_addr; 48 49 enum pci_bf_sort_state { 50 pci_bf_sort_default, 51 pci_force_nobf, 52 pci_force_bf, 53 pci_dmi_bf, 54 }; 55 56 /* pci-i386.c */ 57 58 void pcibios_resource_survey(void); 59 void pcibios_set_cache_line_size(void); 60 61 /* pci-pc.c */ 62 63 extern int pcibios_last_bus; 64 extern struct pci_ops pci_root_ops; 65 66 void pcibios_scan_specific_bus(int busn); 67 68 /* pci-irq.c */ 69 70 struct irq_info { 71 u8 bus, devfn; /* Bus, device and function */ 72 struct { 73 u8 link; /* IRQ line ID, chipset dependent, 74 0 = not routed */ 75 u16 bitmap; /* Available IRQs */ 76 } __attribute__((packed)) irq[4]; 77 u8 slot; /* Slot number, 0=onboard */ 78 u8 rfu; 79 } __attribute__((packed)); 80 81 struct irq_routing_table { 82 u32 signature; /* PIRQ_SIGNATURE should be here */ 83 u16 version; /* PIRQ_VERSION */ 84 u16 size; /* Table size in bytes */ 85 u8 rtr_bus, rtr_devfn; /* Where the interrupt router lies */ 86 u16 exclusive_irqs; /* IRQs devoted exclusively to 87 PCI usage */ 88 u16 rtr_vendor, rtr_device; /* Vendor and device ID of 89 interrupt router */ 90 u32 miniport_data; /* Crap */ 91 u8 rfu[11]; 92 u8 checksum; /* Modulo 256 checksum must give 0 */ 93 struct irq_info slots[]; 94 } __attribute__((packed)); 95 96 struct irt_routing_table { 97 u32 signature; /* IRT_SIGNATURE should be here */ 98 u8 size; /* Number of entries provided */ 99 u8 used; /* Number of entries actually used */ 100 u16 exclusive_irqs; /* IRQs devoted exclusively to 101 PCI usage */ 102 struct irq_info slots[]; 103 } __attribute__((packed)); 104 105 extern unsigned int pcibios_irq_mask; 106 107 extern raw_spinlock_t pci_config_lock; 108 109 extern int (*pcibios_enable_irq)(struct pci_dev *dev); 110 extern void (*pcibios_disable_irq)(struct pci_dev *dev); 111 112 extern bool mp_should_keep_irq(struct device *dev); 113 114 struct pci_raw_ops { 115 int (*read)(unsigned int domain, unsigned int bus, unsigned int devfn, 116 int reg, int len, u32 *val); 117 int (*write)(unsigned int domain, unsigned int bus, unsigned int devfn, 118 int reg, int len, u32 val); 119 }; 120 121 extern const struct pci_raw_ops *raw_pci_ops; 122 extern const struct pci_raw_ops *raw_pci_ext_ops; 123 124 extern const struct pci_raw_ops pci_mmcfg; 125 extern const struct pci_raw_ops pci_direct_conf1; 126 extern bool port_cf9_safe; 127 128 /* arch_initcall level */ 129 #ifdef CONFIG_PCI_DIRECT 130 extern int pci_direct_probe(void); 131 extern void pci_direct_init(int type); 132 #else 133 static inline int pci_direct_probe(void) { return -1; } 134 static inline void pci_direct_init(int type) { } 135 #endif 136 137 #ifdef CONFIG_PCI_BIOS 138 extern void pci_pcbios_init(void); 139 #else 140 static inline void pci_pcbios_init(void) { } 141 #endif 142 143 extern void __init dmi_check_pciprobe(void); 144 extern void __init dmi_check_skip_isa_align(void); 145 146 /* some common used subsys_initcalls */ 147 #ifdef CONFIG_PCI 148 extern int __init pci_acpi_init(void); 149 #else 150 static inline int __init pci_acpi_init(void) 151 { 152 return -EINVAL; 153 } 154 #endif 155 extern void __init pcibios_irq_init(void); 156 extern int __init pcibios_init(void); 157 extern int pci_legacy_init(void); 158 extern void pcibios_fixup_irqs(void); 159 160 /* pci-mmconfig.c */ 161 162 /* "PCI MMCONFIG %04x [bus %02x-%02x]" */ 163 #define PCI_MMCFG_RESOURCE_NAME_LEN (22 + 4 + 2 + 2) 164 165 struct pci_mmcfg_region { 166 struct list_head list; 167 struct resource res; 168 u64 address; 169 char __iomem *virt; 170 u16 segment; 171 u8 start_bus; 172 u8 end_bus; 173 char name[PCI_MMCFG_RESOURCE_NAME_LEN]; 174 }; 175 176 extern int __init pci_mmcfg_arch_init(void); 177 extern void __init pci_mmcfg_arch_free(void); 178 extern int pci_mmcfg_arch_map(struct pci_mmcfg_region *cfg); 179 extern void pci_mmcfg_arch_unmap(struct pci_mmcfg_region *cfg); 180 extern int pci_mmconfig_insert(struct device *dev, u16 seg, u8 start, u8 end, 181 phys_addr_t addr); 182 extern int pci_mmconfig_delete(u16 seg, u8 start, u8 end); 183 extern struct pci_mmcfg_region *pci_mmconfig_lookup(int segment, int bus); 184 extern struct pci_mmcfg_region *__init pci_mmconfig_add(int segment, int start, 185 int end, u64 addr); 186 187 extern struct list_head pci_mmcfg_list; 188 189 #define PCI_MMCFG_BUS_OFFSET(bus) ((bus) << 20) 190 191 /* 192 * On AMD Fam10h CPUs, all PCI MMIO configuration space accesses must use 193 * %eax. No other source or target registers may be used. The following 194 * mmio_config_* accessors enforce this. See "BIOS and Kernel Developer's 195 * Guide (BKDG) For AMD Family 10h Processors", rev. 3.48, sec 2.11.1, 196 * "MMIO Configuration Coding Requirements". 197 */ 198 static inline unsigned char mmio_config_readb(void __iomem *pos) 199 { 200 u8 val; 201 asm volatile("movb (%1),%%al" : "=a" (val) : "r" (pos)); 202 return val; 203 } 204 205 static inline unsigned short mmio_config_readw(void __iomem *pos) 206 { 207 u16 val; 208 asm volatile("movw (%1),%%ax" : "=a" (val) : "r" (pos)); 209 return val; 210 } 211 212 static inline unsigned int mmio_config_readl(void __iomem *pos) 213 { 214 u32 val; 215 asm volatile("movl (%1),%%eax" : "=a" (val) : "r" (pos)); 216 return val; 217 } 218 219 static inline void mmio_config_writeb(void __iomem *pos, u8 val) 220 { 221 asm volatile("movb %%al,(%1)" : : "a" (val), "r" (pos) : "memory"); 222 } 223 224 static inline void mmio_config_writew(void __iomem *pos, u16 val) 225 { 226 asm volatile("movw %%ax,(%1)" : : "a" (val), "r" (pos) : "memory"); 227 } 228 229 static inline void mmio_config_writel(void __iomem *pos, u32 val) 230 { 231 asm volatile("movl %%eax,(%1)" : : "a" (val), "r" (pos) : "memory"); 232 } 233 234 #ifdef CONFIG_PCI 235 # ifdef CONFIG_ACPI 236 # define x86_default_pci_init pci_acpi_init 237 # else 238 # define x86_default_pci_init pci_legacy_init 239 # endif 240 # define x86_default_pci_init_irq pcibios_irq_init 241 # define x86_default_pci_fixup_irqs pcibios_fixup_irqs 242 #else 243 # define x86_default_pci_init NULL 244 # define x86_default_pci_init_irq NULL 245 # define x86_default_pci_fixup_irqs NULL 246 #endif 247