1 /* SPDX-License-Identifier: GPL-2.0 */ 2 3 #ifndef _ASM_X86_NOSPEC_BRANCH_H_ 4 #define _ASM_X86_NOSPEC_BRANCH_H_ 5 6 #include <linux/static_key.h> 7 #include <linux/objtool.h> 8 #include <linux/linkage.h> 9 10 #include <asm/alternative.h> 11 #include <asm/cpufeatures.h> 12 #include <asm/msr-index.h> 13 #include <asm/unwind_hints.h> 14 #include <asm/percpu.h> 15 #include <asm/ptrace-abi.h> 16 17 /* 18 * Call depth tracking for Intel SKL CPUs to address the RSB underflow 19 * issue in software. 20 * 21 * The tracking does not use a counter. It uses uses arithmetic shift 22 * right on call entry and logical shift left on return. 23 * 24 * The depth tracking variable is initialized to 0x8000.... when the call 25 * depth is zero. The arithmetic shift right sign extends the MSB and 26 * saturates after the 12th call. The shift count is 5 for both directions 27 * so the tracking covers 12 nested calls. 28 * 29 * Call 30 * 0: 0x8000000000000000 0x0000000000000000 31 * 1: 0xfc00000000000000 0xf000000000000000 32 * ... 33 * 11: 0xfffffffffffffff8 0xfffffffffffffc00 34 * 12: 0xffffffffffffffff 0xffffffffffffffe0 35 * 36 * After a return buffer fill the depth is credited 12 calls before the 37 * next stuffing has to take place. 38 * 39 * There is a inaccuracy for situations like this: 40 * 41 * 10 calls 42 * 5 returns 43 * 3 calls 44 * 4 returns 45 * 3 calls 46 * .... 47 * 48 * The shift count might cause this to be off by one in either direction, 49 * but there is still a cushion vs. the RSB depth. The algorithm does not 50 * claim to be perfect and it can be speculated around by the CPU, but it 51 * is considered that it obfuscates the problem enough to make exploitation 52 * extremely difficult. 53 */ 54 #define RET_DEPTH_SHIFT 5 55 #define RSB_RET_STUFF_LOOPS 16 56 #define RET_DEPTH_INIT 0x8000000000000000ULL 57 #define RET_DEPTH_INIT_FROM_CALL 0xfc00000000000000ULL 58 #define RET_DEPTH_CREDIT 0xffffffffffffffffULL 59 60 #ifdef CONFIG_CALL_THUNKS_DEBUG 61 # define CALL_THUNKS_DEBUG_INC_CALLS \ 62 incq PER_CPU_VAR(__x86_call_count); 63 # define CALL_THUNKS_DEBUG_INC_RETS \ 64 incq PER_CPU_VAR(__x86_ret_count); 65 # define CALL_THUNKS_DEBUG_INC_STUFFS \ 66 incq PER_CPU_VAR(__x86_stuffs_count); 67 # define CALL_THUNKS_DEBUG_INC_CTXSW \ 68 incq PER_CPU_VAR(__x86_ctxsw_count); 69 #else 70 # define CALL_THUNKS_DEBUG_INC_CALLS 71 # define CALL_THUNKS_DEBUG_INC_RETS 72 # define CALL_THUNKS_DEBUG_INC_STUFFS 73 # define CALL_THUNKS_DEBUG_INC_CTXSW 74 #endif 75 76 #if defined(CONFIG_MITIGATION_CALL_DEPTH_TRACKING) && !defined(COMPILE_OFFSETS) 77 78 #include <asm/asm-offsets.h> 79 80 #define CREDIT_CALL_DEPTH \ 81 movq $-1, PER_CPU_VAR(__x86_call_depth); 82 83 #define RESET_CALL_DEPTH \ 84 xor %eax, %eax; \ 85 bts $63, %rax; \ 86 movq %rax, PER_CPU_VAR(__x86_call_depth); 87 88 #define RESET_CALL_DEPTH_FROM_CALL \ 89 movb $0xfc, %al; \ 90 shl $56, %rax; \ 91 movq %rax, PER_CPU_VAR(__x86_call_depth); \ 92 CALL_THUNKS_DEBUG_INC_CALLS 93 94 #define INCREMENT_CALL_DEPTH \ 95 sarq $5, PER_CPU_VAR(__x86_call_depth); \ 96 CALL_THUNKS_DEBUG_INC_CALLS 97 98 #else 99 #define CREDIT_CALL_DEPTH 100 #define RESET_CALL_DEPTH 101 #define RESET_CALL_DEPTH_FROM_CALL 102 #define INCREMENT_CALL_DEPTH 103 #endif 104 105 /* 106 * Fill the CPU return stack buffer. 107 * 108 * Each entry in the RSB, if used for a speculative 'ret', contains an 109 * infinite 'pause; lfence; jmp' loop to capture speculative execution. 110 * 111 * This is required in various cases for retpoline and IBRS-based 112 * mitigations for the Spectre variant 2 vulnerability. Sometimes to 113 * eliminate potentially bogus entries from the RSB, and sometimes 114 * purely to ensure that it doesn't get empty, which on some CPUs would 115 * allow predictions from other (unwanted!) sources to be used. 116 * 117 * We define a CPP macro such that it can be used from both .S files and 118 * inline assembly. It's possible to do a .macro and then include that 119 * from C via asm(".include <asm/nospec-branch.h>") but let's not go there. 120 */ 121 122 #define RETPOLINE_THUNK_SIZE 32 123 #define RSB_CLEAR_LOOPS 32 /* To forcibly overwrite all entries */ 124 125 /* 126 * Common helper for __FILL_RETURN_BUFFER and __FILL_ONE_RETURN. 127 */ 128 #define __FILL_RETURN_SLOT \ 129 ANNOTATE_INTRA_FUNCTION_CALL; \ 130 call 772f; \ 131 int3; \ 132 772: 133 134 /* 135 * Stuff the entire RSB. 136 * 137 * Google experimented with loop-unrolling and this turned out to be 138 * the optimal version - two calls, each with their own speculation 139 * trap should their return address end up getting used, in a loop. 140 */ 141 #ifdef CONFIG_X86_64 142 #define __FILL_RETURN_BUFFER(reg, nr) \ 143 mov $(nr/2), reg; \ 144 771: \ 145 __FILL_RETURN_SLOT \ 146 __FILL_RETURN_SLOT \ 147 add $(BITS_PER_LONG/8) * 2, %_ASM_SP; \ 148 dec reg; \ 149 jnz 771b; \ 150 /* barrier for jnz misprediction */ \ 151 lfence; \ 152 CREDIT_CALL_DEPTH \ 153 CALL_THUNKS_DEBUG_INC_CTXSW 154 #else 155 /* 156 * i386 doesn't unconditionally have LFENCE, as such it can't 157 * do a loop. 158 */ 159 #define __FILL_RETURN_BUFFER(reg, nr) \ 160 .rept nr; \ 161 __FILL_RETURN_SLOT; \ 162 .endr; \ 163 add $(BITS_PER_LONG/8) * nr, %_ASM_SP; 164 #endif 165 166 /* 167 * Stuff a single RSB slot. 168 * 169 * To mitigate Post-Barrier RSB speculation, one CALL instruction must be 170 * forced to retire before letting a RET instruction execute. 171 * 172 * On PBRSB-vulnerable CPUs, it is not safe for a RET to be executed 173 * before this point. 174 */ 175 #define __FILL_ONE_RETURN \ 176 __FILL_RETURN_SLOT \ 177 add $(BITS_PER_LONG/8), %_ASM_SP; \ 178 lfence; 179 180 /* 181 * Helper for detecting if an interrupt occurred at an unsafe location within 182 * Safe-RET. If Safe-RET is interrupted after the CALL or LEA the RSB may get 183 * poisoned by the interrupt handler. 184 * 185 * The Safe-RET sequence is: 186 * 187 * CALL 188 * LEA 8(%RSP), %RSP 189 * RET 190 * 191 * The two CMPs below check whether RIP points to after the CALL or after the 192 * LEA. 193 * 194 * The LFENCE below is to address this particular speculation case: 195 * 196 * 1. Userspace runs and poisons the BTB around the safe-RET routine 197 * 198 * 2. Userspace triggers some kind of exception 199 * 200 * 3. Kernel executes error_entry() and mis-speculates the branch into thinking 201 * it actually came from kernel space 202 * 203 * 4. The kernel then further mis-speculates that the exception occurred due 204 * to an interrupted safe-RET 205 * 206 * 5. The handle_interrupted_saferet() routine speculatively executes and 207 * speculatively does a safe-RET. But this is unsafe since it was never 208 * untrained. 209 * 210 * The LFENCE fixes this by ensuring step 5 is never reached speculatively. 211 * Note that this LFENCE only occurs if safe-RET was actually interrupted (so 212 * it's outside of the normal path). 213 */ 214 #define __HANDLE_INTR_SAFERET(name, pt_regs) \ 215 cmpq $(name), RIP+pt_regs; \ 216 jb 1f; \ 217 cmpq $(name)+5, RIP+pt_regs; \ 218 ja 1f; \ 219 lfence; \ 220 leaq pt_regs, %rdi; \ 221 call handle_interrupted_saferet; \ 222 1: 223 224 #ifdef __ASSEMBLER__ 225 226 /* 227 * (ab)use RETPOLINE_SAFE on RET to annotate away 'bare' RET instructions 228 * vs RETBleed validation. 229 */ 230 #define ANNOTATE_UNRET_SAFE ANNOTATE_RETPOLINE_SAFE 231 232 /* 233 * Abuse ANNOTATE_RETPOLINE_SAFE on a NOP to indicate UNRET_END, should 234 * eventually turn into its own annotation. 235 */ 236 .macro VALIDATE_UNRET_END 237 #if defined(CONFIG_NOINSTR_VALIDATION) && \ 238 (defined(CONFIG_MITIGATION_UNRET_ENTRY) || defined(CONFIG_MITIGATION_SRSO)) 239 ANNOTATE_RETPOLINE_SAFE 240 nop 241 #endif 242 .endm 243 244 /* 245 * Emits a conditional CS prefix that is compatible with 246 * -mindirect-branch-cs-prefix. 247 */ 248 .macro __CS_PREFIX reg:req 249 .irp rs,r8,r9,r10,r11,r12,r13,r14,r15 250 .ifc \reg,\rs 251 .byte 0x2e 252 .endif 253 .endr 254 .endm 255 256 /* 257 * JMP_NOSPEC and CALL_NOSPEC macros can be used instead of a simple 258 * indirect jmp/call which may be susceptible to the Spectre variant 2 259 * attack. 260 * 261 * NOTE: these do not take kCFI into account and are thus not comparable to C 262 * indirect calls, take care when using. The target of these should be an ENDBR 263 * instruction irrespective of kCFI. 264 */ 265 .macro JMP_NOSPEC reg:req 266 #ifdef CONFIG_MITIGATION_RETPOLINE 267 __CS_PREFIX \reg 268 jmp __x86_indirect_thunk_\reg 269 #else 270 jmp *%\reg 271 int3 272 #endif 273 .endm 274 275 .macro CALL_NOSPEC reg:req 276 #ifdef CONFIG_MITIGATION_RETPOLINE 277 __CS_PREFIX \reg 278 call __x86_indirect_thunk_\reg 279 #else 280 call *%\reg 281 #endif 282 .endm 283 284 /* 285 * A simpler FILL_RETURN_BUFFER macro. Don't make people use the CPP 286 * monstrosity above, manually. 287 */ 288 .macro FILL_RETURN_BUFFER reg:req nr:req ftr:req ftr2=ALT_NOT(X86_FEATURE_ALWAYS) 289 ALTERNATIVE_2 "jmp .Lskip_rsb_\@", \ 290 __stringify(__FILL_RETURN_BUFFER(\reg,\nr)), \ftr, \ 291 __stringify(nop;nop;__FILL_ONE_RETURN), \ftr2 292 293 .Lskip_rsb_\@: 294 .endm 295 296 /* 297 * The CALL to srso_alias_untrain_ret() must be patched in directly at 298 * the spot where untraining must be done, ie., srso_alias_untrain_ret() 299 * must be the target of a CALL instruction instead of indirectly 300 * jumping to a wrapper which then calls it. Therefore, this macro is 301 * called outside of __UNTRAIN_RET below, for the time being, before the 302 * kernel can support nested alternatives with arbitrary nesting. 303 */ 304 .macro CALL_UNTRAIN_RET 305 #if defined(CONFIG_MITIGATION_UNRET_ENTRY) || defined(CONFIG_MITIGATION_SRSO) 306 ALTERNATIVE_2 "", "call entry_untrain_ret", X86_FEATURE_UNRET, \ 307 "call srso_alias_untrain_ret", X86_FEATURE_SRSO_ALIAS 308 #endif 309 .endm 310 311 /* 312 * Mitigate RETBleed for AMD/Hygon Zen uarch. Requires KERNEL CR3 because the 313 * return thunk isn't mapped into the userspace tables (then again, AMD 314 * typically has NO_MELTDOWN). 315 * 316 * While retbleed_untrain_ret() doesn't clobber anything but requires stack, 317 * write_ibpb() will clobber AX, CX, DX. 318 * 319 * As such, this must be placed after every *SWITCH_TO_KERNEL_CR3 at a point 320 * where we have a stack but before any RET instruction. 321 */ 322 .macro __UNTRAIN_RET ibpb_feature, call_depth_insns 323 #if defined(CONFIG_MITIGATION_RETHUNK) || defined(CONFIG_MITIGATION_IBPB_ENTRY) 324 VALIDATE_UNRET_END 325 CALL_UNTRAIN_RET 326 ALTERNATIVE_2 "", \ 327 "call write_ibpb", \ibpb_feature, \ 328 __stringify(\call_depth_insns), X86_FEATURE_CALL_DEPTH 329 #endif 330 .endm 331 332 #define UNTRAIN_RET \ 333 __UNTRAIN_RET X86_FEATURE_ENTRY_IBPB, __stringify(RESET_CALL_DEPTH) 334 335 #define UNTRAIN_RET_VM \ 336 __UNTRAIN_RET X86_FEATURE_IBPB_ON_VMEXIT, __stringify(RESET_CALL_DEPTH) 337 338 #define UNTRAIN_RET_FROM_CALL \ 339 __UNTRAIN_RET X86_FEATURE_ENTRY_IBPB, __stringify(RESET_CALL_DEPTH_FROM_CALL) 340 341 .macro HANDLE_INTR_SAFERET pt_regs 342 #ifdef CONFIG_MITIGATION_SRSO 343 ALTERNATIVE_2 "", \ 344 __stringify(__HANDLE_INTR_SAFERET(srso_safe_ret, \pt_regs)), X86_FEATURE_SRSO, \ 345 __stringify(__HANDLE_INTR_SAFERET(srso_alias_safe_ret, \pt_regs)), X86_FEATURE_SRSO_ALIAS 346 347 #endif 348 .endm 349 350 .macro CALL_DEPTH_ACCOUNT 351 #ifdef CONFIG_MITIGATION_CALL_DEPTH_TRACKING 352 ALTERNATIVE "", \ 353 __stringify(INCREMENT_CALL_DEPTH), X86_FEATURE_CALL_DEPTH 354 #endif 355 .endm 356 357 /* 358 * Macro to execute VERW insns that mitigate transient data sampling 359 * attacks such as MDS or TSA. On affected systems a microcode update 360 * overloaded VERW insns to also clear the CPU buffers. VERW clobbers 361 * CFLAGS.ZF. 362 * Note: Only the memory operand variant of VERW clears the CPU buffers. 363 */ 364 #ifdef CONFIG_X86_64 365 #define VERW verw x86_verw_sel(%rip) 366 #else 367 /* 368 * In 32bit mode, the memory operand must be a %cs reference. The data segments 369 * may not be usable (vm86 mode), and the stack segment may not be flat (ESPFIX32). 370 */ 371 #define VERW verw %cs:x86_verw_sel 372 #endif 373 374 /* 375 * Provide a stringified VERW macro for simple usage, and a non-stringified 376 * VERW macro for use in more elaborate sequences, e.g. to encode a conditional 377 * VERW within an ALTERNATIVE. 378 */ 379 #define __CLEAR_CPU_BUFFERS __stringify(VERW) 380 381 /* If necessary, emit VERW on exit-to-userspace to clear CPU buffers. */ 382 #define CLEAR_CPU_BUFFERS \ 383 ALTERNATIVE "", __CLEAR_CPU_BUFFERS, X86_FEATURE_CLEAR_CPU_BUF 384 385 #ifdef CONFIG_X86_64 386 .macro CLEAR_BRANCH_HISTORY 387 ALTERNATIVE "", "call clear_bhb_loop", X86_FEATURE_CLEAR_BHB_LOOP 388 .endm 389 390 .macro CLEAR_BRANCH_HISTORY_VMEXIT 391 ALTERNATIVE "", "call clear_bhb_loop", X86_FEATURE_CLEAR_BHB_VMEXIT 392 .endm 393 #else 394 #define CLEAR_BRANCH_HISTORY 395 #define CLEAR_BRANCH_HISTORY_VMEXIT 396 #endif 397 398 #else /* __ASSEMBLER__ */ 399 400 #define ITS_THUNK_SIZE 64 401 402 typedef u8 retpoline_thunk_t[RETPOLINE_THUNK_SIZE]; 403 typedef u8 its_thunk_t[ITS_THUNK_SIZE]; 404 extern retpoline_thunk_t __x86_indirect_thunk_array[]; 405 extern retpoline_thunk_t __x86_indirect_call_thunk_array[]; 406 extern retpoline_thunk_t __x86_indirect_jump_thunk_array[]; 407 extern its_thunk_t __x86_indirect_its_thunk_array[]; 408 409 #ifdef CONFIG_MITIGATION_RETHUNK 410 extern void __x86_return_thunk(void); 411 #else 412 static inline void __x86_return_thunk(void) {} 413 #endif 414 415 #ifdef CONFIG_MITIGATION_UNRET_ENTRY 416 extern void retbleed_return_thunk(void); 417 #else 418 static inline void retbleed_return_thunk(void) {} 419 #endif 420 421 extern void srso_alias_untrain_ret(void); 422 423 #ifdef CONFIG_MITIGATION_SRSO 424 extern void srso_return_thunk(void); 425 extern void srso_alias_return_thunk(void); 426 #else 427 static inline void srso_return_thunk(void) {} 428 static inline void srso_alias_return_thunk(void) {} 429 #endif 430 431 #ifdef CONFIG_MITIGATION_ITS 432 extern void its_return_thunk(void); 433 #else 434 static inline void its_return_thunk(void) {} 435 #endif 436 437 extern void retbleed_return_thunk(void); 438 extern void srso_return_thunk(void); 439 extern void srso_alias_return_thunk(void); 440 441 extern void entry_untrain_ret(void); 442 extern void write_ibpb(void); 443 444 #ifdef CONFIG_BPF_JIT 445 extern void bpf_arch_ibpb(void); 446 #endif 447 448 #ifdef CONFIG_X86_64 449 extern void clear_bhb_loop(void); 450 #endif 451 452 extern void (*x86_return_thunk)(void); 453 454 extern void __warn_thunk(void); 455 456 #ifdef CONFIG_MITIGATION_CALL_DEPTH_TRACKING 457 extern void call_depth_return_thunk(void); 458 459 #define CALL_DEPTH_ACCOUNT \ 460 ALTERNATIVE("", \ 461 __stringify(INCREMENT_CALL_DEPTH), \ 462 X86_FEATURE_CALL_DEPTH) 463 464 DECLARE_PER_CPU_CACHE_HOT(u64, __x86_call_depth); 465 466 #ifdef CONFIG_CALL_THUNKS_DEBUG 467 DECLARE_PER_CPU(u64, __x86_call_count); 468 DECLARE_PER_CPU(u64, __x86_ret_count); 469 DECLARE_PER_CPU(u64, __x86_stuffs_count); 470 DECLARE_PER_CPU(u64, __x86_ctxsw_count); 471 #endif 472 #else /* !CONFIG_MITIGATION_CALL_DEPTH_TRACKING */ 473 474 static inline void call_depth_return_thunk(void) {} 475 #define CALL_DEPTH_ACCOUNT "" 476 477 #endif /* CONFIG_MITIGATION_CALL_DEPTH_TRACKING */ 478 479 #ifdef CONFIG_MITIGATION_RETPOLINE 480 481 #define GEN(reg) \ 482 extern retpoline_thunk_t __x86_indirect_thunk_ ## reg; 483 #include <asm/GEN-for-each-reg.h> 484 #undef GEN 485 486 #define GEN(reg) \ 487 extern retpoline_thunk_t __x86_indirect_call_thunk_ ## reg; 488 #include <asm/GEN-for-each-reg.h> 489 #undef GEN 490 491 #define GEN(reg) \ 492 extern retpoline_thunk_t __x86_indirect_jump_thunk_ ## reg; 493 #include <asm/GEN-for-each-reg.h> 494 #undef GEN 495 496 #ifdef CONFIG_X86_64 497 498 /* 499 * Emits a conditional CS prefix that is compatible with 500 * -mindirect-branch-cs-prefix. 501 */ 502 #define __CS_PREFIX(reg) \ 503 ".irp rs,r8,r9,r10,r11,r12,r13,r14,r15\n" \ 504 ".ifc \\rs," reg "\n" \ 505 ".byte 0x2e\n" \ 506 ".endif\n" \ 507 ".endr\n" 508 509 /* 510 * Inline asm uses the %V modifier which is only in newer GCC 511 * which is ensured when CONFIG_MITIGATION_RETPOLINE is defined. 512 */ 513 #define CALL_NOSPEC __CS_PREFIX("%V[thunk_target]") \ 514 "call __x86_indirect_thunk_%V[thunk_target]\n" 515 516 # define THUNK_TARGET(addr) [thunk_target] "r" (addr) 517 518 #else /* CONFIG_X86_32 */ 519 /* 520 * For i386 we use the original ret-equivalent retpoline, because 521 * otherwise we'll run out of registers. We don't care about CET 522 * here, anyway. 523 */ 524 # define CALL_NOSPEC \ 525 ALTERNATIVE_2( \ 526 ANNOTATE_RETPOLINE_SAFE "\n" \ 527 "call *%[thunk_target]\n", \ 528 " jmp 904f;\n" \ 529 " .align 16\n" \ 530 "901: call 903f;\n" \ 531 "902: pause;\n" \ 532 " lfence;\n" \ 533 " jmp 902b;\n" \ 534 " .align 16\n" \ 535 "903: lea 4(%%esp), %%esp;\n" \ 536 " pushl %[thunk_target];\n" \ 537 " ret;\n" \ 538 " .align 16\n" \ 539 "904: call 901b;\n", \ 540 X86_FEATURE_RETPOLINE, \ 541 "lfence;\n" \ 542 ANNOTATE_RETPOLINE_SAFE "\n" \ 543 "call *%[thunk_target]\n", \ 544 X86_FEATURE_RETPOLINE_LFENCE) 545 546 # define THUNK_TARGET(addr) [thunk_target] "rm" (addr) 547 #endif 548 #else /* No retpoline for C / inline asm */ 549 # define CALL_NOSPEC "call *%[thunk_target]\n" 550 # define THUNK_TARGET(addr) [thunk_target] "rm" (addr) 551 #endif 552 553 /* The Spectre V2 mitigation variants */ 554 enum spectre_v2_mitigation { 555 SPECTRE_V2_NONE, 556 SPECTRE_V2_RETPOLINE, 557 SPECTRE_V2_LFENCE, 558 SPECTRE_V2_EIBRS, 559 SPECTRE_V2_EIBRS_RETPOLINE, 560 SPECTRE_V2_EIBRS_LFENCE, 561 SPECTRE_V2_IBRS, 562 }; 563 564 /* The indirect branch speculation control variants */ 565 enum spectre_v2_user_mitigation { 566 SPECTRE_V2_USER_NONE, 567 SPECTRE_V2_USER_STRICT, 568 SPECTRE_V2_USER_STRICT_PREFERRED, 569 SPECTRE_V2_USER_PRCTL, 570 SPECTRE_V2_USER_SECCOMP, 571 }; 572 573 /* The Speculative Store Bypass disable variants */ 574 enum ssb_mitigation { 575 SPEC_STORE_BYPASS_NONE, 576 SPEC_STORE_BYPASS_AUTO, 577 SPEC_STORE_BYPASS_DISABLE, 578 SPEC_STORE_BYPASS_PRCTL, 579 SPEC_STORE_BYPASS_SECCOMP, 580 }; 581 582 static __always_inline 583 void alternative_msr_write(unsigned int msr, u64 val, unsigned int feature) 584 { 585 asm volatile(ALTERNATIVE("", "wrmsr", %c[feature]) 586 : : "c" (msr), 587 "a" ((u32)val), 588 "d" ((u32)(val >> 32)), 589 [feature] "i" (feature) 590 : "memory"); 591 } 592 593 DECLARE_PER_CPU(bool, x86_ibpb_exit_to_user); 594 595 static inline void indirect_branch_prediction_barrier(void) 596 { 597 asm_inline volatile(ALTERNATIVE("", "call write_ibpb", X86_FEATURE_IBPB) 598 : ASM_CALL_CONSTRAINT 599 :: "rax", "rcx", "rdx", "memory"); 600 } 601 602 /* The Intel SPEC CTRL MSR base value cache */ 603 extern u64 x86_spec_ctrl_base; 604 DECLARE_PER_CPU(u64, x86_spec_ctrl_current); 605 extern void update_spec_ctrl_cond(u64 val); 606 extern u64 spec_ctrl_current(void); 607 608 /* 609 * With retpoline, we must use IBRS to restrict branch prediction 610 * before calling into firmware. 611 * 612 * (Implemented as CPP macros due to header hell.) 613 */ 614 #define firmware_restrict_branch_speculation_start() \ 615 do { \ 616 preempt_disable(); \ 617 alternative_msr_write(MSR_IA32_SPEC_CTRL, \ 618 spec_ctrl_current() | SPEC_CTRL_IBRS, \ 619 X86_FEATURE_USE_IBRS_FW); \ 620 alternative_msr_write(MSR_IA32_PRED_CMD, PRED_CMD_IBPB, \ 621 X86_FEATURE_USE_IBPB_FW); \ 622 } while (0) 623 624 #define firmware_restrict_branch_speculation_end() \ 625 do { \ 626 alternative_msr_write(MSR_IA32_SPEC_CTRL, \ 627 spec_ctrl_current(), \ 628 X86_FEATURE_USE_IBRS_FW); \ 629 preempt_enable(); \ 630 } while (0) 631 632 DECLARE_STATIC_KEY_FALSE(switch_to_cond_stibp); 633 DECLARE_STATIC_KEY_FALSE(switch_mm_cond_ibpb); 634 DECLARE_STATIC_KEY_FALSE(switch_mm_always_ibpb); 635 636 DECLARE_STATIC_KEY_FALSE(switch_vcpu_ibpb); 637 638 DECLARE_STATIC_KEY_FALSE(cpu_buf_idle_clear); 639 640 DECLARE_STATIC_KEY_FALSE(switch_mm_cond_l1d_flush); 641 642 extern u16 x86_verw_sel; 643 644 #include <asm/segment.h> 645 646 /** 647 * x86_clear_cpu_buffers - Buffer clearing support for different x86 CPU vulns 648 * 649 * This uses the otherwise unused and obsolete VERW instruction in 650 * combination with microcode which triggers a CPU buffer flush when the 651 * instruction is executed. 652 */ 653 static __always_inline void x86_clear_cpu_buffers(void) 654 { 655 static const u16 ds = __KERNEL_DS; 656 657 /* 658 * Has to be the memory-operand variant because only that 659 * guarantees the CPU buffer flush functionality according to 660 * documentation. The register-operand variant does not. 661 * Works with any segment selector, but a valid writable 662 * data segment is the fastest variant. 663 * 664 * "cc" clobber is required because VERW modifies ZF. 665 */ 666 asm volatile("verw %[ds]" : : [ds] "m" (ds) : "cc"); 667 } 668 669 /** 670 * x86_idle_clear_cpu_buffers - Buffer clearing support in idle for the MDS 671 * and TSA vulnerabilities. 672 * 673 * Clear CPU buffers if the corresponding static key is enabled 674 */ 675 static __always_inline void x86_idle_clear_cpu_buffers(void) 676 { 677 if (static_branch_likely(&cpu_buf_idle_clear)) 678 x86_clear_cpu_buffers(); 679 } 680 681 void srso_safe_ret(void); 682 void srso_alias_safe_ret(void); 683 void handle_interrupted_saferet(struct pt_regs *regs); 684 685 #endif /* __ASSEMBLER__ */ 686 687 #endif /* _ASM_X86_NOSPEC_BRANCH_H_ */ 688