1 #ifndef _ASM_X86_MWAIT_H 2 #define _ASM_X86_MWAIT_H 3 4 #include <linux/sched.h> 5 #include <linux/sched/idle.h> 6 7 #include <asm/cpufeature.h> 8 9 #define MWAIT_SUBSTATE_MASK 0xf 10 #define MWAIT_CSTATE_MASK 0xf 11 #define MWAIT_SUBSTATE_SIZE 4 12 #define MWAIT_HINT2CSTATE(hint) (((hint) >> MWAIT_SUBSTATE_SIZE) & MWAIT_CSTATE_MASK) 13 #define MWAIT_HINT2SUBSTATE(hint) ((hint) & MWAIT_CSTATE_MASK) 14 15 #define CPUID_MWAIT_LEAF 5 16 #define CPUID5_ECX_EXTENSIONS_SUPPORTED 0x1 17 #define CPUID5_ECX_INTERRUPT_BREAK 0x2 18 19 #define MWAIT_ECX_INTERRUPT_BREAK 0x1 20 #define MWAITX_ECX_TIMER_ENABLE BIT(1) 21 #define MWAITX_MAX_LOOPS ((u32)-1) 22 #define MWAITX_DISABLE_CSTATES 0xf 23 24 static inline void __monitor(const void *eax, unsigned long ecx, 25 unsigned long edx) 26 { 27 /* "monitor %eax, %ecx, %edx;" */ 28 asm volatile(".byte 0x0f, 0x01, 0xc8;" 29 :: "a" (eax), "c" (ecx), "d"(edx)); 30 } 31 32 static inline void __monitorx(const void *eax, unsigned long ecx, 33 unsigned long edx) 34 { 35 /* "monitorx %eax, %ecx, %edx;" */ 36 asm volatile(".byte 0x0f, 0x01, 0xfa;" 37 :: "a" (eax), "c" (ecx), "d"(edx)); 38 } 39 40 static inline void __mwait(unsigned long eax, unsigned long ecx) 41 { 42 /* "mwait %eax, %ecx;" */ 43 asm volatile(".byte 0x0f, 0x01, 0xc9;" 44 :: "a" (eax), "c" (ecx)); 45 } 46 47 /* 48 * MWAITX allows for a timer expiration to get the core out a wait state in 49 * addition to the default MWAIT exit condition of a store appearing at a 50 * monitored virtual address. 51 * 52 * Registers: 53 * 54 * MWAITX ECX[1]: enable timer if set 55 * MWAITX EBX[31:0]: max wait time expressed in SW P0 clocks. The software P0 56 * frequency is the same as the TSC frequency. 57 * 58 * Below is a comparison between MWAIT and MWAITX on AMD processors: 59 * 60 * MWAIT MWAITX 61 * opcode 0f 01 c9 | 0f 01 fb 62 * ECX[0] value of RFLAGS.IF seen by instruction 63 * ECX[1] unused/#GP if set | enable timer if set 64 * ECX[31:2] unused/#GP if set 65 * EAX unused (reserve for hint) 66 * EBX[31:0] unused | max wait time (P0 clocks) 67 * 68 * MONITOR MONITORX 69 * opcode 0f 01 c8 | 0f 01 fa 70 * EAX (logical) address to monitor 71 * ECX #GP if not zero 72 */ 73 static inline void __mwaitx(unsigned long eax, unsigned long ebx, 74 unsigned long ecx) 75 { 76 /* "mwaitx %eax, %ebx, %ecx;" */ 77 asm volatile(".byte 0x0f, 0x01, 0xfb;" 78 :: "a" (eax), "b" (ebx), "c" (ecx)); 79 } 80 81 static inline void __sti_mwait(unsigned long eax, unsigned long ecx) 82 { 83 trace_hardirqs_on(); 84 /* "mwait %eax, %ecx;" */ 85 asm volatile("sti; .byte 0x0f, 0x01, 0xc9;" 86 :: "a" (eax), "c" (ecx)); 87 } 88 89 /* 90 * This uses new MONITOR/MWAIT instructions on P4 processors with PNI, 91 * which can obviate IPI to trigger checking of need_resched. 92 * We execute MONITOR against need_resched and enter optimized wait state 93 * through MWAIT. Whenever someone changes need_resched, we would be woken 94 * up from MWAIT (without an IPI). 95 * 96 * New with Core Duo processors, MWAIT can take some hints based on CPU 97 * capability. 98 */ 99 static inline void mwait_idle_with_hints(unsigned long eax, unsigned long ecx) 100 { 101 if (static_cpu_has_bug(X86_BUG_MONITOR) || !current_set_polling_and_test()) { 102 if (static_cpu_has_bug(X86_BUG_CLFLUSH_MONITOR)) { 103 mb(); 104 clflush((void *)¤t_thread_info()->flags); 105 mb(); 106 } 107 108 __monitor((void *)¤t_thread_info()->flags, 0, 0); 109 if (!need_resched()) 110 __mwait(eax, ecx); 111 } 112 current_clr_polling(); 113 } 114 115 #endif /* _ASM_X86_MWAIT_H */ 116