1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _ASM_X86_MWAIT_H 3 #define _ASM_X86_MWAIT_H 4 5 #include <linux/sched.h> 6 #include <linux/sched/idle.h> 7 8 #include <asm/cpufeature.h> 9 #include <asm/nospec-branch.h> 10 11 #define MWAIT_SUBSTATE_MASK 0xf 12 #define MWAIT_CSTATE_MASK 0xf 13 #define MWAIT_SUBSTATE_SIZE 4 14 #define MWAIT_HINT2CSTATE(hint) (((hint) >> MWAIT_SUBSTATE_SIZE) & MWAIT_CSTATE_MASK) 15 #define MWAIT_HINT2SUBSTATE(hint) ((hint) & MWAIT_CSTATE_MASK) 16 #define MWAIT_C1_SUBSTATE_MASK 0xf0 17 18 #define CPUID5_ECX_EXTENSIONS_SUPPORTED 0x1 19 #define CPUID5_ECX_INTERRUPT_BREAK 0x2 20 21 #define MWAIT_ECX_INTERRUPT_BREAK 0x1 22 #define MWAITX_ECX_TIMER_ENABLE BIT(1) 23 #define MWAITX_MAX_WAIT_CYCLES UINT_MAX 24 #define MWAITX_DISABLE_CSTATES 0xf0 25 #define TPAUSE_C01_STATE 1 26 #define TPAUSE_C02_STATE 0 27 28 static __always_inline void __monitor(const void *eax, u32 ecx, u32 edx) 29 { 30 /* 31 * Use the instruction mnemonic with implicit operands, as the LLVM 32 * assembler fails to assemble the mnemonic with explicit operands: 33 */ 34 asm volatile("monitor" :: "a" (eax), "c" (ecx), "d" (edx)); 35 } 36 37 static __always_inline void __monitorx(const void *eax, u32 ecx, u32 edx) 38 { 39 /* "monitorx %eax, %ecx, %edx" */ 40 asm volatile(".byte 0x0f, 0x01, 0xfa" 41 :: "a" (eax), "c" (ecx), "d"(edx)); 42 } 43 44 static __always_inline void __mwait(u32 eax, u32 ecx) 45 { 46 mds_idle_clear_cpu_buffers(); 47 48 /* 49 * Use the instruction mnemonic with implicit operands, as the LLVM 50 * assembler fails to assemble the mnemonic with explicit operands: 51 */ 52 asm volatile("mwait" :: "a" (eax), "c" (ecx)); 53 } 54 55 /* 56 * MWAITX allows for a timer expiration to get the core out a wait state in 57 * addition to the default MWAIT exit condition of a store appearing at a 58 * monitored virtual address. 59 * 60 * Registers: 61 * 62 * MWAITX ECX[1]: enable timer if set 63 * MWAITX EBX[31:0]: max wait time expressed in SW P0 clocks. The software P0 64 * frequency is the same as the TSC frequency. 65 * 66 * Below is a comparison between MWAIT and MWAITX on AMD processors: 67 * 68 * MWAIT MWAITX 69 * opcode 0f 01 c9 | 0f 01 fb 70 * ECX[0] value of RFLAGS.IF seen by instruction 71 * ECX[1] unused/#GP if set | enable timer if set 72 * ECX[31:2] unused/#GP if set 73 * EAX unused (reserve for hint) 74 * EBX[31:0] unused | max wait time (P0 clocks) 75 * 76 * MONITOR MONITORX 77 * opcode 0f 01 c8 | 0f 01 fa 78 * EAX (logical) address to monitor 79 * ECX #GP if not zero 80 */ 81 static __always_inline void __mwaitx(u32 eax, u32 ebx, u32 ecx) 82 { 83 /* No MDS buffer clear as this is AMD/HYGON only */ 84 85 /* "mwaitx %eax, %ebx, %ecx" */ 86 asm volatile(".byte 0x0f, 0x01, 0xfb" 87 :: "a" (eax), "b" (ebx), "c" (ecx)); 88 } 89 90 /* 91 * Re-enable interrupts right upon calling mwait in such a way that 92 * no interrupt can fire _before_ the execution of mwait, ie: no 93 * instruction must be placed between "sti" and "mwait". 94 * 95 * This is necessary because if an interrupt queues a timer before 96 * executing mwait, it would otherwise go unnoticed and the next tick 97 * would not be reprogrammed accordingly before mwait ever wakes up. 98 */ 99 static __always_inline void __sti_mwait(u32 eax, u32 ecx) 100 { 101 mds_idle_clear_cpu_buffers(); 102 103 asm volatile("sti; mwait" :: "a" (eax), "c" (ecx)); 104 } 105 106 /* 107 * This uses new MONITOR/MWAIT instructions on P4 processors with PNI, 108 * which can obviate IPI to trigger checking of need_resched. 109 * We execute MONITOR against need_resched and enter optimized wait state 110 * through MWAIT. Whenever someone changes need_resched, we would be woken 111 * up from MWAIT (without an IPI). 112 * 113 * New with Core Duo processors, MWAIT can take some hints based on CPU 114 * capability. 115 */ 116 static __always_inline void mwait_idle_with_hints(u32 eax, u32 ecx) 117 { 118 if (static_cpu_has_bug(X86_BUG_MONITOR) || !current_set_polling_and_test()) { 119 const void *addr = ¤t_thread_info()->flags; 120 121 alternative_input("", "clflush (%[addr])", X86_BUG_CLFLUSH_MONITOR, [addr] "a" (addr)); 122 __monitor(addr, 0, 0); 123 124 if (!need_resched()) { 125 if (ecx & 1) { 126 __mwait(eax, ecx); 127 } else { 128 __sti_mwait(eax, ecx); 129 raw_local_irq_disable(); 130 } 131 } 132 } 133 current_clr_polling(); 134 } 135 136 /* 137 * Caller can specify whether to enter C0.1 (low latency, less 138 * power saving) or C0.2 state (saves more power, but longer wakeup 139 * latency). This may be overridden by the IA32_UMWAIT_CONTROL MSR 140 * which can force requests for C0.2 to be downgraded to C0.1. 141 */ 142 static inline void __tpause(u32 ecx, u32 edx, u32 eax) 143 { 144 /* "tpause %ecx" */ 145 asm volatile(".byte 0x66, 0x0f, 0xae, 0xf1" 146 :: "c" (ecx), "d" (edx), "a" (eax)); 147 } 148 149 #endif /* _ASM_X86_MWAIT_H */ 150