1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _ASM_X86_MSR_H 3 #define _ASM_X86_MSR_H 4 5 #include "msr-index.h" 6 7 #ifndef __ASSEMBLY__ 8 9 #include <asm/asm.h> 10 #include <asm/errno.h> 11 #include <asm/cpumask.h> 12 #include <uapi/asm/msr.h> 13 #include <asm/shared/msr.h> 14 15 struct msr_info { 16 u32 msr_no; 17 struct msr reg; 18 struct msr *msrs; 19 int err; 20 }; 21 22 struct msr_regs_info { 23 u32 *regs; 24 int err; 25 }; 26 27 struct saved_msr { 28 bool valid; 29 struct msr_info info; 30 }; 31 32 struct saved_msrs { 33 unsigned int num; 34 struct saved_msr *array; 35 }; 36 37 /* 38 * both i386 and x86_64 returns 64-bit value in edx:eax, but gcc's "A" 39 * constraint has different meanings. For i386, "A" means exactly 40 * edx:eax, while for x86_64 it doesn't mean rdx:rax or edx:eax. Instead, 41 * it means rax *or* rdx. 42 */ 43 #ifdef CONFIG_X86_64 44 /* Using 64-bit values saves one instruction clearing the high half of low */ 45 #define DECLARE_ARGS(val, low, high) unsigned long low, high 46 #define EAX_EDX_VAL(val, low, high) ((low) | (high) << 32) 47 #define EAX_EDX_RET(val, low, high) "=a" (low), "=d" (high) 48 #else 49 #define DECLARE_ARGS(val, low, high) unsigned long long val 50 #define EAX_EDX_VAL(val, low, high) (val) 51 #define EAX_EDX_RET(val, low, high) "=A" (val) 52 #endif 53 54 /* 55 * Be very careful with includes. This header is prone to include loops. 56 */ 57 #include <asm/atomic.h> 58 #include <linux/tracepoint-defs.h> 59 60 #ifdef CONFIG_TRACEPOINTS 61 DECLARE_TRACEPOINT(read_msr); 62 DECLARE_TRACEPOINT(write_msr); 63 DECLARE_TRACEPOINT(rdpmc); 64 extern void do_trace_write_msr(unsigned int msr, u64 val, int failed); 65 extern void do_trace_read_msr(unsigned int msr, u64 val, int failed); 66 extern void do_trace_rdpmc(unsigned int msr, u64 val, int failed); 67 #else 68 static inline void do_trace_write_msr(unsigned int msr, u64 val, int failed) {} 69 static inline void do_trace_read_msr(unsigned int msr, u64 val, int failed) {} 70 static inline void do_trace_rdpmc(unsigned int msr, u64 val, int failed) {} 71 #endif 72 73 /* 74 * __rdmsr() and __wrmsr() are the two primitives which are the bare minimum MSR 75 * accessors and should not have any tracing or other functionality piggybacking 76 * on them - those are *purely* for accessing MSRs and nothing more. So don't even 77 * think of extending them - you will be slapped with a stinking trout or a frozen 78 * shark will reach you, wherever you are! You've been warned. 79 */ 80 static __always_inline unsigned long long __rdmsr(unsigned int msr) 81 { 82 DECLARE_ARGS(val, low, high); 83 84 asm volatile("1: rdmsr\n" 85 "2:\n" 86 _ASM_EXTABLE_TYPE(1b, 2b, EX_TYPE_RDMSR) 87 : EAX_EDX_RET(val, low, high) : "c" (msr)); 88 89 return EAX_EDX_VAL(val, low, high); 90 } 91 92 static __always_inline void __wrmsr(unsigned int msr, u32 low, u32 high) 93 { 94 asm volatile("1: wrmsr\n" 95 "2:\n" 96 _ASM_EXTABLE_TYPE(1b, 2b, EX_TYPE_WRMSR) 97 : : "c" (msr), "a"(low), "d" (high) : "memory"); 98 } 99 100 /* 101 * WRMSRNS behaves exactly like WRMSR with the only difference being 102 * that it is not a serializing instruction by default. 103 */ 104 static __always_inline void __wrmsrns(u32 msr, u32 low, u32 high) 105 { 106 /* Instruction opcode for WRMSRNS; supported in binutils >= 2.40. */ 107 asm volatile("1: .byte 0x0f,0x01,0xc6\n" 108 "2:\n" 109 _ASM_EXTABLE_TYPE(1b, 2b, EX_TYPE_WRMSR) 110 : : "c" (msr), "a"(low), "d" (high)); 111 } 112 113 #define native_rdmsr(msr, val1, val2) \ 114 do { \ 115 u64 __val = __rdmsr((msr)); \ 116 (void)((val1) = (u32)__val); \ 117 (void)((val2) = (u32)(__val >> 32)); \ 118 } while (0) 119 120 #define native_wrmsr(msr, low, high) \ 121 __wrmsr(msr, low, high) 122 123 #define native_wrmsrl(msr, val) \ 124 __wrmsr((msr), (u32)((u64)(val)), \ 125 (u32)((u64)(val) >> 32)) 126 127 static inline unsigned long long native_read_msr(unsigned int msr) 128 { 129 unsigned long long val; 130 131 val = __rdmsr(msr); 132 133 if (tracepoint_enabled(read_msr)) 134 do_trace_read_msr(msr, val, 0); 135 136 return val; 137 } 138 139 static inline unsigned long long native_read_msr_safe(unsigned int msr, 140 int *err) 141 { 142 DECLARE_ARGS(val, low, high); 143 144 asm volatile("1: rdmsr ; xor %[err],%[err]\n" 145 "2:\n\t" 146 _ASM_EXTABLE_TYPE_REG(1b, 2b, EX_TYPE_RDMSR_SAFE, %[err]) 147 : [err] "=r" (*err), EAX_EDX_RET(val, low, high) 148 : "c" (msr)); 149 if (tracepoint_enabled(read_msr)) 150 do_trace_read_msr(msr, EAX_EDX_VAL(val, low, high), *err); 151 return EAX_EDX_VAL(val, low, high); 152 } 153 154 /* Can be uninlined because referenced by paravirt */ 155 static inline void notrace 156 native_write_msr(unsigned int msr, u32 low, u32 high) 157 { 158 __wrmsr(msr, low, high); 159 160 if (tracepoint_enabled(write_msr)) 161 do_trace_write_msr(msr, ((u64)high << 32 | low), 0); 162 } 163 164 /* Can be uninlined because referenced by paravirt */ 165 static inline int notrace 166 native_write_msr_safe(unsigned int msr, u32 low, u32 high) 167 { 168 int err; 169 170 asm volatile("1: wrmsr ; xor %[err],%[err]\n" 171 "2:\n\t" 172 _ASM_EXTABLE_TYPE_REG(1b, 2b, EX_TYPE_WRMSR_SAFE, %[err]) 173 : [err] "=a" (err) 174 : "c" (msr), "0" (low), "d" (high) 175 : "memory"); 176 if (tracepoint_enabled(write_msr)) 177 do_trace_write_msr(msr, ((u64)high << 32 | low), err); 178 return err; 179 } 180 181 extern int rdmsr_safe_regs(u32 regs[8]); 182 extern int wrmsr_safe_regs(u32 regs[8]); 183 184 /** 185 * rdtsc() - returns the current TSC without ordering constraints 186 * 187 * rdtsc() returns the result of RDTSC as a 64-bit integer. The 188 * only ordering constraint it supplies is the ordering implied by 189 * "asm volatile": it will put the RDTSC in the place you expect. The 190 * CPU can and will speculatively execute that RDTSC, though, so the 191 * results can be non-monotonic if compared on different CPUs. 192 */ 193 static __always_inline unsigned long long rdtsc(void) 194 { 195 DECLARE_ARGS(val, low, high); 196 197 asm volatile("rdtsc" : EAX_EDX_RET(val, low, high)); 198 199 return EAX_EDX_VAL(val, low, high); 200 } 201 202 /** 203 * rdtsc_ordered() - read the current TSC in program order 204 * 205 * rdtsc_ordered() returns the result of RDTSC as a 64-bit integer. 206 * It is ordered like a load to a global in-memory counter. It should 207 * be impossible to observe non-monotonic rdtsc_unordered() behavior 208 * across multiple CPUs as long as the TSC is synced. 209 */ 210 static __always_inline unsigned long long rdtsc_ordered(void) 211 { 212 DECLARE_ARGS(val, low, high); 213 214 /* 215 * The RDTSC instruction is not ordered relative to memory 216 * access. The Intel SDM and the AMD APM are both vague on this 217 * point, but empirically an RDTSC instruction can be 218 * speculatively executed before prior loads. An RDTSC 219 * immediately after an appropriate barrier appears to be 220 * ordered as a normal load, that is, it provides the same 221 * ordering guarantees as reading from a global memory location 222 * that some other imaginary CPU is updating continuously with a 223 * time stamp. 224 * 225 * Thus, use the preferred barrier on the respective CPU, aiming for 226 * RDTSCP as the default. 227 */ 228 asm volatile(ALTERNATIVE_2("rdtsc", 229 "lfence; rdtsc", X86_FEATURE_LFENCE_RDTSC, 230 "rdtscp", X86_FEATURE_RDTSCP) 231 : EAX_EDX_RET(val, low, high) 232 /* RDTSCP clobbers ECX with MSR_TSC_AUX. */ 233 :: "ecx"); 234 235 return EAX_EDX_VAL(val, low, high); 236 } 237 238 static inline unsigned long long native_read_pmc(int counter) 239 { 240 DECLARE_ARGS(val, low, high); 241 242 asm volatile("rdpmc" : EAX_EDX_RET(val, low, high) : "c" (counter)); 243 if (tracepoint_enabled(rdpmc)) 244 do_trace_rdpmc(counter, EAX_EDX_VAL(val, low, high), 0); 245 return EAX_EDX_VAL(val, low, high); 246 } 247 248 #ifdef CONFIG_PARAVIRT_XXL 249 #include <asm/paravirt.h> 250 #else 251 #include <linux/errno.h> 252 /* 253 * Access to machine-specific registers (available on 586 and better only) 254 * Note: the rd* operations modify the parameters directly (without using 255 * pointer indirection), this allows gcc to optimize better 256 */ 257 258 #define rdmsr(msr, low, high) \ 259 do { \ 260 u64 __val = native_read_msr((msr)); \ 261 (void)((low) = (u32)__val); \ 262 (void)((high) = (u32)(__val >> 32)); \ 263 } while (0) 264 265 static inline void wrmsr(unsigned int msr, u32 low, u32 high) 266 { 267 native_write_msr(msr, low, high); 268 } 269 270 #define rdmsrl(msr, val) \ 271 ((val) = native_read_msr((msr))) 272 273 static inline void wrmsrl(unsigned int msr, u64 val) 274 { 275 native_write_msr(msr, (u32)(val & 0xffffffffULL), (u32)(val >> 32)); 276 } 277 278 /* wrmsr with exception handling */ 279 static inline int wrmsr_safe(unsigned int msr, u32 low, u32 high) 280 { 281 return native_write_msr_safe(msr, low, high); 282 } 283 284 /* rdmsr with exception handling */ 285 #define rdmsr_safe(msr, low, high) \ 286 ({ \ 287 int __err; \ 288 u64 __val = native_read_msr_safe((msr), &__err); \ 289 (*low) = (u32)__val; \ 290 (*high) = (u32)(__val >> 32); \ 291 __err; \ 292 }) 293 294 static inline int rdmsrl_safe(unsigned int msr, unsigned long long *p) 295 { 296 int err; 297 298 *p = native_read_msr_safe(msr, &err); 299 return err; 300 } 301 302 #define rdpmc(counter, low, high) \ 303 do { \ 304 u64 _l = native_read_pmc((counter)); \ 305 (low) = (u32)_l; \ 306 (high) = (u32)(_l >> 32); \ 307 } while (0) 308 309 #define rdpmcl(counter, val) ((val) = native_read_pmc(counter)) 310 311 #endif /* !CONFIG_PARAVIRT_XXL */ 312 313 static __always_inline void wrmsrns(u32 msr, u64 val) 314 { 315 __wrmsrns(msr, val, val >> 32); 316 } 317 318 /* 319 * 64-bit version of wrmsr_safe(): 320 */ 321 static inline int wrmsrl_safe(u32 msr, u64 val) 322 { 323 return wrmsr_safe(msr, (u32)val, (u32)(val >> 32)); 324 } 325 326 struct msr *msrs_alloc(void); 327 void msrs_free(struct msr *msrs); 328 int msr_set_bit(u32 msr, u8 bit); 329 int msr_clear_bit(u32 msr, u8 bit); 330 331 #ifdef CONFIG_SMP 332 int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h); 333 int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h); 334 int rdmsrl_on_cpu(unsigned int cpu, u32 msr_no, u64 *q); 335 int wrmsrl_on_cpu(unsigned int cpu, u32 msr_no, u64 q); 336 void rdmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr *msrs); 337 void wrmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr *msrs); 338 int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h); 339 int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h); 340 int rdmsrl_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 *q); 341 int wrmsrl_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 q); 342 int rdmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]); 343 int wrmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]); 344 #else /* CONFIG_SMP */ 345 static inline int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h) 346 { 347 rdmsr(msr_no, *l, *h); 348 return 0; 349 } 350 static inline int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h) 351 { 352 wrmsr(msr_no, l, h); 353 return 0; 354 } 355 static inline int rdmsrl_on_cpu(unsigned int cpu, u32 msr_no, u64 *q) 356 { 357 rdmsrl(msr_no, *q); 358 return 0; 359 } 360 static inline int wrmsrl_on_cpu(unsigned int cpu, u32 msr_no, u64 q) 361 { 362 wrmsrl(msr_no, q); 363 return 0; 364 } 365 static inline void rdmsr_on_cpus(const struct cpumask *m, u32 msr_no, 366 struct msr *msrs) 367 { 368 rdmsr_on_cpu(0, msr_no, &(msrs[0].l), &(msrs[0].h)); 369 } 370 static inline void wrmsr_on_cpus(const struct cpumask *m, u32 msr_no, 371 struct msr *msrs) 372 { 373 wrmsr_on_cpu(0, msr_no, msrs[0].l, msrs[0].h); 374 } 375 static inline int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, 376 u32 *l, u32 *h) 377 { 378 return rdmsr_safe(msr_no, l, h); 379 } 380 static inline int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h) 381 { 382 return wrmsr_safe(msr_no, l, h); 383 } 384 static inline int rdmsrl_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 *q) 385 { 386 return rdmsrl_safe(msr_no, q); 387 } 388 static inline int wrmsrl_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 q) 389 { 390 return wrmsrl_safe(msr_no, q); 391 } 392 static inline int rdmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]) 393 { 394 return rdmsr_safe_regs(regs); 395 } 396 static inline int wrmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]) 397 { 398 return wrmsr_safe_regs(regs); 399 } 400 #endif /* CONFIG_SMP */ 401 #endif /* __ASSEMBLY__ */ 402 #endif /* _ASM_X86_MSR_H */ 403