1 #ifndef _ASM_X86_MSR_INDEX_H 2 #define _ASM_X86_MSR_INDEX_H 3 4 /* CPU model specific register (MSR) numbers */ 5 6 /* x86-64 specific MSRs */ 7 #define MSR_EFER 0xc0000080 /* extended feature register */ 8 #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */ 9 #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */ 10 #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */ 11 #define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */ 12 #define MSR_FS_BASE 0xc0000100 /* 64bit FS base */ 13 #define MSR_GS_BASE 0xc0000101 /* 64bit GS base */ 14 #define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */ 15 #define MSR_TSC_AUX 0xc0000103 /* Auxiliary TSC */ 16 17 /* EFER bits: */ 18 #define _EFER_SCE 0 /* SYSCALL/SYSRET */ 19 #define _EFER_LME 8 /* Long mode enable */ 20 #define _EFER_LMA 10 /* Long mode active (read-only) */ 21 #define _EFER_NX 11 /* No execute enable */ 22 #define _EFER_SVME 12 /* Enable virtualization */ 23 #define _EFER_LMSLE 13 /* Long Mode Segment Limit Enable */ 24 #define _EFER_FFXSR 14 /* Enable Fast FXSAVE/FXRSTOR */ 25 26 #define EFER_SCE (1<<_EFER_SCE) 27 #define EFER_LME (1<<_EFER_LME) 28 #define EFER_LMA (1<<_EFER_LMA) 29 #define EFER_NX (1<<_EFER_NX) 30 #define EFER_SVME (1<<_EFER_SVME) 31 #define EFER_LMSLE (1<<_EFER_LMSLE) 32 #define EFER_FFXSR (1<<_EFER_FFXSR) 33 34 /* Intel MSRs. Some also available on other CPUs */ 35 #define MSR_IA32_PERFCTR0 0x000000c1 36 #define MSR_IA32_PERFCTR1 0x000000c2 37 #define MSR_FSB_FREQ 0x000000cd 38 #define MSR_NHM_PLATFORM_INFO 0x000000ce 39 40 #define MSR_NHM_SNB_PKG_CST_CFG_CTL 0x000000e2 41 #define NHM_C3_AUTO_DEMOTE (1UL << 25) 42 #define NHM_C1_AUTO_DEMOTE (1UL << 26) 43 #define ATM_LNC_C6_AUTO_DEMOTE (1UL << 25) 44 #define SNB_C1_AUTO_UNDEMOTE (1UL << 27) 45 #define SNB_C3_AUTO_UNDEMOTE (1UL << 28) 46 47 #define MSR_PLATFORM_INFO 0x000000ce 48 #define MSR_MTRRcap 0x000000fe 49 #define MSR_IA32_BBL_CR_CTL 0x00000119 50 #define MSR_IA32_BBL_CR_CTL3 0x0000011e 51 52 #define MSR_IA32_SYSENTER_CS 0x00000174 53 #define MSR_IA32_SYSENTER_ESP 0x00000175 54 #define MSR_IA32_SYSENTER_EIP 0x00000176 55 56 #define MSR_IA32_MCG_CAP 0x00000179 57 #define MSR_IA32_MCG_STATUS 0x0000017a 58 #define MSR_IA32_MCG_CTL 0x0000017b 59 #define MSR_IA32_MCG_EXT_CTL 0x000004d0 60 61 #define MSR_OFFCORE_RSP_0 0x000001a6 62 #define MSR_OFFCORE_RSP_1 0x000001a7 63 #define MSR_NHM_TURBO_RATIO_LIMIT 0x000001ad 64 #define MSR_IVT_TURBO_RATIO_LIMIT 0x000001ae 65 #define MSR_TURBO_RATIO_LIMIT 0x000001ad 66 #define MSR_TURBO_RATIO_LIMIT1 0x000001ae 67 #define MSR_TURBO_RATIO_LIMIT2 0x000001af 68 69 #define MSR_LBR_SELECT 0x000001c8 70 #define MSR_LBR_TOS 0x000001c9 71 #define MSR_LBR_NHM_FROM 0x00000680 72 #define MSR_LBR_NHM_TO 0x000006c0 73 #define MSR_LBR_CORE_FROM 0x00000040 74 #define MSR_LBR_CORE_TO 0x00000060 75 76 #define MSR_LBR_INFO_0 0x00000dc0 /* ... 0xddf for _31 */ 77 #define LBR_INFO_MISPRED BIT_ULL(63) 78 #define LBR_INFO_IN_TX BIT_ULL(62) 79 #define LBR_INFO_ABORT BIT_ULL(61) 80 #define LBR_INFO_CYCLES 0xffff 81 82 #define MSR_IA32_PEBS_ENABLE 0x000003f1 83 #define MSR_IA32_DS_AREA 0x00000600 84 #define MSR_IA32_PERF_CAPABILITIES 0x00000345 85 #define MSR_PEBS_LD_LAT_THRESHOLD 0x000003f6 86 87 #define MSR_IA32_RTIT_CTL 0x00000570 88 #define RTIT_CTL_TRACEEN BIT(0) 89 #define RTIT_CTL_CYCLEACC BIT(1) 90 #define RTIT_CTL_OS BIT(2) 91 #define RTIT_CTL_USR BIT(3) 92 #define RTIT_CTL_CR3EN BIT(7) 93 #define RTIT_CTL_TOPA BIT(8) 94 #define RTIT_CTL_MTC_EN BIT(9) 95 #define RTIT_CTL_TSC_EN BIT(10) 96 #define RTIT_CTL_DISRETC BIT(11) 97 #define RTIT_CTL_BRANCH_EN BIT(13) 98 #define RTIT_CTL_MTC_RANGE_OFFSET 14 99 #define RTIT_CTL_MTC_RANGE (0x0full << RTIT_CTL_MTC_RANGE_OFFSET) 100 #define RTIT_CTL_CYC_THRESH_OFFSET 19 101 #define RTIT_CTL_CYC_THRESH (0x0full << RTIT_CTL_CYC_THRESH_OFFSET) 102 #define RTIT_CTL_PSB_FREQ_OFFSET 24 103 #define RTIT_CTL_PSB_FREQ (0x0full << RTIT_CTL_PSB_FREQ_OFFSET) 104 #define MSR_IA32_RTIT_STATUS 0x00000571 105 #define RTIT_STATUS_CONTEXTEN BIT(1) 106 #define RTIT_STATUS_TRIGGEREN BIT(2) 107 #define RTIT_STATUS_ERROR BIT(4) 108 #define RTIT_STATUS_STOPPED BIT(5) 109 #define MSR_IA32_RTIT_CR3_MATCH 0x00000572 110 #define MSR_IA32_RTIT_OUTPUT_BASE 0x00000560 111 #define MSR_IA32_RTIT_OUTPUT_MASK 0x00000561 112 113 #define MSR_MTRRfix64K_00000 0x00000250 114 #define MSR_MTRRfix16K_80000 0x00000258 115 #define MSR_MTRRfix16K_A0000 0x00000259 116 #define MSR_MTRRfix4K_C0000 0x00000268 117 #define MSR_MTRRfix4K_C8000 0x00000269 118 #define MSR_MTRRfix4K_D0000 0x0000026a 119 #define MSR_MTRRfix4K_D8000 0x0000026b 120 #define MSR_MTRRfix4K_E0000 0x0000026c 121 #define MSR_MTRRfix4K_E8000 0x0000026d 122 #define MSR_MTRRfix4K_F0000 0x0000026e 123 #define MSR_MTRRfix4K_F8000 0x0000026f 124 #define MSR_MTRRdefType 0x000002ff 125 126 #define MSR_IA32_CR_PAT 0x00000277 127 128 #define MSR_IA32_DEBUGCTLMSR 0x000001d9 129 #define MSR_IA32_LASTBRANCHFROMIP 0x000001db 130 #define MSR_IA32_LASTBRANCHTOIP 0x000001dc 131 #define MSR_IA32_LASTINTFROMIP 0x000001dd 132 #define MSR_IA32_LASTINTTOIP 0x000001de 133 134 /* DEBUGCTLMSR bits (others vary by model): */ 135 #define DEBUGCTLMSR_LBR (1UL << 0) /* last branch recording */ 136 #define DEBUGCTLMSR_BTF (1UL << 1) /* single-step on branches */ 137 #define DEBUGCTLMSR_TR (1UL << 6) 138 #define DEBUGCTLMSR_BTS (1UL << 7) 139 #define DEBUGCTLMSR_BTINT (1UL << 8) 140 #define DEBUGCTLMSR_BTS_OFF_OS (1UL << 9) 141 #define DEBUGCTLMSR_BTS_OFF_USR (1UL << 10) 142 #define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI (1UL << 11) 143 144 #define MSR_PEBS_FRONTEND 0x000003f7 145 146 #define MSR_IA32_POWER_CTL 0x000001fc 147 148 #define MSR_IA32_MC0_CTL 0x00000400 149 #define MSR_IA32_MC0_STATUS 0x00000401 150 #define MSR_IA32_MC0_ADDR 0x00000402 151 #define MSR_IA32_MC0_MISC 0x00000403 152 153 /* C-state Residency Counters */ 154 #define MSR_PKG_C3_RESIDENCY 0x000003f8 155 #define MSR_PKG_C6_RESIDENCY 0x000003f9 156 #define MSR_PKG_C7_RESIDENCY 0x000003fa 157 #define MSR_CORE_C3_RESIDENCY 0x000003fc 158 #define MSR_CORE_C6_RESIDENCY 0x000003fd 159 #define MSR_CORE_C7_RESIDENCY 0x000003fe 160 #define MSR_KNL_CORE_C6_RESIDENCY 0x000003ff 161 #define MSR_PKG_C2_RESIDENCY 0x0000060d 162 #define MSR_PKG_C8_RESIDENCY 0x00000630 163 #define MSR_PKG_C9_RESIDENCY 0x00000631 164 #define MSR_PKG_C10_RESIDENCY 0x00000632 165 166 /* Run Time Average Power Limiting (RAPL) Interface */ 167 168 #define MSR_RAPL_POWER_UNIT 0x00000606 169 170 #define MSR_PKG_POWER_LIMIT 0x00000610 171 #define MSR_PKG_ENERGY_STATUS 0x00000611 172 #define MSR_PKG_PERF_STATUS 0x00000613 173 #define MSR_PKG_POWER_INFO 0x00000614 174 175 #define MSR_DRAM_POWER_LIMIT 0x00000618 176 #define MSR_DRAM_ENERGY_STATUS 0x00000619 177 #define MSR_DRAM_PERF_STATUS 0x0000061b 178 #define MSR_DRAM_POWER_INFO 0x0000061c 179 180 #define MSR_PP0_POWER_LIMIT 0x00000638 181 #define MSR_PP0_ENERGY_STATUS 0x00000639 182 #define MSR_PP0_POLICY 0x0000063a 183 #define MSR_PP0_PERF_STATUS 0x0000063b 184 185 #define MSR_PP1_POWER_LIMIT 0x00000640 186 #define MSR_PP1_ENERGY_STATUS 0x00000641 187 #define MSR_PP1_POLICY 0x00000642 188 189 #define MSR_CONFIG_TDP_NOMINAL 0x00000648 190 #define MSR_CONFIG_TDP_LEVEL_1 0x00000649 191 #define MSR_CONFIG_TDP_LEVEL_2 0x0000064A 192 #define MSR_CONFIG_TDP_CONTROL 0x0000064B 193 #define MSR_TURBO_ACTIVATION_RATIO 0x0000064C 194 195 #define MSR_PKG_WEIGHTED_CORE_C0_RES 0x00000658 196 #define MSR_PKG_ANY_CORE_C0_RES 0x00000659 197 #define MSR_PKG_ANY_GFXE_C0_RES 0x0000065A 198 #define MSR_PKG_BOTH_CORE_GFXE_C0_RES 0x0000065B 199 200 #define MSR_CORE_C1_RES 0x00000660 201 202 #define MSR_CC6_DEMOTION_POLICY_CONFIG 0x00000668 203 #define MSR_MC6_DEMOTION_POLICY_CONFIG 0x00000669 204 205 #define MSR_CORE_PERF_LIMIT_REASONS 0x00000690 206 #define MSR_GFX_PERF_LIMIT_REASONS 0x000006B0 207 #define MSR_RING_PERF_LIMIT_REASONS 0x000006B1 208 209 /* Hardware P state interface */ 210 #define MSR_PPERF 0x0000064e 211 #define MSR_PERF_LIMIT_REASONS 0x0000064f 212 #define MSR_PM_ENABLE 0x00000770 213 #define MSR_HWP_CAPABILITIES 0x00000771 214 #define MSR_HWP_REQUEST_PKG 0x00000772 215 #define MSR_HWP_INTERRUPT 0x00000773 216 #define MSR_HWP_REQUEST 0x00000774 217 #define MSR_HWP_STATUS 0x00000777 218 219 /* CPUID.6.EAX */ 220 #define HWP_BASE_BIT (1<<7) 221 #define HWP_NOTIFICATIONS_BIT (1<<8) 222 #define HWP_ACTIVITY_WINDOW_BIT (1<<9) 223 #define HWP_ENERGY_PERF_PREFERENCE_BIT (1<<10) 224 #define HWP_PACKAGE_LEVEL_REQUEST_BIT (1<<11) 225 226 /* IA32_HWP_CAPABILITIES */ 227 #define HWP_HIGHEST_PERF(x) (x & 0xff) 228 #define HWP_GUARANTEED_PERF(x) ((x & (0xff << 8)) >>8) 229 #define HWP_MOSTEFFICIENT_PERF(x) ((x & (0xff << 16)) >>16) 230 #define HWP_LOWEST_PERF(x) ((x & (0xff << 24)) >>24) 231 232 /* IA32_HWP_REQUEST */ 233 #define HWP_MIN_PERF(x) (x & 0xff) 234 #define HWP_MAX_PERF(x) ((x & 0xff) << 8) 235 #define HWP_DESIRED_PERF(x) ((x & 0xff) << 16) 236 #define HWP_ENERGY_PERF_PREFERENCE(x) ((x & 0xff) << 24) 237 #define HWP_ACTIVITY_WINDOW(x) ((x & 0xff3) << 32) 238 #define HWP_PACKAGE_CONTROL(x) ((x & 0x1) << 42) 239 240 /* IA32_HWP_STATUS */ 241 #define HWP_GUARANTEED_CHANGE(x) (x & 0x1) 242 #define HWP_EXCURSION_TO_MINIMUM(x) (x & 0x4) 243 244 /* IA32_HWP_INTERRUPT */ 245 #define HWP_CHANGE_TO_GUARANTEED_INT(x) (x & 0x1) 246 #define HWP_EXCURSION_TO_MINIMUM_INT(x) (x & 0x2) 247 248 #define MSR_AMD64_MC0_MASK 0xc0010044 249 250 #define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x)) 251 #define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x)) 252 #define MSR_IA32_MCx_ADDR(x) (MSR_IA32_MC0_ADDR + 4*(x)) 253 #define MSR_IA32_MCx_MISC(x) (MSR_IA32_MC0_MISC + 4*(x)) 254 255 #define MSR_AMD64_MCx_MASK(x) (MSR_AMD64_MC0_MASK + (x)) 256 257 /* These are consecutive and not in the normal 4er MCE bank block */ 258 #define MSR_IA32_MC0_CTL2 0x00000280 259 #define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x)) 260 261 #define MSR_P6_PERFCTR0 0x000000c1 262 #define MSR_P6_PERFCTR1 0x000000c2 263 #define MSR_P6_EVNTSEL0 0x00000186 264 #define MSR_P6_EVNTSEL1 0x00000187 265 266 #define MSR_KNC_PERFCTR0 0x00000020 267 #define MSR_KNC_PERFCTR1 0x00000021 268 #define MSR_KNC_EVNTSEL0 0x00000028 269 #define MSR_KNC_EVNTSEL1 0x00000029 270 271 /* Alternative perfctr range with full access. */ 272 #define MSR_IA32_PMC0 0x000004c1 273 274 /* AMD64 MSRs. Not complete. See the architecture manual for a more 275 complete list. */ 276 277 #define MSR_AMD64_PATCH_LEVEL 0x0000008b 278 #define MSR_AMD64_TSC_RATIO 0xc0000104 279 #define MSR_AMD64_NB_CFG 0xc001001f 280 #define MSR_AMD64_PATCH_LOADER 0xc0010020 281 #define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140 282 #define MSR_AMD64_OSVW_STATUS 0xc0010141 283 #define MSR_AMD64_LS_CFG 0xc0011020 284 #define MSR_AMD64_DC_CFG 0xc0011022 285 #define MSR_AMD64_BU_CFG2 0xc001102a 286 #define MSR_AMD64_IBSFETCHCTL 0xc0011030 287 #define MSR_AMD64_IBSFETCHLINAD 0xc0011031 288 #define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032 289 #define MSR_AMD64_IBSFETCH_REG_COUNT 3 290 #define MSR_AMD64_IBSFETCH_REG_MASK ((1UL<<MSR_AMD64_IBSFETCH_REG_COUNT)-1) 291 #define MSR_AMD64_IBSOPCTL 0xc0011033 292 #define MSR_AMD64_IBSOPRIP 0xc0011034 293 #define MSR_AMD64_IBSOPDATA 0xc0011035 294 #define MSR_AMD64_IBSOPDATA2 0xc0011036 295 #define MSR_AMD64_IBSOPDATA3 0xc0011037 296 #define MSR_AMD64_IBSDCLINAD 0xc0011038 297 #define MSR_AMD64_IBSDCPHYSAD 0xc0011039 298 #define MSR_AMD64_IBSOP_REG_COUNT 7 299 #define MSR_AMD64_IBSOP_REG_MASK ((1UL<<MSR_AMD64_IBSOP_REG_COUNT)-1) 300 #define MSR_AMD64_IBSCTL 0xc001103a 301 #define MSR_AMD64_IBSBRTARGET 0xc001103b 302 #define MSR_AMD64_IBSOPDATA4 0xc001103d 303 #define MSR_AMD64_IBS_REG_COUNT_MAX 8 /* includes MSR_AMD64_IBSBRTARGET */ 304 305 /* Fam 16h MSRs */ 306 #define MSR_F16H_L2I_PERF_CTL 0xc0010230 307 #define MSR_F16H_L2I_PERF_CTR 0xc0010231 308 #define MSR_F16H_DR1_ADDR_MASK 0xc0011019 309 #define MSR_F16H_DR2_ADDR_MASK 0xc001101a 310 #define MSR_F16H_DR3_ADDR_MASK 0xc001101b 311 #define MSR_F16H_DR0_ADDR_MASK 0xc0011027 312 313 /* Fam 15h MSRs */ 314 #define MSR_F15H_PERF_CTL 0xc0010200 315 #define MSR_F15H_PERF_CTR 0xc0010201 316 #define MSR_F15H_NB_PERF_CTL 0xc0010240 317 #define MSR_F15H_NB_PERF_CTR 0xc0010241 318 319 /* Fam 10h MSRs */ 320 #define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058 321 #define FAM10H_MMIO_CONF_ENABLE (1<<0) 322 #define FAM10H_MMIO_CONF_BUSRANGE_MASK 0xf 323 #define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2 324 #define FAM10H_MMIO_CONF_BASE_MASK 0xfffffffULL 325 #define FAM10H_MMIO_CONF_BASE_SHIFT 20 326 #define MSR_FAM10H_NODE_ID 0xc001100c 327 328 /* K8 MSRs */ 329 #define MSR_K8_TOP_MEM1 0xc001001a 330 #define MSR_K8_TOP_MEM2 0xc001001d 331 #define MSR_K8_SYSCFG 0xc0010010 332 #define MSR_K8_INT_PENDING_MSG 0xc0010055 333 /* C1E active bits in int pending message */ 334 #define K8_INTP_C1E_ACTIVE_MASK 0x18000000 335 #define MSR_K8_TSEG_ADDR 0xc0010112 336 #define MSR_K8_TSEG_MASK 0xc0010113 337 #define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */ 338 #define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */ 339 #define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818 /* Mask: RdMem|WrMem */ 340 341 /* K7 MSRs */ 342 #define MSR_K7_EVNTSEL0 0xc0010000 343 #define MSR_K7_PERFCTR0 0xc0010004 344 #define MSR_K7_EVNTSEL1 0xc0010001 345 #define MSR_K7_PERFCTR1 0xc0010005 346 #define MSR_K7_EVNTSEL2 0xc0010002 347 #define MSR_K7_PERFCTR2 0xc0010006 348 #define MSR_K7_EVNTSEL3 0xc0010003 349 #define MSR_K7_PERFCTR3 0xc0010007 350 #define MSR_K7_CLK_CTL 0xc001001b 351 #define MSR_K7_HWCR 0xc0010015 352 #define MSR_K7_FID_VID_CTL 0xc0010041 353 #define MSR_K7_FID_VID_STATUS 0xc0010042 354 355 /* K6 MSRs */ 356 #define MSR_K6_WHCR 0xc0000082 357 #define MSR_K6_UWCCR 0xc0000085 358 #define MSR_K6_EPMR 0xc0000086 359 #define MSR_K6_PSOR 0xc0000087 360 #define MSR_K6_PFIR 0xc0000088 361 362 /* Centaur-Hauls/IDT defined MSRs. */ 363 #define MSR_IDT_FCR1 0x00000107 364 #define MSR_IDT_FCR2 0x00000108 365 #define MSR_IDT_FCR3 0x00000109 366 #define MSR_IDT_FCR4 0x0000010a 367 368 #define MSR_IDT_MCR0 0x00000110 369 #define MSR_IDT_MCR1 0x00000111 370 #define MSR_IDT_MCR2 0x00000112 371 #define MSR_IDT_MCR3 0x00000113 372 #define MSR_IDT_MCR4 0x00000114 373 #define MSR_IDT_MCR5 0x00000115 374 #define MSR_IDT_MCR6 0x00000116 375 #define MSR_IDT_MCR7 0x00000117 376 #define MSR_IDT_MCR_CTRL 0x00000120 377 378 /* VIA Cyrix defined MSRs*/ 379 #define MSR_VIA_FCR 0x00001107 380 #define MSR_VIA_LONGHAUL 0x0000110a 381 #define MSR_VIA_RNG 0x0000110b 382 #define MSR_VIA_BCR2 0x00001147 383 384 /* Transmeta defined MSRs */ 385 #define MSR_TMTA_LONGRUN_CTRL 0x80868010 386 #define MSR_TMTA_LONGRUN_FLAGS 0x80868011 387 #define MSR_TMTA_LRTI_READOUT 0x80868018 388 #define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a 389 390 /* Intel defined MSRs. */ 391 #define MSR_IA32_P5_MC_ADDR 0x00000000 392 #define MSR_IA32_P5_MC_TYPE 0x00000001 393 #define MSR_IA32_TSC 0x00000010 394 #define MSR_IA32_PLATFORM_ID 0x00000017 395 #define MSR_IA32_EBL_CR_POWERON 0x0000002a 396 #define MSR_EBC_FREQUENCY_ID 0x0000002c 397 #define MSR_SMI_COUNT 0x00000034 398 #define MSR_IA32_FEATURE_CONTROL 0x0000003a 399 #define MSR_IA32_TSC_ADJUST 0x0000003b 400 #define MSR_IA32_BNDCFGS 0x00000d90 401 402 #define MSR_IA32_XSS 0x00000da0 403 404 #define FEATURE_CONTROL_LOCKED (1<<0) 405 #define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX (1<<1) 406 #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2) 407 #define FEATURE_CONTROL_LMCE (1<<20) 408 409 #define MSR_IA32_APICBASE 0x0000001b 410 #define MSR_IA32_APICBASE_BSP (1<<8) 411 #define MSR_IA32_APICBASE_ENABLE (1<<11) 412 #define MSR_IA32_APICBASE_BASE (0xfffff<<12) 413 414 #define MSR_IA32_TSCDEADLINE 0x000006e0 415 416 #define MSR_IA32_UCODE_WRITE 0x00000079 417 #define MSR_IA32_UCODE_REV 0x0000008b 418 419 #define MSR_IA32_SMM_MONITOR_CTL 0x0000009b 420 #define MSR_IA32_SMBASE 0x0000009e 421 422 #define MSR_IA32_PERF_STATUS 0x00000198 423 #define MSR_IA32_PERF_CTL 0x00000199 424 #define INTEL_PERF_CTL_MASK 0xffff 425 #define MSR_AMD_PSTATE_DEF_BASE 0xc0010064 426 #define MSR_AMD_PERF_STATUS 0xc0010063 427 #define MSR_AMD_PERF_CTL 0xc0010062 428 429 #define MSR_IA32_MPERF 0x000000e7 430 #define MSR_IA32_APERF 0x000000e8 431 432 #define MSR_IA32_THERM_CONTROL 0x0000019a 433 #define MSR_IA32_THERM_INTERRUPT 0x0000019b 434 435 #define THERM_INT_HIGH_ENABLE (1 << 0) 436 #define THERM_INT_LOW_ENABLE (1 << 1) 437 #define THERM_INT_PLN_ENABLE (1 << 24) 438 439 #define MSR_IA32_THERM_STATUS 0x0000019c 440 441 #define THERM_STATUS_PROCHOT (1 << 0) 442 #define THERM_STATUS_POWER_LIMIT (1 << 10) 443 444 #define MSR_THERM2_CTL 0x0000019d 445 446 #define MSR_THERM2_CTL_TM_SELECT (1ULL << 16) 447 448 #define MSR_IA32_MISC_ENABLE 0x000001a0 449 450 #define MSR_IA32_TEMPERATURE_TARGET 0x000001a2 451 452 #define MSR_MISC_PWR_MGMT 0x000001aa 453 454 #define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0 455 #define ENERGY_PERF_BIAS_PERFORMANCE 0 456 #define ENERGY_PERF_BIAS_NORMAL 6 457 #define ENERGY_PERF_BIAS_POWERSAVE 15 458 459 #define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1 460 461 #define PACKAGE_THERM_STATUS_PROCHOT (1 << 0) 462 #define PACKAGE_THERM_STATUS_POWER_LIMIT (1 << 10) 463 464 #define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001b2 465 466 #define PACKAGE_THERM_INT_HIGH_ENABLE (1 << 0) 467 #define PACKAGE_THERM_INT_LOW_ENABLE (1 << 1) 468 #define PACKAGE_THERM_INT_PLN_ENABLE (1 << 24) 469 470 /* Thermal Thresholds Support */ 471 #define THERM_INT_THRESHOLD0_ENABLE (1 << 15) 472 #define THERM_SHIFT_THRESHOLD0 8 473 #define THERM_MASK_THRESHOLD0 (0x7f << THERM_SHIFT_THRESHOLD0) 474 #define THERM_INT_THRESHOLD1_ENABLE (1 << 23) 475 #define THERM_SHIFT_THRESHOLD1 16 476 #define THERM_MASK_THRESHOLD1 (0x7f << THERM_SHIFT_THRESHOLD1) 477 #define THERM_STATUS_THRESHOLD0 (1 << 6) 478 #define THERM_LOG_THRESHOLD0 (1 << 7) 479 #define THERM_STATUS_THRESHOLD1 (1 << 8) 480 #define THERM_LOG_THRESHOLD1 (1 << 9) 481 482 /* MISC_ENABLE bits: architectural */ 483 #define MSR_IA32_MISC_ENABLE_FAST_STRING_BIT 0 484 #define MSR_IA32_MISC_ENABLE_FAST_STRING (1ULL << MSR_IA32_MISC_ENABLE_FAST_STRING_BIT) 485 #define MSR_IA32_MISC_ENABLE_TCC_BIT 1 486 #define MSR_IA32_MISC_ENABLE_TCC (1ULL << MSR_IA32_MISC_ENABLE_TCC_BIT) 487 #define MSR_IA32_MISC_ENABLE_EMON_BIT 7 488 #define MSR_IA32_MISC_ENABLE_EMON (1ULL << MSR_IA32_MISC_ENABLE_EMON_BIT) 489 #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT 11 490 #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT) 491 #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT 12 492 #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT) 493 #define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT 16 494 #define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP (1ULL << MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT) 495 #define MSR_IA32_MISC_ENABLE_MWAIT_BIT 18 496 #define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << MSR_IA32_MISC_ENABLE_MWAIT_BIT) 497 #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT 22 498 #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1ULL << MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT) 499 #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT 23 500 #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT) 501 #define MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT 34 502 #define MSR_IA32_MISC_ENABLE_XD_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT) 503 504 /* MISC_ENABLE bits: model-specific, meaning may vary from core to core */ 505 #define MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT 2 506 #define MSR_IA32_MISC_ENABLE_X87_COMPAT (1ULL << MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT) 507 #define MSR_IA32_MISC_ENABLE_TM1_BIT 3 508 #define MSR_IA32_MISC_ENABLE_TM1 (1ULL << MSR_IA32_MISC_ENABLE_TM1_BIT) 509 #define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT 4 510 #define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT) 511 #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT 6 512 #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT) 513 #define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT 8 514 #define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT) 515 #define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT 9 516 #define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT) 517 #define MSR_IA32_MISC_ENABLE_FERR_BIT 10 518 #define MSR_IA32_MISC_ENABLE_FERR (1ULL << MSR_IA32_MISC_ENABLE_FERR_BIT) 519 #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT 10 520 #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX (1ULL << MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT) 521 #define MSR_IA32_MISC_ENABLE_TM2_BIT 13 522 #define MSR_IA32_MISC_ENABLE_TM2 (1ULL << MSR_IA32_MISC_ENABLE_TM2_BIT) 523 #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT 19 524 #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT) 525 #define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT 20 526 #define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT) 527 #define MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT 24 528 #define MSR_IA32_MISC_ENABLE_L1D_CONTEXT (1ULL << MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT) 529 #define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT 37 530 #define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT) 531 #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT 38 532 #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT) 533 #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT 39 534 #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT) 535 536 #define MSR_IA32_TSC_DEADLINE 0x000006E0 537 538 /* P4/Xeon+ specific */ 539 #define MSR_IA32_MCG_EAX 0x00000180 540 #define MSR_IA32_MCG_EBX 0x00000181 541 #define MSR_IA32_MCG_ECX 0x00000182 542 #define MSR_IA32_MCG_EDX 0x00000183 543 #define MSR_IA32_MCG_ESI 0x00000184 544 #define MSR_IA32_MCG_EDI 0x00000185 545 #define MSR_IA32_MCG_EBP 0x00000186 546 #define MSR_IA32_MCG_ESP 0x00000187 547 #define MSR_IA32_MCG_EFLAGS 0x00000188 548 #define MSR_IA32_MCG_EIP 0x00000189 549 #define MSR_IA32_MCG_RESERVED 0x0000018a 550 551 /* Pentium IV performance counter MSRs */ 552 #define MSR_P4_BPU_PERFCTR0 0x00000300 553 #define MSR_P4_BPU_PERFCTR1 0x00000301 554 #define MSR_P4_BPU_PERFCTR2 0x00000302 555 #define MSR_P4_BPU_PERFCTR3 0x00000303 556 #define MSR_P4_MS_PERFCTR0 0x00000304 557 #define MSR_P4_MS_PERFCTR1 0x00000305 558 #define MSR_P4_MS_PERFCTR2 0x00000306 559 #define MSR_P4_MS_PERFCTR3 0x00000307 560 #define MSR_P4_FLAME_PERFCTR0 0x00000308 561 #define MSR_P4_FLAME_PERFCTR1 0x00000309 562 #define MSR_P4_FLAME_PERFCTR2 0x0000030a 563 #define MSR_P4_FLAME_PERFCTR3 0x0000030b 564 #define MSR_P4_IQ_PERFCTR0 0x0000030c 565 #define MSR_P4_IQ_PERFCTR1 0x0000030d 566 #define MSR_P4_IQ_PERFCTR2 0x0000030e 567 #define MSR_P4_IQ_PERFCTR3 0x0000030f 568 #define MSR_P4_IQ_PERFCTR4 0x00000310 569 #define MSR_P4_IQ_PERFCTR5 0x00000311 570 #define MSR_P4_BPU_CCCR0 0x00000360 571 #define MSR_P4_BPU_CCCR1 0x00000361 572 #define MSR_P4_BPU_CCCR2 0x00000362 573 #define MSR_P4_BPU_CCCR3 0x00000363 574 #define MSR_P4_MS_CCCR0 0x00000364 575 #define MSR_P4_MS_CCCR1 0x00000365 576 #define MSR_P4_MS_CCCR2 0x00000366 577 #define MSR_P4_MS_CCCR3 0x00000367 578 #define MSR_P4_FLAME_CCCR0 0x00000368 579 #define MSR_P4_FLAME_CCCR1 0x00000369 580 #define MSR_P4_FLAME_CCCR2 0x0000036a 581 #define MSR_P4_FLAME_CCCR3 0x0000036b 582 #define MSR_P4_IQ_CCCR0 0x0000036c 583 #define MSR_P4_IQ_CCCR1 0x0000036d 584 #define MSR_P4_IQ_CCCR2 0x0000036e 585 #define MSR_P4_IQ_CCCR3 0x0000036f 586 #define MSR_P4_IQ_CCCR4 0x00000370 587 #define MSR_P4_IQ_CCCR5 0x00000371 588 #define MSR_P4_ALF_ESCR0 0x000003ca 589 #define MSR_P4_ALF_ESCR1 0x000003cb 590 #define MSR_P4_BPU_ESCR0 0x000003b2 591 #define MSR_P4_BPU_ESCR1 0x000003b3 592 #define MSR_P4_BSU_ESCR0 0x000003a0 593 #define MSR_P4_BSU_ESCR1 0x000003a1 594 #define MSR_P4_CRU_ESCR0 0x000003b8 595 #define MSR_P4_CRU_ESCR1 0x000003b9 596 #define MSR_P4_CRU_ESCR2 0x000003cc 597 #define MSR_P4_CRU_ESCR3 0x000003cd 598 #define MSR_P4_CRU_ESCR4 0x000003e0 599 #define MSR_P4_CRU_ESCR5 0x000003e1 600 #define MSR_P4_DAC_ESCR0 0x000003a8 601 #define MSR_P4_DAC_ESCR1 0x000003a9 602 #define MSR_P4_FIRM_ESCR0 0x000003a4 603 #define MSR_P4_FIRM_ESCR1 0x000003a5 604 #define MSR_P4_FLAME_ESCR0 0x000003a6 605 #define MSR_P4_FLAME_ESCR1 0x000003a7 606 #define MSR_P4_FSB_ESCR0 0x000003a2 607 #define MSR_P4_FSB_ESCR1 0x000003a3 608 #define MSR_P4_IQ_ESCR0 0x000003ba 609 #define MSR_P4_IQ_ESCR1 0x000003bb 610 #define MSR_P4_IS_ESCR0 0x000003b4 611 #define MSR_P4_IS_ESCR1 0x000003b5 612 #define MSR_P4_ITLB_ESCR0 0x000003b6 613 #define MSR_P4_ITLB_ESCR1 0x000003b7 614 #define MSR_P4_IX_ESCR0 0x000003c8 615 #define MSR_P4_IX_ESCR1 0x000003c9 616 #define MSR_P4_MOB_ESCR0 0x000003aa 617 #define MSR_P4_MOB_ESCR1 0x000003ab 618 #define MSR_P4_MS_ESCR0 0x000003c0 619 #define MSR_P4_MS_ESCR1 0x000003c1 620 #define MSR_P4_PMH_ESCR0 0x000003ac 621 #define MSR_P4_PMH_ESCR1 0x000003ad 622 #define MSR_P4_RAT_ESCR0 0x000003bc 623 #define MSR_P4_RAT_ESCR1 0x000003bd 624 #define MSR_P4_SAAT_ESCR0 0x000003ae 625 #define MSR_P4_SAAT_ESCR1 0x000003af 626 #define MSR_P4_SSU_ESCR0 0x000003be 627 #define MSR_P4_SSU_ESCR1 0x000003bf /* guess: not in manual */ 628 629 #define MSR_P4_TBPU_ESCR0 0x000003c2 630 #define MSR_P4_TBPU_ESCR1 0x000003c3 631 #define MSR_P4_TC_ESCR0 0x000003c4 632 #define MSR_P4_TC_ESCR1 0x000003c5 633 #define MSR_P4_U2L_ESCR0 0x000003b0 634 #define MSR_P4_U2L_ESCR1 0x000003b1 635 636 #define MSR_P4_PEBS_MATRIX_VERT 0x000003f2 637 638 /* Intel Core-based CPU performance counters */ 639 #define MSR_CORE_PERF_FIXED_CTR0 0x00000309 640 #define MSR_CORE_PERF_FIXED_CTR1 0x0000030a 641 #define MSR_CORE_PERF_FIXED_CTR2 0x0000030b 642 #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x0000038d 643 #define MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e 644 #define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f 645 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390 646 647 /* Geode defined MSRs */ 648 #define MSR_GEODE_BUSCONT_CONF0 0x00001900 649 650 /* Intel VT MSRs */ 651 #define MSR_IA32_VMX_BASIC 0x00000480 652 #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481 653 #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482 654 #define MSR_IA32_VMX_EXIT_CTLS 0x00000483 655 #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484 656 #define MSR_IA32_VMX_MISC 0x00000485 657 #define MSR_IA32_VMX_CR0_FIXED0 0x00000486 658 #define MSR_IA32_VMX_CR0_FIXED1 0x00000487 659 #define MSR_IA32_VMX_CR4_FIXED0 0x00000488 660 #define MSR_IA32_VMX_CR4_FIXED1 0x00000489 661 #define MSR_IA32_VMX_VMCS_ENUM 0x0000048a 662 #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b 663 #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c 664 #define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d 665 #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e 666 #define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f 667 #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490 668 #define MSR_IA32_VMX_VMFUNC 0x00000491 669 670 /* VMX_BASIC bits and bitmasks */ 671 #define VMX_BASIC_VMCS_SIZE_SHIFT 32 672 #define VMX_BASIC_TRUE_CTLS (1ULL << 55) 673 #define VMX_BASIC_64 0x0001000000000000LLU 674 #define VMX_BASIC_MEM_TYPE_SHIFT 50 675 #define VMX_BASIC_MEM_TYPE_MASK 0x003c000000000000LLU 676 #define VMX_BASIC_MEM_TYPE_WB 6LLU 677 #define VMX_BASIC_INOUT 0x0040000000000000LLU 678 679 /* MSR_IA32_VMX_MISC bits */ 680 #define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS (1ULL << 29) 681 #define MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE 0x1F 682 /* AMD-V MSRs */ 683 684 #define MSR_VM_CR 0xc0010114 685 #define MSR_VM_IGNNE 0xc0010115 686 #define MSR_VM_HSAVE_PA 0xc0010117 687 688 #endif /* _ASM_X86_MSR_INDEX_H */ 689