1 #ifndef _ASM_X86_MSR_INDEX_H 2 #define _ASM_X86_MSR_INDEX_H 3 4 /* CPU model specific register (MSR) numbers */ 5 6 /* x86-64 specific MSRs */ 7 #define MSR_EFER 0xc0000080 /* extended feature register */ 8 #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */ 9 #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */ 10 #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */ 11 #define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */ 12 #define MSR_FS_BASE 0xc0000100 /* 64bit FS base */ 13 #define MSR_GS_BASE 0xc0000101 /* 64bit GS base */ 14 #define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */ 15 #define MSR_TSC_AUX 0xc0000103 /* Auxiliary TSC */ 16 17 /* EFER bits: */ 18 #define _EFER_SCE 0 /* SYSCALL/SYSRET */ 19 #define _EFER_LME 8 /* Long mode enable */ 20 #define _EFER_LMA 10 /* Long mode active (read-only) */ 21 #define _EFER_NX 11 /* No execute enable */ 22 #define _EFER_SVME 12 /* Enable virtualization */ 23 #define _EFER_LMSLE 13 /* Long Mode Segment Limit Enable */ 24 #define _EFER_FFXSR 14 /* Enable Fast FXSAVE/FXRSTOR */ 25 26 #define EFER_SCE (1<<_EFER_SCE) 27 #define EFER_LME (1<<_EFER_LME) 28 #define EFER_LMA (1<<_EFER_LMA) 29 #define EFER_NX (1<<_EFER_NX) 30 #define EFER_SVME (1<<_EFER_SVME) 31 #define EFER_LMSLE (1<<_EFER_LMSLE) 32 #define EFER_FFXSR (1<<_EFER_FFXSR) 33 34 /* Intel MSRs. Some also available on other CPUs */ 35 #define MSR_IA32_PERFCTR0 0x000000c1 36 #define MSR_IA32_PERFCTR1 0x000000c2 37 #define MSR_FSB_FREQ 0x000000cd 38 39 #define MSR_MTRRcap 0x000000fe 40 #define MSR_IA32_BBL_CR_CTL 0x00000119 41 42 #define MSR_IA32_SYSENTER_CS 0x00000174 43 #define MSR_IA32_SYSENTER_ESP 0x00000175 44 #define MSR_IA32_SYSENTER_EIP 0x00000176 45 46 #define MSR_IA32_MCG_CAP 0x00000179 47 #define MSR_IA32_MCG_STATUS 0x0000017a 48 #define MSR_IA32_MCG_CTL 0x0000017b 49 50 #define MSR_IA32_PEBS_ENABLE 0x000003f1 51 #define MSR_IA32_DS_AREA 0x00000600 52 #define MSR_IA32_PERF_CAPABILITIES 0x00000345 53 54 #define MSR_MTRRfix64K_00000 0x00000250 55 #define MSR_MTRRfix16K_80000 0x00000258 56 #define MSR_MTRRfix16K_A0000 0x00000259 57 #define MSR_MTRRfix4K_C0000 0x00000268 58 #define MSR_MTRRfix4K_C8000 0x00000269 59 #define MSR_MTRRfix4K_D0000 0x0000026a 60 #define MSR_MTRRfix4K_D8000 0x0000026b 61 #define MSR_MTRRfix4K_E0000 0x0000026c 62 #define MSR_MTRRfix4K_E8000 0x0000026d 63 #define MSR_MTRRfix4K_F0000 0x0000026e 64 #define MSR_MTRRfix4K_F8000 0x0000026f 65 #define MSR_MTRRdefType 0x000002ff 66 67 #define MSR_IA32_CR_PAT 0x00000277 68 69 #define MSR_IA32_DEBUGCTLMSR 0x000001d9 70 #define MSR_IA32_LASTBRANCHFROMIP 0x000001db 71 #define MSR_IA32_LASTBRANCHTOIP 0x000001dc 72 #define MSR_IA32_LASTINTFROMIP 0x000001dd 73 #define MSR_IA32_LASTINTTOIP 0x000001de 74 75 /* DEBUGCTLMSR bits (others vary by model): */ 76 #define DEBUGCTLMSR_LBR (1UL << 0) /* last branch recording */ 77 #define DEBUGCTLMSR_BTF (1UL << 1) /* single-step on branches */ 78 #define DEBUGCTLMSR_TR (1UL << 6) 79 #define DEBUGCTLMSR_BTS (1UL << 7) 80 #define DEBUGCTLMSR_BTINT (1UL << 8) 81 #define DEBUGCTLMSR_BTS_OFF_OS (1UL << 9) 82 #define DEBUGCTLMSR_BTS_OFF_USR (1UL << 10) 83 #define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI (1UL << 11) 84 85 #define MSR_IA32_MC0_CTL 0x00000400 86 #define MSR_IA32_MC0_STATUS 0x00000401 87 #define MSR_IA32_MC0_ADDR 0x00000402 88 #define MSR_IA32_MC0_MISC 0x00000403 89 90 #define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x)) 91 #define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x)) 92 #define MSR_IA32_MCx_ADDR(x) (MSR_IA32_MC0_ADDR + 4*(x)) 93 #define MSR_IA32_MCx_MISC(x) (MSR_IA32_MC0_MISC + 4*(x)) 94 95 /* These are consecutive and not in the normal 4er MCE bank block */ 96 #define MSR_IA32_MC0_CTL2 0x00000280 97 #define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x)) 98 99 #define MSR_P6_PERFCTR0 0x000000c1 100 #define MSR_P6_PERFCTR1 0x000000c2 101 #define MSR_P6_EVNTSEL0 0x00000186 102 #define MSR_P6_EVNTSEL1 0x00000187 103 104 /* AMD64 MSRs. Not complete. See the architecture manual for a more 105 complete list. */ 106 107 #define MSR_AMD64_PATCH_LEVEL 0x0000008b 108 #define MSR_AMD64_NB_CFG 0xc001001f 109 #define MSR_AMD64_PATCH_LOADER 0xc0010020 110 #define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140 111 #define MSR_AMD64_OSVW_STATUS 0xc0010141 112 #define MSR_AMD64_DC_CFG 0xc0011022 113 #define MSR_AMD64_IBSFETCHCTL 0xc0011030 114 #define MSR_AMD64_IBSFETCHLINAD 0xc0011031 115 #define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032 116 #define MSR_AMD64_IBSOPCTL 0xc0011033 117 #define MSR_AMD64_IBSOPRIP 0xc0011034 118 #define MSR_AMD64_IBSOPDATA 0xc0011035 119 #define MSR_AMD64_IBSOPDATA2 0xc0011036 120 #define MSR_AMD64_IBSOPDATA3 0xc0011037 121 #define MSR_AMD64_IBSDCLINAD 0xc0011038 122 #define MSR_AMD64_IBSDCPHYSAD 0xc0011039 123 #define MSR_AMD64_IBSCTL 0xc001103a 124 #define MSR_AMD64_IBSBRTARGET 0xc001103b 125 126 /* Fam 10h MSRs */ 127 #define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058 128 #define FAM10H_MMIO_CONF_ENABLE (1<<0) 129 #define FAM10H_MMIO_CONF_BUSRANGE_MASK 0xf 130 #define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2 131 #define FAM10H_MMIO_CONF_BASE_MASK 0xfffffff 132 #define FAM10H_MMIO_CONF_BASE_SHIFT 20 133 #define MSR_FAM10H_NODE_ID 0xc001100c 134 135 /* K8 MSRs */ 136 #define MSR_K8_TOP_MEM1 0xc001001a 137 #define MSR_K8_TOP_MEM2 0xc001001d 138 #define MSR_K8_SYSCFG 0xc0010010 139 #define MSR_K8_INT_PENDING_MSG 0xc0010055 140 /* C1E active bits in int pending message */ 141 #define K8_INTP_C1E_ACTIVE_MASK 0x18000000 142 #define MSR_K8_TSEG_ADDR 0xc0010112 143 #define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */ 144 #define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */ 145 #define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818 /* Mask: RdMem|WrMem */ 146 147 /* K7 MSRs */ 148 #define MSR_K7_EVNTSEL0 0xc0010000 149 #define MSR_K7_PERFCTR0 0xc0010004 150 #define MSR_K7_EVNTSEL1 0xc0010001 151 #define MSR_K7_PERFCTR1 0xc0010005 152 #define MSR_K7_EVNTSEL2 0xc0010002 153 #define MSR_K7_PERFCTR2 0xc0010006 154 #define MSR_K7_EVNTSEL3 0xc0010003 155 #define MSR_K7_PERFCTR3 0xc0010007 156 #define MSR_K7_CLK_CTL 0xc001001b 157 #define MSR_K7_HWCR 0xc0010015 158 #define MSR_K7_FID_VID_CTL 0xc0010041 159 #define MSR_K7_FID_VID_STATUS 0xc0010042 160 161 /* K6 MSRs */ 162 #define MSR_K6_WHCR 0xc0000082 163 #define MSR_K6_UWCCR 0xc0000085 164 #define MSR_K6_EPMR 0xc0000086 165 #define MSR_K6_PSOR 0xc0000087 166 #define MSR_K6_PFIR 0xc0000088 167 168 /* Centaur-Hauls/IDT defined MSRs. */ 169 #define MSR_IDT_FCR1 0x00000107 170 #define MSR_IDT_FCR2 0x00000108 171 #define MSR_IDT_FCR3 0x00000109 172 #define MSR_IDT_FCR4 0x0000010a 173 174 #define MSR_IDT_MCR0 0x00000110 175 #define MSR_IDT_MCR1 0x00000111 176 #define MSR_IDT_MCR2 0x00000112 177 #define MSR_IDT_MCR3 0x00000113 178 #define MSR_IDT_MCR4 0x00000114 179 #define MSR_IDT_MCR5 0x00000115 180 #define MSR_IDT_MCR6 0x00000116 181 #define MSR_IDT_MCR7 0x00000117 182 #define MSR_IDT_MCR_CTRL 0x00000120 183 184 /* VIA Cyrix defined MSRs*/ 185 #define MSR_VIA_FCR 0x00001107 186 #define MSR_VIA_LONGHAUL 0x0000110a 187 #define MSR_VIA_RNG 0x0000110b 188 #define MSR_VIA_BCR2 0x00001147 189 190 /* Transmeta defined MSRs */ 191 #define MSR_TMTA_LONGRUN_CTRL 0x80868010 192 #define MSR_TMTA_LONGRUN_FLAGS 0x80868011 193 #define MSR_TMTA_LRTI_READOUT 0x80868018 194 #define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a 195 196 /* Intel defined MSRs. */ 197 #define MSR_IA32_P5_MC_ADDR 0x00000000 198 #define MSR_IA32_P5_MC_TYPE 0x00000001 199 #define MSR_IA32_TSC 0x00000010 200 #define MSR_IA32_PLATFORM_ID 0x00000017 201 #define MSR_IA32_EBL_CR_POWERON 0x0000002a 202 #define MSR_EBC_FREQUENCY_ID 0x0000002c 203 #define MSR_IA32_FEATURE_CONTROL 0x0000003a 204 205 #define FEATURE_CONTROL_LOCKED (1<<0) 206 #define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX (1<<1) 207 #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2) 208 209 #define MSR_IA32_APICBASE 0x0000001b 210 #define MSR_IA32_APICBASE_BSP (1<<8) 211 #define MSR_IA32_APICBASE_ENABLE (1<<11) 212 #define MSR_IA32_APICBASE_BASE (0xfffff<<12) 213 214 #define MSR_IA32_UCODE_WRITE 0x00000079 215 #define MSR_IA32_UCODE_REV 0x0000008b 216 217 #define MSR_IA32_PERF_STATUS 0x00000198 218 #define MSR_IA32_PERF_CTL 0x00000199 219 220 #define MSR_IA32_MPERF 0x000000e7 221 #define MSR_IA32_APERF 0x000000e8 222 223 #define MSR_IA32_THERM_CONTROL 0x0000019a 224 #define MSR_IA32_THERM_INTERRUPT 0x0000019b 225 226 #define THERM_INT_HIGH_ENABLE (1 << 0) 227 #define THERM_INT_LOW_ENABLE (1 << 1) 228 #define THERM_INT_PLN_ENABLE (1 << 24) 229 230 #define MSR_IA32_THERM_STATUS 0x0000019c 231 232 #define THERM_STATUS_PROCHOT (1 << 0) 233 #define THERM_STATUS_POWER_LIMIT (1 << 10) 234 235 #define MSR_THERM2_CTL 0x0000019d 236 237 #define MSR_THERM2_CTL_TM_SELECT (1ULL << 16) 238 239 #define MSR_IA32_MISC_ENABLE 0x000001a0 240 241 #define MSR_IA32_TEMPERATURE_TARGET 0x000001a2 242 243 #define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0 244 245 #define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1 246 247 #define PACKAGE_THERM_STATUS_PROCHOT (1 << 0) 248 #define PACKAGE_THERM_STATUS_POWER_LIMIT (1 << 10) 249 250 #define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001b2 251 252 #define PACKAGE_THERM_INT_HIGH_ENABLE (1 << 0) 253 #define PACKAGE_THERM_INT_LOW_ENABLE (1 << 1) 254 #define PACKAGE_THERM_INT_PLN_ENABLE (1 << 24) 255 256 /* MISC_ENABLE bits: architectural */ 257 #define MSR_IA32_MISC_ENABLE_FAST_STRING (1ULL << 0) 258 #define MSR_IA32_MISC_ENABLE_TCC (1ULL << 1) 259 #define MSR_IA32_MISC_ENABLE_EMON (1ULL << 7) 260 #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1ULL << 11) 261 #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1ULL << 12) 262 #define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP (1ULL << 16) 263 #define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << 18) 264 #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1ULL << 22) 265 #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1ULL << 23) 266 #define MSR_IA32_MISC_ENABLE_XD_DISABLE (1ULL << 34) 267 268 /* MISC_ENABLE bits: model-specific, meaning may vary from core to core */ 269 #define MSR_IA32_MISC_ENABLE_X87_COMPAT (1ULL << 2) 270 #define MSR_IA32_MISC_ENABLE_TM1 (1ULL << 3) 271 #define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE (1ULL << 4) 272 #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE (1ULL << 6) 273 #define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK (1ULL << 8) 274 #define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE (1ULL << 9) 275 #define MSR_IA32_MISC_ENABLE_FERR (1ULL << 10) 276 #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX (1ULL << 10) 277 #define MSR_IA32_MISC_ENABLE_TM2 (1ULL << 13) 278 #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE (1ULL << 19) 279 #define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK (1ULL << 20) 280 #define MSR_IA32_MISC_ENABLE_L1D_CONTEXT (1ULL << 24) 281 #define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE (1ULL << 37) 282 #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE (1ULL << 38) 283 #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << 39) 284 285 /* P4/Xeon+ specific */ 286 #define MSR_IA32_MCG_EAX 0x00000180 287 #define MSR_IA32_MCG_EBX 0x00000181 288 #define MSR_IA32_MCG_ECX 0x00000182 289 #define MSR_IA32_MCG_EDX 0x00000183 290 #define MSR_IA32_MCG_ESI 0x00000184 291 #define MSR_IA32_MCG_EDI 0x00000185 292 #define MSR_IA32_MCG_EBP 0x00000186 293 #define MSR_IA32_MCG_ESP 0x00000187 294 #define MSR_IA32_MCG_EFLAGS 0x00000188 295 #define MSR_IA32_MCG_EIP 0x00000189 296 #define MSR_IA32_MCG_RESERVED 0x0000018a 297 298 /* Pentium IV performance counter MSRs */ 299 #define MSR_P4_BPU_PERFCTR0 0x00000300 300 #define MSR_P4_BPU_PERFCTR1 0x00000301 301 #define MSR_P4_BPU_PERFCTR2 0x00000302 302 #define MSR_P4_BPU_PERFCTR3 0x00000303 303 #define MSR_P4_MS_PERFCTR0 0x00000304 304 #define MSR_P4_MS_PERFCTR1 0x00000305 305 #define MSR_P4_MS_PERFCTR2 0x00000306 306 #define MSR_P4_MS_PERFCTR3 0x00000307 307 #define MSR_P4_FLAME_PERFCTR0 0x00000308 308 #define MSR_P4_FLAME_PERFCTR1 0x00000309 309 #define MSR_P4_FLAME_PERFCTR2 0x0000030a 310 #define MSR_P4_FLAME_PERFCTR3 0x0000030b 311 #define MSR_P4_IQ_PERFCTR0 0x0000030c 312 #define MSR_P4_IQ_PERFCTR1 0x0000030d 313 #define MSR_P4_IQ_PERFCTR2 0x0000030e 314 #define MSR_P4_IQ_PERFCTR3 0x0000030f 315 #define MSR_P4_IQ_PERFCTR4 0x00000310 316 #define MSR_P4_IQ_PERFCTR5 0x00000311 317 #define MSR_P4_BPU_CCCR0 0x00000360 318 #define MSR_P4_BPU_CCCR1 0x00000361 319 #define MSR_P4_BPU_CCCR2 0x00000362 320 #define MSR_P4_BPU_CCCR3 0x00000363 321 #define MSR_P4_MS_CCCR0 0x00000364 322 #define MSR_P4_MS_CCCR1 0x00000365 323 #define MSR_P4_MS_CCCR2 0x00000366 324 #define MSR_P4_MS_CCCR3 0x00000367 325 #define MSR_P4_FLAME_CCCR0 0x00000368 326 #define MSR_P4_FLAME_CCCR1 0x00000369 327 #define MSR_P4_FLAME_CCCR2 0x0000036a 328 #define MSR_P4_FLAME_CCCR3 0x0000036b 329 #define MSR_P4_IQ_CCCR0 0x0000036c 330 #define MSR_P4_IQ_CCCR1 0x0000036d 331 #define MSR_P4_IQ_CCCR2 0x0000036e 332 #define MSR_P4_IQ_CCCR3 0x0000036f 333 #define MSR_P4_IQ_CCCR4 0x00000370 334 #define MSR_P4_IQ_CCCR5 0x00000371 335 #define MSR_P4_ALF_ESCR0 0x000003ca 336 #define MSR_P4_ALF_ESCR1 0x000003cb 337 #define MSR_P4_BPU_ESCR0 0x000003b2 338 #define MSR_P4_BPU_ESCR1 0x000003b3 339 #define MSR_P4_BSU_ESCR0 0x000003a0 340 #define MSR_P4_BSU_ESCR1 0x000003a1 341 #define MSR_P4_CRU_ESCR0 0x000003b8 342 #define MSR_P4_CRU_ESCR1 0x000003b9 343 #define MSR_P4_CRU_ESCR2 0x000003cc 344 #define MSR_P4_CRU_ESCR3 0x000003cd 345 #define MSR_P4_CRU_ESCR4 0x000003e0 346 #define MSR_P4_CRU_ESCR5 0x000003e1 347 #define MSR_P4_DAC_ESCR0 0x000003a8 348 #define MSR_P4_DAC_ESCR1 0x000003a9 349 #define MSR_P4_FIRM_ESCR0 0x000003a4 350 #define MSR_P4_FIRM_ESCR1 0x000003a5 351 #define MSR_P4_FLAME_ESCR0 0x000003a6 352 #define MSR_P4_FLAME_ESCR1 0x000003a7 353 #define MSR_P4_FSB_ESCR0 0x000003a2 354 #define MSR_P4_FSB_ESCR1 0x000003a3 355 #define MSR_P4_IQ_ESCR0 0x000003ba 356 #define MSR_P4_IQ_ESCR1 0x000003bb 357 #define MSR_P4_IS_ESCR0 0x000003b4 358 #define MSR_P4_IS_ESCR1 0x000003b5 359 #define MSR_P4_ITLB_ESCR0 0x000003b6 360 #define MSR_P4_ITLB_ESCR1 0x000003b7 361 #define MSR_P4_IX_ESCR0 0x000003c8 362 #define MSR_P4_IX_ESCR1 0x000003c9 363 #define MSR_P4_MOB_ESCR0 0x000003aa 364 #define MSR_P4_MOB_ESCR1 0x000003ab 365 #define MSR_P4_MS_ESCR0 0x000003c0 366 #define MSR_P4_MS_ESCR1 0x000003c1 367 #define MSR_P4_PMH_ESCR0 0x000003ac 368 #define MSR_P4_PMH_ESCR1 0x000003ad 369 #define MSR_P4_RAT_ESCR0 0x000003bc 370 #define MSR_P4_RAT_ESCR1 0x000003bd 371 #define MSR_P4_SAAT_ESCR0 0x000003ae 372 #define MSR_P4_SAAT_ESCR1 0x000003af 373 #define MSR_P4_SSU_ESCR0 0x000003be 374 #define MSR_P4_SSU_ESCR1 0x000003bf /* guess: not in manual */ 375 376 #define MSR_P4_TBPU_ESCR0 0x000003c2 377 #define MSR_P4_TBPU_ESCR1 0x000003c3 378 #define MSR_P4_TC_ESCR0 0x000003c4 379 #define MSR_P4_TC_ESCR1 0x000003c5 380 #define MSR_P4_U2L_ESCR0 0x000003b0 381 #define MSR_P4_U2L_ESCR1 0x000003b1 382 383 #define MSR_P4_PEBS_MATRIX_VERT 0x000003f2 384 385 /* Intel Core-based CPU performance counters */ 386 #define MSR_CORE_PERF_FIXED_CTR0 0x00000309 387 #define MSR_CORE_PERF_FIXED_CTR1 0x0000030a 388 #define MSR_CORE_PERF_FIXED_CTR2 0x0000030b 389 #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x0000038d 390 #define MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e 391 #define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f 392 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390 393 394 /* Geode defined MSRs */ 395 #define MSR_GEODE_BUSCONT_CONF0 0x00001900 396 397 /* Intel VT MSRs */ 398 #define MSR_IA32_VMX_BASIC 0x00000480 399 #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481 400 #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482 401 #define MSR_IA32_VMX_EXIT_CTLS 0x00000483 402 #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484 403 #define MSR_IA32_VMX_MISC 0x00000485 404 #define MSR_IA32_VMX_CR0_FIXED0 0x00000486 405 #define MSR_IA32_VMX_CR0_FIXED1 0x00000487 406 #define MSR_IA32_VMX_CR4_FIXED0 0x00000488 407 #define MSR_IA32_VMX_CR4_FIXED1 0x00000489 408 #define MSR_IA32_VMX_VMCS_ENUM 0x0000048a 409 #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b 410 #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c 411 412 /* AMD-V MSRs */ 413 414 #define MSR_VM_CR 0xc0010114 415 #define MSR_VM_IGNNE 0xc0010115 416 #define MSR_VM_HSAVE_PA 0xc0010117 417 418 #endif /* _ASM_X86_MSR_INDEX_H */ 419