xref: /linux/arch/x86/include/asm/microcode.h (revision bdf4d8280616308b5bb42babad1432ff4575cb8b)
1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _ASM_X86_MICROCODE_H
3 #define _ASM_X86_MICROCODE_H
4 
5 #include <asm/msr.h>
6 #include <asm/cpuid/api.h>
7 
8 struct cpu_signature {
9 	unsigned int sig;
10 	unsigned int pf;
11 	unsigned int rev;
12 };
13 
14 struct ucode_cpu_info {
15 	struct cpu_signature	cpu_sig;
16 	void			*mc;
17 };
18 
19 #ifdef CONFIG_MICROCODE
20 void load_ucode_bsp(void);
21 void load_ucode_ap(void);
22 void microcode_bsp_resume(void);
23 bool __init microcode_loader_disabled(void);
24 #else
25 static inline void load_ucode_bsp(void)	{ }
26 static inline void load_ucode_ap(void) { }
27 static inline void microcode_bsp_resume(void) { }
28 static inline bool __init microcode_loader_disabled(void) { return false; }
29 #endif
30 
31 extern unsigned long initrd_start_early;
32 
33 #ifdef CONFIG_CPU_SUP_INTEL
34 /* Intel specific microcode defines. Public for IFS */
35 struct microcode_header_intel {
36 	unsigned int	hdrver;
37 	unsigned int	rev;
38 	unsigned int	date;
39 	unsigned int	sig;
40 	unsigned int	cksum;
41 	unsigned int	ldrver;
42 	unsigned int	pf;
43 	unsigned int	datasize;
44 	unsigned int	totalsize;
45 	unsigned int	metasize;
46 	unsigned int	min_req_ver;
47 	unsigned int	reserved;
48 };
49 
50 struct microcode_intel {
51 	struct microcode_header_intel	hdr;
52 	unsigned int			bits[];
53 };
54 
55 #define DEFAULT_UCODE_DATASIZE		(2000)
56 #define MC_HEADER_SIZE			(sizeof(struct microcode_header_intel))
57 #define MC_HEADER_TYPE_MICROCODE	1
58 #define MC_HEADER_TYPE_IFS		2
59 
60 static inline int intel_microcode_get_datasize(struct microcode_header_intel *hdr)
61 {
62 	return hdr->datasize ? : DEFAULT_UCODE_DATASIZE;
63 }
64 
65 extern u32 intel_get_platform_id(void);
66 
67 static inline u32 intel_get_microcode_revision(void)
68 {
69 	u32 rev, dummy;
70 
71 	native_wrmsrq(MSR_IA32_UCODE_REV, 0);
72 
73 	/* As documented in the SDM: Do a CPUID 1 here */
74 	native_cpuid_eax(1);
75 
76 	/* get the current revision from MSR 0x8B */
77 	native_rdmsr(MSR_IA32_UCODE_REV, dummy, rev);
78 
79 	return rev;
80 }
81 #endif /* !CONFIG_CPU_SUP_INTEL */
82 
83 bool microcode_nmi_handler(void);
84 void microcode_offline_nmi_handler(void);
85 
86 #ifdef CONFIG_MICROCODE_LATE_LOADING
87 DECLARE_STATIC_KEY_FALSE(microcode_nmi_handler_enable);
88 static __always_inline bool microcode_nmi_handler_enabled(void)
89 {
90 	return static_branch_unlikely(&microcode_nmi_handler_enable);
91 }
92 #else
93 static __always_inline bool microcode_nmi_handler_enabled(void) { return false; }
94 #endif
95 
96 #endif /* _ASM_X86_MICROCODE_H */
97