1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _ASM_X86_MCE_H 3 #define _ASM_X86_MCE_H 4 5 #include <uapi/asm/mce.h> 6 7 /* 8 * Machine Check support for x86 9 */ 10 11 /* MCG_CAP register defines */ 12 #define MCG_BANKCNT_MASK 0xff /* Number of Banks */ 13 #define MCG_CTL_P BIT_ULL(8) /* MCG_CTL register available */ 14 #define MCG_EXT_P BIT_ULL(9) /* Extended registers available */ 15 #define MCG_CMCI_P BIT_ULL(10) /* CMCI supported */ 16 #define MCG_TES_P BIT_ULL(11) /* Threshold-based error status supported */ 17 #define MCG_SEAM_NR BIT_ULL(12) /* MCG_STATUS_SEAM_NR supported */ 18 #define MCG_EXT_CNT_MASK 0xff0000 /* Number of Extended registers */ 19 #define MCG_EXT_CNT_SHIFT 16 20 #define MCG_EXT_CNT(c) (((c) & MCG_EXT_CNT_MASK) >> MCG_EXT_CNT_SHIFT) 21 #define MCG_SER_P BIT_ULL(24) /* MCA recovery/new status bits */ 22 #define MCG_ELOG_P BIT_ULL(26) /* Extended error log supported */ 23 #define MCG_LMCE_P BIT_ULL(27) /* Local machine check supported */ 24 25 /* MCG_STATUS register defines */ 26 #define MCG_STATUS_RIPV BIT_ULL(0) /* restart ip valid */ 27 #define MCG_STATUS_EIPV BIT_ULL(1) /* ip points to correct instruction */ 28 #define MCG_STATUS_MCIP BIT_ULL(2) /* machine check in progress */ 29 #define MCG_STATUS_LMCES BIT_ULL(3) /* LMCE signaled */ 30 #define MCG_STATUS_SEAM_NR BIT_ULL(12) /* Machine check inside SEAM non-root mode */ 31 32 /* MCG_EXT_CTL register defines */ 33 #define MCG_EXT_CTL_LMCE_EN BIT_ULL(0) /* Enable LMCE */ 34 35 /* MCi_STATUS register defines */ 36 #define MCI_STATUS_VAL BIT_ULL(63) /* valid error */ 37 #define MCI_STATUS_OVER BIT_ULL(62) /* previous errors lost */ 38 #define MCI_STATUS_UC BIT_ULL(61) /* uncorrected error */ 39 #define MCI_STATUS_EN BIT_ULL(60) /* error enabled */ 40 #define MCI_STATUS_MISCV BIT_ULL(59) /* misc error reg. valid */ 41 #define MCI_STATUS_ADDRV BIT_ULL(58) /* addr reg. valid */ 42 #define MCI_STATUS_PCC BIT_ULL(57) /* processor context corrupt */ 43 #define MCI_STATUS_S BIT_ULL(56) /* Signaled machine check */ 44 #define MCI_STATUS_AR BIT_ULL(55) /* Action required */ 45 #define MCI_STATUS_TES_MASK GENMASK_ULL(54, 53) 46 #define MCI_STATUS_TES(s) FIELD_GET(MCI_STATUS_TES_MASK, s) 47 #define MCI_STATUS_TES_GREEN 1 /* Threshold-based errors below threshold */ 48 #define MCI_STATUS_TES_YELLOW 2 /* Threshold-based errors above threshold */ 49 #define MCI_STATUS_CEC_SHIFT 38 /* Corrected Error Count */ 50 #define MCI_STATUS_CEC_MASK GENMASK_ULL(52,38) 51 #define MCI_STATUS_CEC(c) (((c) & MCI_STATUS_CEC_MASK) >> MCI_STATUS_CEC_SHIFT) 52 #define MCI_STATUS_MSCOD(m) (((m) >> 16) & 0xffff) 53 54 /* AMD-specific bits */ 55 #define MCI_STATUS_TCC BIT_ULL(55) /* Task context corrupt */ 56 #define MCI_STATUS_PADDRV BIT_ULL(54) /* Valid System Physical Address */ 57 #define MCI_STATUS_SYNDV BIT_ULL(53) /* synd reg. valid */ 58 #define MCI_STATUS_DEFERRED BIT_ULL(44) /* uncorrected error, deferred exception */ 59 #define MCI_STATUS_POISON BIT_ULL(43) /* access poisonous data */ 60 #define MCI_STATUS_SCRUB BIT_ULL(40) /* Error detected during scrub operation */ 61 62 /* 63 * McaX field if set indicates a given bank supports MCA extensions: 64 * - Deferred error interrupt type is specifiable by bank. 65 * - MCx_MISC0[BlkPtr] field indicates presence of extended MISC registers, 66 * But should not be used to determine MSR numbers. 67 * - TCC bit is present in MCx_STATUS. 68 */ 69 #define MCI_CONFIG_MCAX 0x1 70 #define MCI_CONFIG_FRUTEXT BIT_ULL(9) 71 #define MCI_CONFIG_PADDRV BIT_ULL(11) 72 #define MCI_IPID_MCATYPE 0xFFFF0000 73 #define MCI_IPID_HWID 0xFFF 74 75 /* 76 * Note that the full MCACOD field of IA32_MCi_STATUS MSR is 77 * bits 15:0. But bit 12 is the 'F' bit, defined for corrected 78 * errors to indicate that errors are being filtered by hardware. 79 * We should mask out bit 12 when looking for specific signatures 80 * of uncorrected errors - so the F bit is deliberately skipped 81 * in this #define. 82 */ 83 #define MCACOD 0xefff /* MCA Error Code */ 84 85 /* Architecturally defined codes from SDM Vol. 3B Chapter 15 */ 86 #define MCACOD_SCRUB 0x00C0 /* 0xC0-0xCF Memory Scrubbing */ 87 #define MCACOD_SCRUBMSK 0xeff0 /* Skip bit 12 ('F' bit) */ 88 #define MCACOD_L3WB 0x017A /* L3 Explicit Writeback */ 89 #define MCACOD_DATA 0x0134 /* Data Load */ 90 #define MCACOD_INSTR 0x0150 /* Instruction Fetch */ 91 92 /* MCi_MISC register defines */ 93 #define MCI_MISC_ADDR_LSB(m) ((m) & 0x3f) 94 #define MCI_MISC_ADDR_MODE(m) (((m) >> 6) & 7) 95 #define MCI_MISC_ADDR_SEGOFF 0 /* segment offset */ 96 #define MCI_MISC_ADDR_LINEAR 1 /* linear address */ 97 #define MCI_MISC_ADDR_PHYS 2 /* physical address */ 98 #define MCI_MISC_ADDR_MEM 3 /* memory address */ 99 #define MCI_MISC_ADDR_GENERIC 7 /* generic */ 100 101 /* MCi_ADDR register defines */ 102 #define MCI_ADDR_PHYSADDR GENMASK_ULL(boot_cpu_data.x86_phys_bits - 1, 0) 103 104 /* CTL2 register defines */ 105 #define MCI_CTL2_CMCI_EN BIT_ULL(30) 106 #define MCI_CTL2_CMCI_THRESHOLD_MASK 0x7fffULL 107 108 #define MCJ_CTX_MASK 3 109 #define MCJ_CTX(flags) ((flags) & MCJ_CTX_MASK) 110 #define MCJ_CTX_RANDOM 0 /* inject context: random */ 111 #define MCJ_CTX_PROCESS 0x1 /* inject context: process */ 112 #define MCJ_CTX_IRQ 0x2 /* inject context: IRQ */ 113 #define MCJ_NMI_BROADCAST 0x4 /* do NMI broadcasting */ 114 #define MCJ_EXCEPTION 0x8 /* raise as exception */ 115 #define MCJ_IRQ_BROADCAST 0x10 /* do IRQ broadcasting */ 116 117 #define MCE_OVERFLOW 0 /* bit 0 in flags means overflow */ 118 119 #define MCE_LOG_MIN_LEN 32U 120 #define MCE_LOG_SIGNATURE "MACHINECHECK" 121 122 /* AMD Scalable MCA */ 123 #define MSR_AMD64_SMCA_MC0_CTL 0xc0002000 124 #define MSR_AMD64_SMCA_MC0_STATUS 0xc0002001 125 #define MSR_AMD64_SMCA_MC0_ADDR 0xc0002002 126 #define MSR_AMD64_SMCA_MC0_MISC0 0xc0002003 127 #define MSR_AMD64_SMCA_MC0_CONFIG 0xc0002004 128 #define MSR_AMD64_SMCA_MC0_IPID 0xc0002005 129 #define MSR_AMD64_SMCA_MC0_SYND 0xc0002006 130 #define MSR_AMD64_SMCA_MC0_DESTAT 0xc0002008 131 #define MSR_AMD64_SMCA_MC0_DEADDR 0xc0002009 132 #define MSR_AMD64_SMCA_MC0_MISC1 0xc000200a 133 /* Registers MISC2 to MISC4 are at offsets B to D. */ 134 #define MSR_AMD64_SMCA_MC0_SYND1 0xc000200e 135 #define MSR_AMD64_SMCA_MC0_SYND2 0xc000200f 136 #define MSR_AMD64_SMCA_MCx_CTL(x) (MSR_AMD64_SMCA_MC0_CTL + 0x10*(x)) 137 #define MSR_AMD64_SMCA_MCx_STATUS(x) (MSR_AMD64_SMCA_MC0_STATUS + 0x10*(x)) 138 #define MSR_AMD64_SMCA_MCx_ADDR(x) (MSR_AMD64_SMCA_MC0_ADDR + 0x10*(x)) 139 #define MSR_AMD64_SMCA_MCx_MISC(x) (MSR_AMD64_SMCA_MC0_MISC0 + 0x10*(x)) 140 #define MSR_AMD64_SMCA_MCx_CONFIG(x) (MSR_AMD64_SMCA_MC0_CONFIG + 0x10*(x)) 141 #define MSR_AMD64_SMCA_MCx_IPID(x) (MSR_AMD64_SMCA_MC0_IPID + 0x10*(x)) 142 #define MSR_AMD64_SMCA_MCx_SYND(x) (MSR_AMD64_SMCA_MC0_SYND + 0x10*(x)) 143 #define MSR_AMD64_SMCA_MCx_DESTAT(x) (MSR_AMD64_SMCA_MC0_DESTAT + 0x10*(x)) 144 #define MSR_AMD64_SMCA_MCx_DEADDR(x) (MSR_AMD64_SMCA_MC0_DEADDR + 0x10*(x)) 145 #define MSR_AMD64_SMCA_MCx_MISCy(x, y) ((MSR_AMD64_SMCA_MC0_MISC1 + y) + (0x10*(x))) 146 #define MSR_AMD64_SMCA_MCx_SYND1(x) (MSR_AMD64_SMCA_MC0_SYND1 + 0x10*(x)) 147 #define MSR_AMD64_SMCA_MCx_SYND2(x) (MSR_AMD64_SMCA_MC0_SYND2 + 0x10*(x)) 148 149 #define XEC(x, mask) (((x) >> 16) & mask) 150 151 /* mce.kflags flag bits for logging etc. */ 152 #define MCE_HANDLED_CEC BIT_ULL(0) 153 #define MCE_HANDLED_UC BIT_ULL(1) 154 #define MCE_HANDLED_EXTLOG BIT_ULL(2) 155 #define MCE_HANDLED_NFIT BIT_ULL(3) 156 #define MCE_HANDLED_EDAC BIT_ULL(4) 157 #define MCE_HANDLED_MCELOG BIT_ULL(5) 158 159 /* 160 * Indicates an MCE which has happened in kernel space but from 161 * which the kernel can recover simply by executing fixup_exception() 162 * so that an error is returned to the caller of the function that 163 * hit the machine check. 164 */ 165 #define MCE_IN_KERNEL_RECOV BIT_ULL(6) 166 167 /* 168 * Indicates an MCE that happened in kernel space while copying data 169 * from user. In this case fixup_exception() gets the kernel to the 170 * error exit for the copy function. Machine check handler can then 171 * treat it like a fault taken in user mode. 172 */ 173 #define MCE_IN_KERNEL_COPYIN BIT_ULL(7) 174 175 /* 176 * Indicates that handler should check and clear Deferred error registers 177 * rather than common ones. 178 */ 179 #define MCE_CHECK_DFR_REGS BIT_ULL(8) 180 181 /* 182 * This structure contains all data related to the MCE log. Also 183 * carries a signature to make it easier to find from external 184 * debugging tools. Each entry is only valid when its finished flag 185 * is set. 186 */ 187 struct mce_log_buffer { 188 char signature[12]; /* "MACHINECHECK" */ 189 unsigned len; /* = elements in .mce_entry[] */ 190 unsigned next; 191 unsigned flags; 192 unsigned recordlen; /* length of struct mce */ 193 struct mce entry[]; 194 }; 195 196 /* Highest last */ 197 enum mce_notifier_prios { 198 MCE_PRIO_LOWEST, 199 MCE_PRIO_MCELOG, 200 MCE_PRIO_EDAC, 201 MCE_PRIO_NFIT, 202 MCE_PRIO_EXTLOG, 203 MCE_PRIO_UC, 204 MCE_PRIO_EARLY, 205 MCE_PRIO_CEC, 206 MCE_PRIO_HIGHEST = MCE_PRIO_CEC 207 }; 208 209 /** 210 * struct mce_hw_err - Hardware Error Record. 211 * @m: Machine Check record. 212 * @vendor: Vendor-specific error information. 213 * 214 * Vendor-specific fields should not be added to struct mce. Instead, vendors 215 * should export their vendor-specific data through their structure in the 216 * vendor union below. 217 * 218 * AMD's vendor data is parsed by error decoding tools for supplemental error 219 * information. Thus, current offsets of existing fields must be maintained. 220 * Only add new fields at the end of AMD's vendor structure. 221 */ 222 struct mce_hw_err { 223 struct mce m; 224 225 union vendor_info { 226 struct { 227 u64 synd1; /* MCA_SYND1 MSR */ 228 u64 synd2; /* MCA_SYND2 MSR */ 229 } amd; 230 } vendor; 231 }; 232 233 #define to_mce_hw_err(mce) container_of(mce, struct mce_hw_err, m) 234 235 struct notifier_block; 236 extern void mce_register_decode_chain(struct notifier_block *nb); 237 extern void mce_unregister_decode_chain(struct notifier_block *nb); 238 239 #include <linux/percpu.h> 240 #include <linux/atomic.h> 241 242 extern int mce_p5_enabled; 243 244 #ifdef CONFIG_ARCH_HAS_COPY_MC 245 extern void enable_copy_mc_fragile(void); 246 unsigned long __must_check copy_mc_fragile(void *dst, const void *src, unsigned cnt); 247 #else 248 static inline void enable_copy_mc_fragile(void) 249 { 250 } 251 #endif 252 253 struct cper_ia_proc_ctx; 254 255 #ifdef CONFIG_X86_MCE 256 int mcheck_init(void); 257 void mca_bsp_init(struct cpuinfo_x86 *c); 258 void mcheck_cpu_init(struct cpuinfo_x86 *c); 259 void mcheck_cpu_clear(struct cpuinfo_x86 *c); 260 int apei_smca_report_x86_error(struct cper_ia_proc_ctx *ctx_info, 261 u64 lapic_id); 262 #else 263 static inline int mcheck_init(void) { return 0; } 264 static inline void mca_bsp_init(struct cpuinfo_x86 *c) {} 265 static inline void mcheck_cpu_init(struct cpuinfo_x86 *c) {} 266 static inline void mcheck_cpu_clear(struct cpuinfo_x86 *c) {} 267 static inline int apei_smca_report_x86_error(struct cper_ia_proc_ctx *ctx_info, 268 u64 lapic_id) { return -EINVAL; } 269 #endif 270 271 void mce_prep_record(struct mce_hw_err *err); 272 void mce_log(struct mce_hw_err *err); 273 DECLARE_PER_CPU(struct device *, mce_device); 274 275 /* Maximum number of MCA banks per CPU. */ 276 #define MAX_NR_BANKS 64 277 278 #ifdef CONFIG_X86_MCE_INTEL 279 void mce_intel_feature_init(struct cpuinfo_x86 *c); 280 void mce_intel_feature_clear(struct cpuinfo_x86 *c); 281 void cmci_clear(void); 282 void cmci_reenable(void); 283 void cmci_rediscover(void); 284 void cmci_recheck(void); 285 #else 286 static inline void mce_intel_feature_init(struct cpuinfo_x86 *c) { } 287 static inline void mce_intel_feature_clear(struct cpuinfo_x86 *c) { } 288 static inline void cmci_clear(void) {} 289 static inline void cmci_reenable(void) {} 290 static inline void cmci_rediscover(void) {} 291 static inline void cmci_recheck(void) {} 292 #endif 293 294 bool mce_available(struct cpuinfo_x86 *c); 295 bool mce_is_memory_error(struct mce *m); 296 bool mce_is_correctable(struct mce *m); 297 bool mce_usable_address(struct mce *m); 298 299 typedef DECLARE_BITMAP(mce_banks_t, MAX_NR_BANKS); 300 DECLARE_PER_CPU(mce_banks_t, mce_poll_banks); 301 302 enum mcp_flags { 303 MCP_TIMESTAMP = BIT(0), /* log time stamp */ 304 MCP_UC = BIT(1), /* log uncorrected errors */ 305 MCP_QUEUE_LOG = BIT(2), /* only queue to genpool */ 306 }; 307 308 void machine_check_poll(enum mcp_flags flags, mce_banks_t *b); 309 310 DECLARE_PER_CPU(struct mce, injectm); 311 312 /* Disable CMCI/polling for MCA bank claimed by firmware */ 313 extern void mce_disable_bank(int bank); 314 315 #ifdef CONFIG_X86_MCE_THRESHOLD 316 void mce_save_apei_thr_limit(u32 thr_limit); 317 #else 318 static inline void mce_save_apei_thr_limit(u32 thr_limit) { } 319 #endif /* CONFIG_X86_MCE_THRESHOLD */ 320 321 /* 322 * Exception handler 323 */ 324 void do_machine_check(struct pt_regs *pt_regs); 325 326 /* 327 * Threshold handler 328 */ 329 extern void (*mce_threshold_vector)(void); 330 331 /* Deferred error interrupt handler */ 332 extern void (*deferred_error_int_vector)(void); 333 334 /* 335 * Used by APEI to report memory error via /dev/mcelog 336 */ 337 338 struct cper_sec_mem_err; 339 extern void apei_mce_report_mem_error(int corrected, 340 struct cper_sec_mem_err *mem_err); 341 342 /* 343 * Enumerate new IP types and HWID values in AMD processors which support 344 * Scalable MCA. 345 */ 346 #ifdef CONFIG_X86_MCE_AMD 347 348 /* 349 * These may be used by multiple smca_hwid_mcatypes. 350 * 351 * Keep in alphanumeric order, numerals before letters. 352 * Exception: Keep "V2, etc." with their originals. 353 */ 354 enum smca_bank_types { 355 SMCA_CS, /* Coherent Station */ 356 SMCA_CS_V2, 357 SMCA_DACC_BE, /* Data Acceleration Back-end */ 358 SMCA_DACC_FE, /* Data Acceleration Front-end */ 359 SMCA_DE, /* Decoder Unit */ 360 SMCA_EDDR5CMN, /* eDDR5 CMN */ 361 SMCA_EX, /* Execution Unit */ 362 SMCA_FP, /* Floating Point */ 363 SMCA_GMI_PCS, /* GMI PCS Unit */ 364 SMCA_GMI_PHY, /* GMI PHY Unit */ 365 SMCA_IF, /* Instruction Fetch */ 366 SMCA_L2_CACHE, /* L2 Cache */ 367 SMCA_L3_CACHE, /* L3 Cache */ 368 SMCA_LS, /* Load Store */ 369 SMCA_LS_V2, 370 SMCA_MA_LLC, /* Memory Attached Last Level Cache */ 371 SMCA_MP5, /* Microprocessor 5 Unit */ 372 SMCA_MPART, /* AMD Root of Trust Microprocessor */ 373 SMCA_MPASP, /* AMD Secure Processor */ 374 SMCA_MPASP_V2, 375 SMCA_MPDACC, /* MP for Data Acceleration */ 376 SMCA_MPDMA, /* MPDMA Unit */ 377 SMCA_MPM, /* Microprocessor Manageability Core */ 378 SMCA_MPRAS, /* MP for RAS */ 379 SMCA_NBIF, /* NBIF Unit */ 380 SMCA_NBIO, /* Northbridge IO Unit */ 381 SMCA_PB, /* Parameter Block */ 382 SMCA_PCIE, /* PCI Express Unit */ 383 SMCA_PCIE_V2, 384 SMCA_PCIE_PL, /* PCIe Link */ 385 SMCA_PIE, /* Power, Interrupts, etc. */ 386 SMCA_PSP, /* Platform Security Processor */ 387 SMCA_PSP_V2, 388 SMCA_RESERVED, /* Reserved */ 389 SMCA_SATA, /* SATA Unit */ 390 SMCA_SHUB, /* System HUB Unit */ 391 SMCA_SMU, /* System Management Unit */ 392 SMCA_SMU_V2, 393 SMCA_SSBDCI, /* Die to Die Interconnect */ 394 SMCA_UMC, /* Unified Memory Controller */ 395 SMCA_UMC_V2, 396 SMCA_USB, /* USB Unit */ 397 SMCA_USR_CP, /* Ultra Short Reach Control Plane Controller */ 398 SMCA_USR_DP, /* Ultra Short Reach Data Plane Controller */ 399 SMCA_WAFL_PHY, /* WAFL PHY Unit */ 400 SMCA_XGMI_PCS, /* xGMI PCS Unit */ 401 SMCA_XGMI_PHY, /* xGMI PHY Unit */ 402 N_SMCA_BANK_TYPES 403 }; 404 405 extern bool amd_mce_is_memory_error(struct mce *m); 406 407 void mce_amd_feature_init(struct cpuinfo_x86 *c); 408 enum smca_bank_types smca_get_bank_type(unsigned int cpu, unsigned int bank); 409 #else 410 static inline bool amd_mce_is_memory_error(struct mce *m) { return false; }; 411 static inline void mce_amd_feature_init(struct cpuinfo_x86 *c) { } 412 #endif 413 414 unsigned long copy_mc_fragile_handle_tail(char *to, char *from, unsigned len); 415 416 #endif /* _ASM_X86_MCE_H */ 417