1 #ifndef _ASM_X86_MCE_H 2 #define _ASM_X86_MCE_H 3 4 #include <uapi/asm/mce.h> 5 6 7 struct mca_config { 8 bool dont_log_ce; 9 bool cmci_disabled; 10 bool ignore_ce; 11 bool disabled; 12 bool ser; 13 bool bios_cmci_threshold; 14 u8 banks; 15 s8 bootlog; 16 int tolerant; 17 int monarch_timeout; 18 int panic_timeout; 19 u32 rip_msr; 20 }; 21 22 extern struct mca_config mca_cfg; 23 extern void mce_register_decode_chain(struct notifier_block *nb); 24 extern void mce_unregister_decode_chain(struct notifier_block *nb); 25 26 #include <linux/percpu.h> 27 #include <linux/init.h> 28 #include <linux/atomic.h> 29 30 extern int mce_p5_enabled; 31 32 #ifdef CONFIG_X86_MCE 33 int mcheck_init(void); 34 void mcheck_cpu_init(struct cpuinfo_x86 *c); 35 #else 36 static inline int mcheck_init(void) { return 0; } 37 static inline void mcheck_cpu_init(struct cpuinfo_x86 *c) {} 38 #endif 39 40 #ifdef CONFIG_X86_ANCIENT_MCE 41 void intel_p5_mcheck_init(struct cpuinfo_x86 *c); 42 void winchip_mcheck_init(struct cpuinfo_x86 *c); 43 static inline void enable_p5_mce(void) { mce_p5_enabled = 1; } 44 #else 45 static inline void intel_p5_mcheck_init(struct cpuinfo_x86 *c) {} 46 static inline void winchip_mcheck_init(struct cpuinfo_x86 *c) {} 47 static inline void enable_p5_mce(void) {} 48 #endif 49 50 void mce_setup(struct mce *m); 51 void mce_log(struct mce *m); 52 DECLARE_PER_CPU(struct device *, mce_device); 53 54 /* 55 * Maximum banks number. 56 * This is the limit of the current register layout on 57 * Intel CPUs. 58 */ 59 #define MAX_NR_BANKS 32 60 61 #ifdef CONFIG_X86_MCE_INTEL 62 void mce_intel_feature_init(struct cpuinfo_x86 *c); 63 void cmci_clear(void); 64 void cmci_reenable(void); 65 void cmci_rediscover(int dying); 66 void cmci_recheck(void); 67 #else 68 static inline void mce_intel_feature_init(struct cpuinfo_x86 *c) { } 69 static inline void cmci_clear(void) {} 70 static inline void cmci_reenable(void) {} 71 static inline void cmci_rediscover(int dying) {} 72 static inline void cmci_recheck(void) {} 73 #endif 74 75 #ifdef CONFIG_X86_MCE_AMD 76 void mce_amd_feature_init(struct cpuinfo_x86 *c); 77 #else 78 static inline void mce_amd_feature_init(struct cpuinfo_x86 *c) { } 79 #endif 80 81 int mce_available(struct cpuinfo_x86 *c); 82 83 DECLARE_PER_CPU(unsigned, mce_exception_count); 84 DECLARE_PER_CPU(unsigned, mce_poll_count); 85 86 extern atomic_t mce_entry; 87 88 typedef DECLARE_BITMAP(mce_banks_t, MAX_NR_BANKS); 89 DECLARE_PER_CPU(mce_banks_t, mce_poll_banks); 90 91 enum mcp_flags { 92 MCP_TIMESTAMP = (1 << 0), /* log time stamp */ 93 MCP_UC = (1 << 1), /* log uncorrected errors */ 94 MCP_DONTLOG = (1 << 2), /* only clear, don't log */ 95 }; 96 void machine_check_poll(enum mcp_flags flags, mce_banks_t *b); 97 98 int mce_notify_irq(void); 99 void mce_notify_process(void); 100 101 DECLARE_PER_CPU(struct mce, injectm); 102 103 extern void register_mce_write_callback(ssize_t (*)(struct file *filp, 104 const char __user *ubuf, 105 size_t usize, loff_t *off)); 106 107 /* 108 * Exception handler 109 */ 110 111 /* Call the installed machine check handler for this CPU setup. */ 112 extern void (*machine_check_vector)(struct pt_regs *, long error_code); 113 void do_machine_check(struct pt_regs *, long); 114 115 /* 116 * Threshold handler 117 */ 118 119 extern void (*mce_threshold_vector)(void); 120 extern void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu); 121 122 /* 123 * Thermal handler 124 */ 125 126 void intel_init_thermal(struct cpuinfo_x86 *c); 127 128 void mce_log_therm_throt_event(__u64 status); 129 130 /* Interrupt Handler for core thermal thresholds */ 131 extern int (*platform_thermal_notify)(__u64 msr_val); 132 133 #ifdef CONFIG_X86_THERMAL_VECTOR 134 extern void mcheck_intel_therm_init(void); 135 #else 136 static inline void mcheck_intel_therm_init(void) { } 137 #endif 138 139 /* 140 * Used by APEI to report memory error via /dev/mcelog 141 */ 142 143 struct cper_sec_mem_err; 144 extern void apei_mce_report_mem_error(int corrected, 145 struct cper_sec_mem_err *mem_err); 146 147 #endif /* _ASM_X86_MCE_H */ 148