1 #ifndef _ASM_X86_MCE_H 2 #define _ASM_X86_MCE_H 3 4 #include <linux/types.h> 5 #include <asm/ioctls.h> 6 7 /* 8 * Machine Check support for x86 9 */ 10 11 #define MCG_BANKCNT_MASK 0xff /* Number of Banks */ 12 #define MCG_CTL_P (1ULL<<8) /* MCG_CAP register available */ 13 #define MCG_EXT_P (1ULL<<9) /* Extended registers available */ 14 #define MCG_CMCI_P (1ULL<<10) /* CMCI supported */ 15 #define MCG_EXT_CNT_MASK 0xff0000 /* Number of Extended registers */ 16 #define MCG_EXT_CNT_SHIFT 16 17 #define MCG_EXT_CNT(c) (((c) & MCG_EXT_CNT_MASK) >> MCG_EXT_CNT_SHIFT) 18 #define MCG_SER_P (1ULL<<24) /* MCA recovery/new status bits */ 19 20 #define MCG_STATUS_RIPV (1ULL<<0) /* restart ip valid */ 21 #define MCG_STATUS_EIPV (1ULL<<1) /* ip points to correct instruction */ 22 #define MCG_STATUS_MCIP (1ULL<<2) /* machine check in progress */ 23 24 #define MCI_STATUS_VAL (1ULL<<63) /* valid error */ 25 #define MCI_STATUS_OVER (1ULL<<62) /* previous errors lost */ 26 #define MCI_STATUS_UC (1ULL<<61) /* uncorrected error */ 27 #define MCI_STATUS_EN (1ULL<<60) /* error enabled */ 28 #define MCI_STATUS_MISCV (1ULL<<59) /* misc error reg. valid */ 29 #define MCI_STATUS_ADDRV (1ULL<<58) /* addr reg. valid */ 30 #define MCI_STATUS_PCC (1ULL<<57) /* processor context corrupt */ 31 #define MCI_STATUS_S (1ULL<<56) /* Signaled machine check */ 32 #define MCI_STATUS_AR (1ULL<<55) /* Action required */ 33 34 /* MISC register defines */ 35 #define MCM_ADDR_SEGOFF 0 /* segment offset */ 36 #define MCM_ADDR_LINEAR 1 /* linear address */ 37 #define MCM_ADDR_PHYS 2 /* physical address */ 38 #define MCM_ADDR_MEM 3 /* memory address */ 39 #define MCM_ADDR_GENERIC 7 /* generic */ 40 41 /* Fields are zero when not available */ 42 struct mce { 43 __u64 status; 44 __u64 misc; 45 __u64 addr; 46 __u64 mcgstatus; 47 __u64 ip; 48 __u64 tsc; /* cpu time stamp counter */ 49 __u64 time; /* wall time_t when error was detected */ 50 __u8 cpuvendor; /* cpu vendor as encoded in system.h */ 51 __u8 pad1; 52 __u16 pad2; 53 __u32 cpuid; /* CPUID 1 EAX */ 54 __u8 cs; /* code segment */ 55 __u8 bank; /* machine check bank */ 56 __u8 cpu; /* cpu number; obsolete; use extcpu now */ 57 __u8 finished; /* entry is valid */ 58 __u32 extcpu; /* linux cpu number that detected the error */ 59 __u32 socketid; /* CPU socket ID */ 60 __u32 apicid; /* CPU initial apic ID */ 61 __u64 mcgcap; /* MCGCAP MSR: machine check capabilities of CPU */ 62 }; 63 64 /* 65 * This structure contains all data related to the MCE log. Also 66 * carries a signature to make it easier to find from external 67 * debugging tools. Each entry is only valid when its finished flag 68 * is set. 69 */ 70 71 #define MCE_LOG_LEN 32 72 73 struct mce_log { 74 char signature[12]; /* "MACHINECHECK" */ 75 unsigned len; /* = MCE_LOG_LEN */ 76 unsigned next; 77 unsigned flags; 78 unsigned recordlen; /* length of struct mce */ 79 struct mce entry[MCE_LOG_LEN]; 80 }; 81 82 #define MCE_OVERFLOW 0 /* bit 0 in flags means overflow */ 83 84 #define MCE_LOG_SIGNATURE "MACHINECHECK" 85 86 #define MCE_GET_RECORD_LEN _IOR('M', 1, int) 87 #define MCE_GET_LOG_LEN _IOR('M', 2, int) 88 #define MCE_GETCLEAR_FLAGS _IOR('M', 3, int) 89 90 /* Software defined banks */ 91 #define MCE_EXTENDED_BANK 128 92 #define MCE_THERMAL_BANK MCE_EXTENDED_BANK + 0 93 94 #define K8_MCE_THRESHOLD_BASE (MCE_EXTENDED_BANK + 1) /* MCE_AMD */ 95 #define K8_MCE_THRESHOLD_BANK_0 (MCE_THRESHOLD_BASE + 0 * 9) 96 #define K8_MCE_THRESHOLD_BANK_1 (MCE_THRESHOLD_BASE + 1 * 9) 97 #define K8_MCE_THRESHOLD_BANK_2 (MCE_THRESHOLD_BASE + 2 * 9) 98 #define K8_MCE_THRESHOLD_BANK_3 (MCE_THRESHOLD_BASE + 3 * 9) 99 #define K8_MCE_THRESHOLD_BANK_4 (MCE_THRESHOLD_BASE + 4 * 9) 100 #define K8_MCE_THRESHOLD_BANK_5 (MCE_THRESHOLD_BASE + 5 * 9) 101 #define K8_MCE_THRESHOLD_DRAM_ECC (MCE_THRESHOLD_BANK_4 + 0) 102 103 #ifdef __KERNEL__ 104 105 #include <linux/percpu.h> 106 #include <linux/init.h> 107 #include <asm/atomic.h> 108 109 extern int mce_disabled; 110 extern int mce_p5_enabled; 111 112 #ifdef CONFIG_X86_MCE 113 void mcheck_init(struct cpuinfo_x86 *c); 114 #else 115 static inline void mcheck_init(struct cpuinfo_x86 *c) {} 116 #endif 117 118 #ifdef CONFIG_X86_OLD_MCE 119 extern int nr_mce_banks; 120 void amd_mcheck_init(struct cpuinfo_x86 *c); 121 void intel_p4_mcheck_init(struct cpuinfo_x86 *c); 122 void intel_p6_mcheck_init(struct cpuinfo_x86 *c); 123 #endif 124 125 #ifdef CONFIG_X86_ANCIENT_MCE 126 void intel_p5_mcheck_init(struct cpuinfo_x86 *c); 127 void winchip_mcheck_init(struct cpuinfo_x86 *c); 128 static inline void enable_p5_mce(void) { mce_p5_enabled = 1; } 129 #else 130 static inline void intel_p5_mcheck_init(struct cpuinfo_x86 *c) {} 131 static inline void winchip_mcheck_init(struct cpuinfo_x86 *c) {} 132 static inline void enable_p5_mce(void) {} 133 #endif 134 135 void mce_setup(struct mce *m); 136 void mce_log(struct mce *m); 137 DECLARE_PER_CPU(struct sys_device, mce_dev); 138 139 /* 140 * To support more than 128 would need to escape the predefined 141 * Linux defined extended banks first. 142 */ 143 #define MAX_NR_BANKS (MCE_EXTENDED_BANK - 1) 144 145 #ifdef CONFIG_X86_MCE_INTEL 146 extern int mce_cmci_disabled; 147 extern int mce_ignore_ce; 148 void mce_intel_feature_init(struct cpuinfo_x86 *c); 149 void cmci_clear(void); 150 void cmci_reenable(void); 151 void cmci_rediscover(int dying); 152 void cmci_recheck(void); 153 #else 154 static inline void mce_intel_feature_init(struct cpuinfo_x86 *c) { } 155 static inline void cmci_clear(void) {} 156 static inline void cmci_reenable(void) {} 157 static inline void cmci_rediscover(int dying) {} 158 static inline void cmci_recheck(void) {} 159 #endif 160 161 #ifdef CONFIG_X86_MCE_AMD 162 void mce_amd_feature_init(struct cpuinfo_x86 *c); 163 #else 164 static inline void mce_amd_feature_init(struct cpuinfo_x86 *c) { } 165 #endif 166 167 int mce_available(struct cpuinfo_x86 *c); 168 169 DECLARE_PER_CPU(unsigned, mce_exception_count); 170 DECLARE_PER_CPU(unsigned, mce_poll_count); 171 172 extern atomic_t mce_entry; 173 174 typedef DECLARE_BITMAP(mce_banks_t, MAX_NR_BANKS); 175 DECLARE_PER_CPU(mce_banks_t, mce_poll_banks); 176 177 enum mcp_flags { 178 MCP_TIMESTAMP = (1 << 0), /* log time stamp */ 179 MCP_UC = (1 << 1), /* log uncorrected errors */ 180 MCP_DONTLOG = (1 << 2), /* only clear, don't log */ 181 }; 182 void machine_check_poll(enum mcp_flags flags, mce_banks_t *b); 183 184 int mce_notify_irq(void); 185 void mce_notify_process(void); 186 187 DECLARE_PER_CPU(struct mce, injectm); 188 extern struct file_operations mce_chrdev_ops; 189 190 /* 191 * Exception handler 192 */ 193 194 /* Call the installed machine check handler for this CPU setup. */ 195 extern void (*machine_check_vector)(struct pt_regs *, long error_code); 196 void do_machine_check(struct pt_regs *, long); 197 198 /* 199 * Threshold handler 200 */ 201 202 extern void (*mce_threshold_vector)(void); 203 extern void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu); 204 205 /* 206 * Thermal handler 207 */ 208 209 void intel_init_thermal(struct cpuinfo_x86 *c); 210 211 #ifdef CONFIG_X86_NEW_MCE 212 void mce_log_therm_throt_event(__u64 status); 213 #else 214 static inline void mce_log_therm_throt_event(__u64 status) {} 215 #endif 216 217 #endif /* __KERNEL__ */ 218 #endif /* _ASM_X86_MCE_H */ 219