1 /* 2 * Kernel-based Virtual Machine driver for Linux 3 * 4 * This header defines architecture specific interfaces, x86 version 5 * 6 * This work is licensed under the terms of the GNU GPL, version 2. See 7 * the COPYING file in the top-level directory. 8 * 9 */ 10 11 #ifndef _ASM_X86_KVM_HOST_H 12 #define _ASM_X86_KVM_HOST_H 13 14 #include <linux/types.h> 15 #include <linux/mm.h> 16 #include <linux/mmu_notifier.h> 17 #include <linux/tracepoint.h> 18 #include <linux/cpumask.h> 19 #include <linux/irq_work.h> 20 21 #include <linux/kvm.h> 22 #include <linux/kvm_para.h> 23 #include <linux/kvm_types.h> 24 #include <linux/perf_event.h> 25 #include <linux/pvclock_gtod.h> 26 #include <linux/clocksource.h> 27 #include <linux/irqbypass.h> 28 #include <linux/hyperv.h> 29 30 #include <asm/apic.h> 31 #include <asm/pvclock-abi.h> 32 #include <asm/desc.h> 33 #include <asm/mtrr.h> 34 #include <asm/msr-index.h> 35 #include <asm/asm.h> 36 #include <asm/kvm_page_track.h> 37 38 #define KVM_MAX_VCPUS 288 39 #define KVM_SOFT_MAX_VCPUS 240 40 #define KVM_MAX_VCPU_ID 1023 41 #define KVM_USER_MEM_SLOTS 509 42 /* memory slots that are not exposed to userspace */ 43 #define KVM_PRIVATE_MEM_SLOTS 3 44 #define KVM_MEM_SLOTS_NUM (KVM_USER_MEM_SLOTS + KVM_PRIVATE_MEM_SLOTS) 45 46 #define KVM_HALT_POLL_NS_DEFAULT 200000 47 48 #define KVM_IRQCHIP_NUM_PINS KVM_IOAPIC_NUM_PINS 49 50 /* x86-specific vcpu->requests bit members */ 51 #define KVM_REQ_MIGRATE_TIMER 8 52 #define KVM_REQ_REPORT_TPR_ACCESS 9 53 #define KVM_REQ_TRIPLE_FAULT 10 54 #define KVM_REQ_MMU_SYNC 11 55 #define KVM_REQ_CLOCK_UPDATE 12 56 #define KVM_REQ_EVENT 14 57 #define KVM_REQ_APF_HALT 15 58 #define KVM_REQ_STEAL_UPDATE 16 59 #define KVM_REQ_NMI 17 60 #define KVM_REQ_PMU 18 61 #define KVM_REQ_PMI 19 62 #define KVM_REQ_SMI 20 63 #define KVM_REQ_MASTERCLOCK_UPDATE 21 64 #define KVM_REQ_MCLOCK_INPROGRESS (22 | KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP) 65 #define KVM_REQ_SCAN_IOAPIC (23 | KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP) 66 #define KVM_REQ_GLOBAL_CLOCK_UPDATE 24 67 #define KVM_REQ_APIC_PAGE_RELOAD (25 | KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP) 68 #define KVM_REQ_HV_CRASH 26 69 #define KVM_REQ_IOAPIC_EOI_EXIT 27 70 #define KVM_REQ_HV_RESET 28 71 #define KVM_REQ_HV_EXIT 29 72 #define KVM_REQ_HV_STIMER 30 73 74 #define CR0_RESERVED_BITS \ 75 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \ 76 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \ 77 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG)) 78 79 #define CR3_L_MODE_RESERVED_BITS 0xFFFFFF0000000000ULL 80 #define CR3_PCID_INVD BIT_64(63) 81 #define CR4_RESERVED_BITS \ 82 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\ 83 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \ 84 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR | X86_CR4_PCIDE \ 85 | X86_CR4_OSXSAVE | X86_CR4_SMEP | X86_CR4_FSGSBASE \ 86 | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE | X86_CR4_SMAP \ 87 | X86_CR4_PKE)) 88 89 #define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR) 90 91 92 93 #define INVALID_PAGE (~(hpa_t)0) 94 #define VALID_PAGE(x) ((x) != INVALID_PAGE) 95 96 #define UNMAPPED_GVA (~(gpa_t)0) 97 98 /* KVM Hugepage definitions for x86 */ 99 #define KVM_NR_PAGE_SIZES 3 100 #define KVM_HPAGE_GFN_SHIFT(x) (((x) - 1) * 9) 101 #define KVM_HPAGE_SHIFT(x) (PAGE_SHIFT + KVM_HPAGE_GFN_SHIFT(x)) 102 #define KVM_HPAGE_SIZE(x) (1UL << KVM_HPAGE_SHIFT(x)) 103 #define KVM_HPAGE_MASK(x) (~(KVM_HPAGE_SIZE(x) - 1)) 104 #define KVM_PAGES_PER_HPAGE(x) (KVM_HPAGE_SIZE(x) / PAGE_SIZE) 105 106 static inline gfn_t gfn_to_index(gfn_t gfn, gfn_t base_gfn, int level) 107 { 108 /* KVM_HPAGE_GFN_SHIFT(PT_PAGE_TABLE_LEVEL) must be 0. */ 109 return (gfn >> KVM_HPAGE_GFN_SHIFT(level)) - 110 (base_gfn >> KVM_HPAGE_GFN_SHIFT(level)); 111 } 112 113 #define KVM_PERMILLE_MMU_PAGES 20 114 #define KVM_MIN_ALLOC_MMU_PAGES 64 115 #define KVM_MMU_HASH_SHIFT 12 116 #define KVM_NUM_MMU_PAGES (1 << KVM_MMU_HASH_SHIFT) 117 #define KVM_MIN_FREE_MMU_PAGES 5 118 #define KVM_REFILL_PAGES 25 119 #define KVM_MAX_CPUID_ENTRIES 80 120 #define KVM_NR_FIXED_MTRR_REGION 88 121 #define KVM_NR_VAR_MTRR 8 122 123 #define ASYNC_PF_PER_VCPU 64 124 125 enum kvm_reg { 126 VCPU_REGS_RAX = 0, 127 VCPU_REGS_RCX = 1, 128 VCPU_REGS_RDX = 2, 129 VCPU_REGS_RBX = 3, 130 VCPU_REGS_RSP = 4, 131 VCPU_REGS_RBP = 5, 132 VCPU_REGS_RSI = 6, 133 VCPU_REGS_RDI = 7, 134 #ifdef CONFIG_X86_64 135 VCPU_REGS_R8 = 8, 136 VCPU_REGS_R9 = 9, 137 VCPU_REGS_R10 = 10, 138 VCPU_REGS_R11 = 11, 139 VCPU_REGS_R12 = 12, 140 VCPU_REGS_R13 = 13, 141 VCPU_REGS_R14 = 14, 142 VCPU_REGS_R15 = 15, 143 #endif 144 VCPU_REGS_RIP, 145 NR_VCPU_REGS 146 }; 147 148 enum kvm_reg_ex { 149 VCPU_EXREG_PDPTR = NR_VCPU_REGS, 150 VCPU_EXREG_CR3, 151 VCPU_EXREG_RFLAGS, 152 VCPU_EXREG_SEGMENTS, 153 }; 154 155 enum { 156 VCPU_SREG_ES, 157 VCPU_SREG_CS, 158 VCPU_SREG_SS, 159 VCPU_SREG_DS, 160 VCPU_SREG_FS, 161 VCPU_SREG_GS, 162 VCPU_SREG_TR, 163 VCPU_SREG_LDTR, 164 }; 165 166 #include <asm/kvm_emulate.h> 167 168 #define KVM_NR_MEM_OBJS 40 169 170 #define KVM_NR_DB_REGS 4 171 172 #define DR6_BD (1 << 13) 173 #define DR6_BS (1 << 14) 174 #define DR6_RTM (1 << 16) 175 #define DR6_FIXED_1 0xfffe0ff0 176 #define DR6_INIT 0xffff0ff0 177 #define DR6_VOLATILE 0x0001e00f 178 179 #define DR7_BP_EN_MASK 0x000000ff 180 #define DR7_GE (1 << 9) 181 #define DR7_GD (1 << 13) 182 #define DR7_FIXED_1 0x00000400 183 #define DR7_VOLATILE 0xffff2bff 184 185 #define PFERR_PRESENT_BIT 0 186 #define PFERR_WRITE_BIT 1 187 #define PFERR_USER_BIT 2 188 #define PFERR_RSVD_BIT 3 189 #define PFERR_FETCH_BIT 4 190 #define PFERR_PK_BIT 5 191 #define PFERR_GUEST_FINAL_BIT 32 192 #define PFERR_GUEST_PAGE_BIT 33 193 194 #define PFERR_PRESENT_MASK (1U << PFERR_PRESENT_BIT) 195 #define PFERR_WRITE_MASK (1U << PFERR_WRITE_BIT) 196 #define PFERR_USER_MASK (1U << PFERR_USER_BIT) 197 #define PFERR_RSVD_MASK (1U << PFERR_RSVD_BIT) 198 #define PFERR_FETCH_MASK (1U << PFERR_FETCH_BIT) 199 #define PFERR_PK_MASK (1U << PFERR_PK_BIT) 200 #define PFERR_GUEST_FINAL_MASK (1ULL << PFERR_GUEST_FINAL_BIT) 201 #define PFERR_GUEST_PAGE_MASK (1ULL << PFERR_GUEST_PAGE_BIT) 202 203 #define PFERR_NESTED_GUEST_PAGE (PFERR_GUEST_PAGE_MASK | \ 204 PFERR_USER_MASK | \ 205 PFERR_WRITE_MASK | \ 206 PFERR_PRESENT_MASK) 207 208 /* 209 * The mask used to denote special SPTEs, which can be either MMIO SPTEs or 210 * Access Tracking SPTEs. We use bit 62 instead of bit 63 to avoid conflicting 211 * with the SVE bit in EPT PTEs. 212 */ 213 #define SPTE_SPECIAL_MASK (1ULL << 62) 214 215 /* apic attention bits */ 216 #define KVM_APIC_CHECK_VAPIC 0 217 /* 218 * The following bit is set with PV-EOI, unset on EOI. 219 * We detect PV-EOI changes by guest by comparing 220 * this bit with PV-EOI in guest memory. 221 * See the implementation in apic_update_pv_eoi. 222 */ 223 #define KVM_APIC_PV_EOI_PENDING 1 224 225 struct kvm_kernel_irq_routing_entry; 226 227 /* 228 * We don't want allocation failures within the mmu code, so we preallocate 229 * enough memory for a single page fault in a cache. 230 */ 231 struct kvm_mmu_memory_cache { 232 int nobjs; 233 void *objects[KVM_NR_MEM_OBJS]; 234 }; 235 236 /* 237 * the pages used as guest page table on soft mmu are tracked by 238 * kvm_memory_slot.arch.gfn_track which is 16 bits, so the role bits used 239 * by indirect shadow page can not be more than 15 bits. 240 * 241 * Currently, we used 14 bits that are @level, @cr4_pae, @quadrant, @access, 242 * @nxe, @cr0_wp, @smep_andnot_wp and @smap_andnot_wp. 243 */ 244 union kvm_mmu_page_role { 245 unsigned word; 246 struct { 247 unsigned level:4; 248 unsigned cr4_pae:1; 249 unsigned quadrant:2; 250 unsigned direct:1; 251 unsigned access:3; 252 unsigned invalid:1; 253 unsigned nxe:1; 254 unsigned cr0_wp:1; 255 unsigned smep_andnot_wp:1; 256 unsigned smap_andnot_wp:1; 257 unsigned :8; 258 259 /* 260 * This is left at the top of the word so that 261 * kvm_memslots_for_spte_role can extract it with a 262 * simple shift. While there is room, give it a whole 263 * byte so it is also faster to load it from memory. 264 */ 265 unsigned smm:8; 266 }; 267 }; 268 269 struct kvm_rmap_head { 270 unsigned long val; 271 }; 272 273 struct kvm_mmu_page { 274 struct list_head link; 275 struct hlist_node hash_link; 276 277 /* 278 * The following two entries are used to key the shadow page in the 279 * hash table. 280 */ 281 gfn_t gfn; 282 union kvm_mmu_page_role role; 283 284 u64 *spt; 285 /* hold the gfn of each spte inside spt */ 286 gfn_t *gfns; 287 bool unsync; 288 int root_count; /* Currently serving as active root */ 289 unsigned int unsync_children; 290 struct kvm_rmap_head parent_ptes; /* rmap pointers to parent sptes */ 291 292 /* The page is obsolete if mmu_valid_gen != kvm->arch.mmu_valid_gen. */ 293 unsigned long mmu_valid_gen; 294 295 DECLARE_BITMAP(unsync_child_bitmap, 512); 296 297 #ifdef CONFIG_X86_32 298 /* 299 * Used out of the mmu-lock to avoid reading spte values while an 300 * update is in progress; see the comments in __get_spte_lockless(). 301 */ 302 int clear_spte_count; 303 #endif 304 305 /* Number of writes since the last time traversal visited this page. */ 306 atomic_t write_flooding_count; 307 }; 308 309 struct kvm_pio_request { 310 unsigned long count; 311 int in; 312 int port; 313 int size; 314 }; 315 316 struct rsvd_bits_validate { 317 u64 rsvd_bits_mask[2][4]; 318 u64 bad_mt_xwr; 319 }; 320 321 /* 322 * x86 supports 3 paging modes (4-level 64-bit, 3-level 64-bit, and 2-level 323 * 32-bit). The kvm_mmu structure abstracts the details of the current mmu 324 * mode. 325 */ 326 struct kvm_mmu { 327 void (*set_cr3)(struct kvm_vcpu *vcpu, unsigned long root); 328 unsigned long (*get_cr3)(struct kvm_vcpu *vcpu); 329 u64 (*get_pdptr)(struct kvm_vcpu *vcpu, int index); 330 int (*page_fault)(struct kvm_vcpu *vcpu, gva_t gva, u32 err, 331 bool prefault); 332 void (*inject_page_fault)(struct kvm_vcpu *vcpu, 333 struct x86_exception *fault); 334 gpa_t (*gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t gva, u32 access, 335 struct x86_exception *exception); 336 gpa_t (*translate_gpa)(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, 337 struct x86_exception *exception); 338 int (*sync_page)(struct kvm_vcpu *vcpu, 339 struct kvm_mmu_page *sp); 340 void (*invlpg)(struct kvm_vcpu *vcpu, gva_t gva); 341 void (*update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, 342 u64 *spte, const void *pte); 343 hpa_t root_hpa; 344 union kvm_mmu_page_role base_role; 345 u8 root_level; 346 u8 shadow_root_level; 347 u8 ept_ad; 348 bool direct_map; 349 350 /* 351 * Bitmap; bit set = permission fault 352 * Byte index: page fault error code [4:1] 353 * Bit index: pte permissions in ACC_* format 354 */ 355 u8 permissions[16]; 356 357 /* 358 * The pkru_mask indicates if protection key checks are needed. It 359 * consists of 16 domains indexed by page fault error code bits [4:1], 360 * with PFEC.RSVD replaced by ACC_USER_MASK from the page tables. 361 * Each domain has 2 bits which are ANDed with AD and WD from PKRU. 362 */ 363 u32 pkru_mask; 364 365 u64 *pae_root; 366 u64 *lm_root; 367 368 /* 369 * check zero bits on shadow page table entries, these 370 * bits include not only hardware reserved bits but also 371 * the bits spte never used. 372 */ 373 struct rsvd_bits_validate shadow_zero_check; 374 375 struct rsvd_bits_validate guest_rsvd_check; 376 377 /* Can have large pages at levels 2..last_nonleaf_level-1. */ 378 u8 last_nonleaf_level; 379 380 bool nx; 381 382 u64 pdptrs[4]; /* pae */ 383 }; 384 385 enum pmc_type { 386 KVM_PMC_GP = 0, 387 KVM_PMC_FIXED, 388 }; 389 390 struct kvm_pmc { 391 enum pmc_type type; 392 u8 idx; 393 u64 counter; 394 u64 eventsel; 395 struct perf_event *perf_event; 396 struct kvm_vcpu *vcpu; 397 }; 398 399 struct kvm_pmu { 400 unsigned nr_arch_gp_counters; 401 unsigned nr_arch_fixed_counters; 402 unsigned available_event_types; 403 u64 fixed_ctr_ctrl; 404 u64 global_ctrl; 405 u64 global_status; 406 u64 global_ovf_ctrl; 407 u64 counter_bitmask[2]; 408 u64 global_ctrl_mask; 409 u64 reserved_bits; 410 u8 version; 411 struct kvm_pmc gp_counters[INTEL_PMC_MAX_GENERIC]; 412 struct kvm_pmc fixed_counters[INTEL_PMC_MAX_FIXED]; 413 struct irq_work irq_work; 414 u64 reprogram_pmi; 415 }; 416 417 struct kvm_pmu_ops; 418 419 enum { 420 KVM_DEBUGREG_BP_ENABLED = 1, 421 KVM_DEBUGREG_WONT_EXIT = 2, 422 KVM_DEBUGREG_RELOAD = 4, 423 }; 424 425 struct kvm_mtrr_range { 426 u64 base; 427 u64 mask; 428 struct list_head node; 429 }; 430 431 struct kvm_mtrr { 432 struct kvm_mtrr_range var_ranges[KVM_NR_VAR_MTRR]; 433 mtrr_type fixed_ranges[KVM_NR_FIXED_MTRR_REGION]; 434 u64 deftype; 435 436 struct list_head head; 437 }; 438 439 /* Hyper-V SynIC timer */ 440 struct kvm_vcpu_hv_stimer { 441 struct hrtimer timer; 442 int index; 443 u64 config; 444 u64 count; 445 u64 exp_time; 446 struct hv_message msg; 447 bool msg_pending; 448 }; 449 450 /* Hyper-V synthetic interrupt controller (SynIC)*/ 451 struct kvm_vcpu_hv_synic { 452 u64 version; 453 u64 control; 454 u64 msg_page; 455 u64 evt_page; 456 atomic64_t sint[HV_SYNIC_SINT_COUNT]; 457 atomic_t sint_to_gsi[HV_SYNIC_SINT_COUNT]; 458 DECLARE_BITMAP(auto_eoi_bitmap, 256); 459 DECLARE_BITMAP(vec_bitmap, 256); 460 bool active; 461 }; 462 463 /* Hyper-V per vcpu emulation context */ 464 struct kvm_vcpu_hv { 465 u64 hv_vapic; 466 s64 runtime_offset; 467 struct kvm_vcpu_hv_synic synic; 468 struct kvm_hyperv_exit exit; 469 struct kvm_vcpu_hv_stimer stimer[HV_SYNIC_STIMER_COUNT]; 470 DECLARE_BITMAP(stimer_pending_bitmap, HV_SYNIC_STIMER_COUNT); 471 }; 472 473 struct kvm_vcpu_arch { 474 /* 475 * rip and regs accesses must go through 476 * kvm_{register,rip}_{read,write} functions. 477 */ 478 unsigned long regs[NR_VCPU_REGS]; 479 u32 regs_avail; 480 u32 regs_dirty; 481 482 unsigned long cr0; 483 unsigned long cr0_guest_owned_bits; 484 unsigned long cr2; 485 unsigned long cr3; 486 unsigned long cr4; 487 unsigned long cr4_guest_owned_bits; 488 unsigned long cr8; 489 u32 hflags; 490 u64 efer; 491 u64 apic_base; 492 struct kvm_lapic *apic; /* kernel irqchip context */ 493 bool apicv_active; 494 DECLARE_BITMAP(ioapic_handled_vectors, 256); 495 unsigned long apic_attention; 496 int32_t apic_arb_prio; 497 int mp_state; 498 u64 ia32_misc_enable_msr; 499 u64 smbase; 500 bool tpr_access_reporting; 501 u64 ia32_xss; 502 503 /* 504 * Paging state of the vcpu 505 * 506 * If the vcpu runs in guest mode with two level paging this still saves 507 * the paging mode of the l1 guest. This context is always used to 508 * handle faults. 509 */ 510 struct kvm_mmu mmu; 511 512 /* 513 * Paging state of an L2 guest (used for nested npt) 514 * 515 * This context will save all necessary information to walk page tables 516 * of the an L2 guest. This context is only initialized for page table 517 * walking and not for faulting since we never handle l2 page faults on 518 * the host. 519 */ 520 struct kvm_mmu nested_mmu; 521 522 /* 523 * Pointer to the mmu context currently used for 524 * gva_to_gpa translations. 525 */ 526 struct kvm_mmu *walk_mmu; 527 528 struct kvm_mmu_memory_cache mmu_pte_list_desc_cache; 529 struct kvm_mmu_memory_cache mmu_page_cache; 530 struct kvm_mmu_memory_cache mmu_page_header_cache; 531 532 struct fpu guest_fpu; 533 u64 xcr0; 534 u64 guest_supported_xcr0; 535 u32 guest_xstate_size; 536 537 struct kvm_pio_request pio; 538 void *pio_data; 539 540 u8 event_exit_inst_len; 541 542 struct kvm_queued_exception { 543 bool pending; 544 bool has_error_code; 545 bool reinject; 546 u8 nr; 547 u32 error_code; 548 } exception; 549 550 struct kvm_queued_interrupt { 551 bool pending; 552 bool soft; 553 u8 nr; 554 } interrupt; 555 556 int halt_request; /* real mode on Intel only */ 557 558 int cpuid_nent; 559 struct kvm_cpuid_entry2 cpuid_entries[KVM_MAX_CPUID_ENTRIES]; 560 561 int maxphyaddr; 562 563 /* emulate context */ 564 565 struct x86_emulate_ctxt emulate_ctxt; 566 bool emulate_regs_need_sync_to_vcpu; 567 bool emulate_regs_need_sync_from_vcpu; 568 int (*complete_userspace_io)(struct kvm_vcpu *vcpu); 569 570 gpa_t time; 571 struct pvclock_vcpu_time_info hv_clock; 572 unsigned int hw_tsc_khz; 573 struct gfn_to_hva_cache pv_time; 574 bool pv_time_enabled; 575 /* set guest stopped flag in pvclock flags field */ 576 bool pvclock_set_guest_stopped_request; 577 578 struct { 579 u64 msr_val; 580 u64 last_steal; 581 struct gfn_to_hva_cache stime; 582 struct kvm_steal_time steal; 583 } st; 584 585 u64 tsc_offset; 586 u64 last_guest_tsc; 587 u64 last_host_tsc; 588 u64 tsc_offset_adjustment; 589 u64 this_tsc_nsec; 590 u64 this_tsc_write; 591 u64 this_tsc_generation; 592 bool tsc_catchup; 593 bool tsc_always_catchup; 594 s8 virtual_tsc_shift; 595 u32 virtual_tsc_mult; 596 u32 virtual_tsc_khz; 597 s64 ia32_tsc_adjust_msr; 598 u64 tsc_scaling_ratio; 599 600 atomic_t nmi_queued; /* unprocessed asynchronous NMIs */ 601 unsigned nmi_pending; /* NMI queued after currently running handler */ 602 bool nmi_injected; /* Trying to inject an NMI this entry */ 603 bool smi_pending; /* SMI queued after currently running handler */ 604 605 struct kvm_mtrr mtrr_state; 606 u64 pat; 607 608 unsigned switch_db_regs; 609 unsigned long db[KVM_NR_DB_REGS]; 610 unsigned long dr6; 611 unsigned long dr7; 612 unsigned long eff_db[KVM_NR_DB_REGS]; 613 unsigned long guest_debug_dr7; 614 u64 msr_platform_info; 615 u64 msr_misc_features_enables; 616 617 u64 mcg_cap; 618 u64 mcg_status; 619 u64 mcg_ctl; 620 u64 mcg_ext_ctl; 621 u64 *mce_banks; 622 623 /* Cache MMIO info */ 624 u64 mmio_gva; 625 unsigned access; 626 gfn_t mmio_gfn; 627 u64 mmio_gen; 628 629 struct kvm_pmu pmu; 630 631 /* used for guest single stepping over the given code position */ 632 unsigned long singlestep_rip; 633 634 struct kvm_vcpu_hv hyperv; 635 636 cpumask_var_t wbinvd_dirty_mask; 637 638 unsigned long last_retry_eip; 639 unsigned long last_retry_addr; 640 641 struct { 642 bool halted; 643 gfn_t gfns[roundup_pow_of_two(ASYNC_PF_PER_VCPU)]; 644 struct gfn_to_hva_cache data; 645 u64 msr_val; 646 u32 id; 647 bool send_user_only; 648 } apf; 649 650 /* OSVW MSRs (AMD only) */ 651 struct { 652 u64 length; 653 u64 status; 654 } osvw; 655 656 struct { 657 u64 msr_val; 658 struct gfn_to_hva_cache data; 659 } pv_eoi; 660 661 /* 662 * Indicate whether the access faults on its page table in guest 663 * which is set when fix page fault and used to detect unhandeable 664 * instruction. 665 */ 666 bool write_fault_to_shadow_pgtable; 667 668 /* set at EPT violation at this point */ 669 unsigned long exit_qualification; 670 671 /* pv related host specific info */ 672 struct { 673 bool pv_unhalted; 674 } pv; 675 676 int pending_ioapic_eoi; 677 int pending_external_vector; 678 679 /* GPA available (AMD only) */ 680 bool gpa_available; 681 }; 682 683 struct kvm_lpage_info { 684 int disallow_lpage; 685 }; 686 687 struct kvm_arch_memory_slot { 688 struct kvm_rmap_head *rmap[KVM_NR_PAGE_SIZES]; 689 struct kvm_lpage_info *lpage_info[KVM_NR_PAGE_SIZES - 1]; 690 unsigned short *gfn_track[KVM_PAGE_TRACK_MAX]; 691 }; 692 693 /* 694 * We use as the mode the number of bits allocated in the LDR for the 695 * logical processor ID. It happens that these are all powers of two. 696 * This makes it is very easy to detect cases where the APICs are 697 * configured for multiple modes; in that case, we cannot use the map and 698 * hence cannot use kvm_irq_delivery_to_apic_fast either. 699 */ 700 #define KVM_APIC_MODE_XAPIC_CLUSTER 4 701 #define KVM_APIC_MODE_XAPIC_FLAT 8 702 #define KVM_APIC_MODE_X2APIC 16 703 704 struct kvm_apic_map { 705 struct rcu_head rcu; 706 u8 mode; 707 u32 max_apic_id; 708 union { 709 struct kvm_lapic *xapic_flat_map[8]; 710 struct kvm_lapic *xapic_cluster_map[16][4]; 711 }; 712 struct kvm_lapic *phys_map[]; 713 }; 714 715 /* Hyper-V emulation context */ 716 struct kvm_hv { 717 struct mutex hv_lock; 718 u64 hv_guest_os_id; 719 u64 hv_hypercall; 720 u64 hv_tsc_page; 721 722 /* Hyper-v based guest crash (NT kernel bugcheck) parameters */ 723 u64 hv_crash_param[HV_X64_MSR_CRASH_PARAMS]; 724 u64 hv_crash_ctl; 725 726 HV_REFERENCE_TSC_PAGE tsc_ref; 727 }; 728 729 enum kvm_irqchip_mode { 730 KVM_IRQCHIP_NONE, 731 KVM_IRQCHIP_KERNEL, /* created with KVM_CREATE_IRQCHIP */ 732 KVM_IRQCHIP_SPLIT, /* created with KVM_CAP_SPLIT_IRQCHIP */ 733 }; 734 735 struct kvm_arch { 736 unsigned int n_used_mmu_pages; 737 unsigned int n_requested_mmu_pages; 738 unsigned int n_max_mmu_pages; 739 unsigned int indirect_shadow_pages; 740 unsigned long mmu_valid_gen; 741 struct hlist_head mmu_page_hash[KVM_NUM_MMU_PAGES]; 742 /* 743 * Hash table of struct kvm_mmu_page. 744 */ 745 struct list_head active_mmu_pages; 746 struct list_head zapped_obsolete_pages; 747 struct kvm_page_track_notifier_node mmu_sp_tracker; 748 struct kvm_page_track_notifier_head track_notifier_head; 749 750 struct list_head assigned_dev_head; 751 struct iommu_domain *iommu_domain; 752 bool iommu_noncoherent; 753 #define __KVM_HAVE_ARCH_NONCOHERENT_DMA 754 atomic_t noncoherent_dma_count; 755 #define __KVM_HAVE_ARCH_ASSIGNED_DEVICE 756 atomic_t assigned_device_count; 757 struct kvm_pic *vpic; 758 struct kvm_ioapic *vioapic; 759 struct kvm_pit *vpit; 760 atomic_t vapics_in_nmi_mode; 761 struct mutex apic_map_lock; 762 struct kvm_apic_map *apic_map; 763 764 unsigned int tss_addr; 765 bool apic_access_page_done; 766 767 gpa_t wall_clock; 768 769 bool ept_identity_pagetable_done; 770 gpa_t ept_identity_map_addr; 771 772 unsigned long irq_sources_bitmap; 773 s64 kvmclock_offset; 774 raw_spinlock_t tsc_write_lock; 775 u64 last_tsc_nsec; 776 u64 last_tsc_write; 777 u32 last_tsc_khz; 778 u64 cur_tsc_nsec; 779 u64 cur_tsc_write; 780 u64 cur_tsc_offset; 781 u64 cur_tsc_generation; 782 int nr_vcpus_matched_tsc; 783 784 spinlock_t pvclock_gtod_sync_lock; 785 bool use_master_clock; 786 u64 master_kernel_ns; 787 u64 master_cycle_now; 788 struct delayed_work kvmclock_update_work; 789 struct delayed_work kvmclock_sync_work; 790 791 struct kvm_xen_hvm_config xen_hvm_config; 792 793 /* reads protected by irq_srcu, writes by irq_lock */ 794 struct hlist_head mask_notifier_list; 795 796 struct kvm_hv hyperv; 797 798 #ifdef CONFIG_KVM_MMU_AUDIT 799 int audit_point; 800 #endif 801 802 bool boot_vcpu_runs_old_kvmclock; 803 u32 bsp_vcpu_id; 804 805 u64 disabled_quirks; 806 807 enum kvm_irqchip_mode irqchip_mode; 808 u8 nr_reserved_ioapic_pins; 809 810 bool disabled_lapic_found; 811 812 /* Struct members for AVIC */ 813 u32 avic_vm_id; 814 u32 ldr_mode; 815 struct page *avic_logical_id_table_page; 816 struct page *avic_physical_id_table_page; 817 struct hlist_node hnode; 818 819 bool x2apic_format; 820 bool x2apic_broadcast_quirk_disabled; 821 }; 822 823 struct kvm_vm_stat { 824 ulong mmu_shadow_zapped; 825 ulong mmu_pte_write; 826 ulong mmu_pte_updated; 827 ulong mmu_pde_zapped; 828 ulong mmu_flooded; 829 ulong mmu_recycled; 830 ulong mmu_cache_miss; 831 ulong mmu_unsync; 832 ulong remote_tlb_flush; 833 ulong lpages; 834 ulong max_mmu_page_hash_collisions; 835 }; 836 837 struct kvm_vcpu_stat { 838 u64 pf_fixed; 839 u64 pf_guest; 840 u64 tlb_flush; 841 u64 invlpg; 842 843 u64 exits; 844 u64 io_exits; 845 u64 mmio_exits; 846 u64 signal_exits; 847 u64 irq_window_exits; 848 u64 nmi_window_exits; 849 u64 halt_exits; 850 u64 halt_successful_poll; 851 u64 halt_attempted_poll; 852 u64 halt_poll_invalid; 853 u64 halt_wakeup; 854 u64 request_irq_exits; 855 u64 irq_exits; 856 u64 host_state_reload; 857 u64 efer_reload; 858 u64 fpu_reload; 859 u64 insn_emulation; 860 u64 insn_emulation_fail; 861 u64 hypercalls; 862 u64 irq_injections; 863 u64 nmi_injections; 864 u64 req_event; 865 }; 866 867 struct x86_instruction_info; 868 869 struct msr_data { 870 bool host_initiated; 871 u32 index; 872 u64 data; 873 }; 874 875 struct kvm_lapic_irq { 876 u32 vector; 877 u16 delivery_mode; 878 u16 dest_mode; 879 bool level; 880 u16 trig_mode; 881 u32 shorthand; 882 u32 dest_id; 883 bool msi_redir_hint; 884 }; 885 886 struct kvm_x86_ops { 887 int (*cpu_has_kvm_support)(void); /* __init */ 888 int (*disabled_by_bios)(void); /* __init */ 889 int (*hardware_enable)(void); 890 void (*hardware_disable)(void); 891 void (*check_processor_compatibility)(void *rtn); 892 int (*hardware_setup)(void); /* __init */ 893 void (*hardware_unsetup)(void); /* __exit */ 894 bool (*cpu_has_accelerated_tpr)(void); 895 bool (*cpu_has_high_real_mode_segbase)(void); 896 void (*cpuid_update)(struct kvm_vcpu *vcpu); 897 898 int (*vm_init)(struct kvm *kvm); 899 void (*vm_destroy)(struct kvm *kvm); 900 901 /* Create, but do not attach this VCPU */ 902 struct kvm_vcpu *(*vcpu_create)(struct kvm *kvm, unsigned id); 903 void (*vcpu_free)(struct kvm_vcpu *vcpu); 904 void (*vcpu_reset)(struct kvm_vcpu *vcpu, bool init_event); 905 906 void (*prepare_guest_switch)(struct kvm_vcpu *vcpu); 907 void (*vcpu_load)(struct kvm_vcpu *vcpu, int cpu); 908 void (*vcpu_put)(struct kvm_vcpu *vcpu); 909 910 void (*update_bp_intercept)(struct kvm_vcpu *vcpu); 911 int (*get_msr)(struct kvm_vcpu *vcpu, struct msr_data *msr); 912 int (*set_msr)(struct kvm_vcpu *vcpu, struct msr_data *msr); 913 u64 (*get_segment_base)(struct kvm_vcpu *vcpu, int seg); 914 void (*get_segment)(struct kvm_vcpu *vcpu, 915 struct kvm_segment *var, int seg); 916 int (*get_cpl)(struct kvm_vcpu *vcpu); 917 void (*set_segment)(struct kvm_vcpu *vcpu, 918 struct kvm_segment *var, int seg); 919 void (*get_cs_db_l_bits)(struct kvm_vcpu *vcpu, int *db, int *l); 920 void (*decache_cr0_guest_bits)(struct kvm_vcpu *vcpu); 921 void (*decache_cr3)(struct kvm_vcpu *vcpu); 922 void (*decache_cr4_guest_bits)(struct kvm_vcpu *vcpu); 923 void (*set_cr0)(struct kvm_vcpu *vcpu, unsigned long cr0); 924 void (*set_cr3)(struct kvm_vcpu *vcpu, unsigned long cr3); 925 int (*set_cr4)(struct kvm_vcpu *vcpu, unsigned long cr4); 926 void (*set_efer)(struct kvm_vcpu *vcpu, u64 efer); 927 void (*get_idt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt); 928 void (*set_idt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt); 929 void (*get_gdt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt); 930 void (*set_gdt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt); 931 u64 (*get_dr6)(struct kvm_vcpu *vcpu); 932 void (*set_dr6)(struct kvm_vcpu *vcpu, unsigned long value); 933 void (*sync_dirty_debug_regs)(struct kvm_vcpu *vcpu); 934 void (*set_dr7)(struct kvm_vcpu *vcpu, unsigned long value); 935 void (*cache_reg)(struct kvm_vcpu *vcpu, enum kvm_reg reg); 936 unsigned long (*get_rflags)(struct kvm_vcpu *vcpu); 937 void (*set_rflags)(struct kvm_vcpu *vcpu, unsigned long rflags); 938 u32 (*get_pkru)(struct kvm_vcpu *vcpu); 939 940 void (*tlb_flush)(struct kvm_vcpu *vcpu); 941 942 void (*run)(struct kvm_vcpu *vcpu); 943 int (*handle_exit)(struct kvm_vcpu *vcpu); 944 void (*skip_emulated_instruction)(struct kvm_vcpu *vcpu); 945 void (*set_interrupt_shadow)(struct kvm_vcpu *vcpu, int mask); 946 u32 (*get_interrupt_shadow)(struct kvm_vcpu *vcpu); 947 void (*patch_hypercall)(struct kvm_vcpu *vcpu, 948 unsigned char *hypercall_addr); 949 void (*set_irq)(struct kvm_vcpu *vcpu); 950 void (*set_nmi)(struct kvm_vcpu *vcpu); 951 void (*queue_exception)(struct kvm_vcpu *vcpu, unsigned nr, 952 bool has_error_code, u32 error_code, 953 bool reinject); 954 void (*cancel_injection)(struct kvm_vcpu *vcpu); 955 int (*interrupt_allowed)(struct kvm_vcpu *vcpu); 956 int (*nmi_allowed)(struct kvm_vcpu *vcpu); 957 bool (*get_nmi_mask)(struct kvm_vcpu *vcpu); 958 void (*set_nmi_mask)(struct kvm_vcpu *vcpu, bool masked); 959 void (*enable_nmi_window)(struct kvm_vcpu *vcpu); 960 void (*enable_irq_window)(struct kvm_vcpu *vcpu); 961 void (*update_cr8_intercept)(struct kvm_vcpu *vcpu, int tpr, int irr); 962 bool (*get_enable_apicv)(void); 963 void (*refresh_apicv_exec_ctrl)(struct kvm_vcpu *vcpu); 964 void (*hwapic_irr_update)(struct kvm_vcpu *vcpu, int max_irr); 965 void (*hwapic_isr_update)(struct kvm_vcpu *vcpu, int isr); 966 void (*load_eoi_exitmap)(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap); 967 void (*set_virtual_x2apic_mode)(struct kvm_vcpu *vcpu, bool set); 968 void (*set_apic_access_page_addr)(struct kvm_vcpu *vcpu, hpa_t hpa); 969 void (*deliver_posted_interrupt)(struct kvm_vcpu *vcpu, int vector); 970 int (*sync_pir_to_irr)(struct kvm_vcpu *vcpu); 971 int (*set_tss_addr)(struct kvm *kvm, unsigned int addr); 972 int (*get_tdp_level)(void); 973 u64 (*get_mt_mask)(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio); 974 int (*get_lpage_level)(void); 975 bool (*rdtscp_supported)(void); 976 bool (*invpcid_supported)(void); 977 978 void (*set_tdp_cr3)(struct kvm_vcpu *vcpu, unsigned long cr3); 979 980 void (*set_supported_cpuid)(u32 func, struct kvm_cpuid_entry2 *entry); 981 982 bool (*has_wbinvd_exit)(void); 983 984 void (*write_tsc_offset)(struct kvm_vcpu *vcpu, u64 offset); 985 986 void (*get_exit_info)(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2); 987 988 int (*check_intercept)(struct kvm_vcpu *vcpu, 989 struct x86_instruction_info *info, 990 enum x86_intercept_stage stage); 991 void (*handle_external_intr)(struct kvm_vcpu *vcpu); 992 bool (*mpx_supported)(void); 993 bool (*xsaves_supported)(void); 994 995 int (*check_nested_events)(struct kvm_vcpu *vcpu, bool external_intr); 996 997 void (*sched_in)(struct kvm_vcpu *kvm, int cpu); 998 999 /* 1000 * Arch-specific dirty logging hooks. These hooks are only supposed to 1001 * be valid if the specific arch has hardware-accelerated dirty logging 1002 * mechanism. Currently only for PML on VMX. 1003 * 1004 * - slot_enable_log_dirty: 1005 * called when enabling log dirty mode for the slot. 1006 * - slot_disable_log_dirty: 1007 * called when disabling log dirty mode for the slot. 1008 * also called when slot is created with log dirty disabled. 1009 * - flush_log_dirty: 1010 * called before reporting dirty_bitmap to userspace. 1011 * - enable_log_dirty_pt_masked: 1012 * called when reenabling log dirty for the GFNs in the mask after 1013 * corresponding bits are cleared in slot->dirty_bitmap. 1014 */ 1015 void (*slot_enable_log_dirty)(struct kvm *kvm, 1016 struct kvm_memory_slot *slot); 1017 void (*slot_disable_log_dirty)(struct kvm *kvm, 1018 struct kvm_memory_slot *slot); 1019 void (*flush_log_dirty)(struct kvm *kvm); 1020 void (*enable_log_dirty_pt_masked)(struct kvm *kvm, 1021 struct kvm_memory_slot *slot, 1022 gfn_t offset, unsigned long mask); 1023 int (*write_log_dirty)(struct kvm_vcpu *vcpu); 1024 1025 /* pmu operations of sub-arch */ 1026 const struct kvm_pmu_ops *pmu_ops; 1027 1028 /* 1029 * Architecture specific hooks for vCPU blocking due to 1030 * HLT instruction. 1031 * Returns for .pre_block(): 1032 * - 0 means continue to block the vCPU. 1033 * - 1 means we cannot block the vCPU since some event 1034 * happens during this period, such as, 'ON' bit in 1035 * posted-interrupts descriptor is set. 1036 */ 1037 int (*pre_block)(struct kvm_vcpu *vcpu); 1038 void (*post_block)(struct kvm_vcpu *vcpu); 1039 1040 void (*vcpu_blocking)(struct kvm_vcpu *vcpu); 1041 void (*vcpu_unblocking)(struct kvm_vcpu *vcpu); 1042 1043 int (*update_pi_irte)(struct kvm *kvm, unsigned int host_irq, 1044 uint32_t guest_irq, bool set); 1045 void (*apicv_post_state_restore)(struct kvm_vcpu *vcpu); 1046 1047 int (*set_hv_timer)(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc); 1048 void (*cancel_hv_timer)(struct kvm_vcpu *vcpu); 1049 1050 void (*setup_mce)(struct kvm_vcpu *vcpu); 1051 }; 1052 1053 struct kvm_arch_async_pf { 1054 u32 token; 1055 gfn_t gfn; 1056 unsigned long cr3; 1057 bool direct_map; 1058 }; 1059 1060 extern struct kvm_x86_ops *kvm_x86_ops; 1061 1062 int kvm_mmu_module_init(void); 1063 void kvm_mmu_module_exit(void); 1064 1065 void kvm_mmu_destroy(struct kvm_vcpu *vcpu); 1066 int kvm_mmu_create(struct kvm_vcpu *vcpu); 1067 void kvm_mmu_setup(struct kvm_vcpu *vcpu); 1068 void kvm_mmu_init_vm(struct kvm *kvm); 1069 void kvm_mmu_uninit_vm(struct kvm *kvm); 1070 void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask, 1071 u64 dirty_mask, u64 nx_mask, u64 x_mask, u64 p_mask, 1072 u64 acc_track_mask); 1073 1074 void kvm_mmu_reset_context(struct kvm_vcpu *vcpu); 1075 void kvm_mmu_slot_remove_write_access(struct kvm *kvm, 1076 struct kvm_memory_slot *memslot); 1077 void kvm_mmu_zap_collapsible_sptes(struct kvm *kvm, 1078 const struct kvm_memory_slot *memslot); 1079 void kvm_mmu_slot_leaf_clear_dirty(struct kvm *kvm, 1080 struct kvm_memory_slot *memslot); 1081 void kvm_mmu_slot_largepage_remove_write_access(struct kvm *kvm, 1082 struct kvm_memory_slot *memslot); 1083 void kvm_mmu_slot_set_dirty(struct kvm *kvm, 1084 struct kvm_memory_slot *memslot); 1085 void kvm_mmu_clear_dirty_pt_masked(struct kvm *kvm, 1086 struct kvm_memory_slot *slot, 1087 gfn_t gfn_offset, unsigned long mask); 1088 void kvm_mmu_zap_all(struct kvm *kvm); 1089 void kvm_mmu_invalidate_mmio_sptes(struct kvm *kvm, struct kvm_memslots *slots); 1090 unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm); 1091 void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int kvm_nr_mmu_pages); 1092 1093 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3); 1094 bool pdptrs_changed(struct kvm_vcpu *vcpu); 1095 1096 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, 1097 const void *val, int bytes); 1098 1099 struct kvm_irq_mask_notifier { 1100 void (*func)(struct kvm_irq_mask_notifier *kimn, bool masked); 1101 int irq; 1102 struct hlist_node link; 1103 }; 1104 1105 void kvm_register_irq_mask_notifier(struct kvm *kvm, int irq, 1106 struct kvm_irq_mask_notifier *kimn); 1107 void kvm_unregister_irq_mask_notifier(struct kvm *kvm, int irq, 1108 struct kvm_irq_mask_notifier *kimn); 1109 void kvm_fire_mask_notifiers(struct kvm *kvm, unsigned irqchip, unsigned pin, 1110 bool mask); 1111 1112 extern bool tdp_enabled; 1113 1114 u64 vcpu_tsc_khz(struct kvm_vcpu *vcpu); 1115 1116 /* control of guest tsc rate supported? */ 1117 extern bool kvm_has_tsc_control; 1118 /* maximum supported tsc_khz for guests */ 1119 extern u32 kvm_max_guest_tsc_khz; 1120 /* number of bits of the fractional part of the TSC scaling ratio */ 1121 extern u8 kvm_tsc_scaling_ratio_frac_bits; 1122 /* maximum allowed value of TSC scaling ratio */ 1123 extern u64 kvm_max_tsc_scaling_ratio; 1124 /* 1ull << kvm_tsc_scaling_ratio_frac_bits */ 1125 extern u64 kvm_default_tsc_scaling_ratio; 1126 1127 extern u64 kvm_mce_cap_supported; 1128 1129 enum emulation_result { 1130 EMULATE_DONE, /* no further processing */ 1131 EMULATE_USER_EXIT, /* kvm_run ready for userspace exit */ 1132 EMULATE_FAIL, /* can't emulate this instruction */ 1133 }; 1134 1135 #define EMULTYPE_NO_DECODE (1 << 0) 1136 #define EMULTYPE_TRAP_UD (1 << 1) 1137 #define EMULTYPE_SKIP (1 << 2) 1138 #define EMULTYPE_RETRY (1 << 3) 1139 #define EMULTYPE_NO_REEXECUTE (1 << 4) 1140 int x86_emulate_instruction(struct kvm_vcpu *vcpu, unsigned long cr2, 1141 int emulation_type, void *insn, int insn_len); 1142 1143 static inline int emulate_instruction(struct kvm_vcpu *vcpu, 1144 int emulation_type) 1145 { 1146 return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0); 1147 } 1148 1149 void kvm_enable_efer_bits(u64); 1150 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer); 1151 int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr); 1152 int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr); 1153 1154 struct x86_emulate_ctxt; 1155 1156 int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port); 1157 int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size, unsigned short port); 1158 int kvm_emulate_cpuid(struct kvm_vcpu *vcpu); 1159 int kvm_emulate_halt(struct kvm_vcpu *vcpu); 1160 int kvm_vcpu_halt(struct kvm_vcpu *vcpu); 1161 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu); 1162 1163 void kvm_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg); 1164 int kvm_load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector, int seg); 1165 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector); 1166 1167 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index, 1168 int reason, bool has_error_code, u32 error_code); 1169 1170 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0); 1171 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3); 1172 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4); 1173 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8); 1174 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val); 1175 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val); 1176 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu); 1177 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw); 1178 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l); 1179 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr); 1180 1181 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr); 1182 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr); 1183 1184 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu); 1185 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags); 1186 bool kvm_rdpmc(struct kvm_vcpu *vcpu); 1187 1188 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr); 1189 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code); 1190 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr); 1191 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code); 1192 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault); 1193 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, 1194 gfn_t gfn, void *data, int offset, int len, 1195 u32 access); 1196 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl); 1197 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr); 1198 1199 static inline int __kvm_irq_line_state(unsigned long *irq_state, 1200 int irq_source_id, int level) 1201 { 1202 /* Logical OR for level trig interrupt */ 1203 if (level) 1204 __set_bit(irq_source_id, irq_state); 1205 else 1206 __clear_bit(irq_source_id, irq_state); 1207 1208 return !!(*irq_state); 1209 } 1210 1211 int kvm_pic_set_irq(struct kvm_pic *pic, int irq, int irq_source_id, int level); 1212 void kvm_pic_clear_all(struct kvm_pic *pic, int irq_source_id); 1213 1214 void kvm_inject_nmi(struct kvm_vcpu *vcpu); 1215 1216 int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn); 1217 int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva); 1218 void __kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu); 1219 int kvm_mmu_load(struct kvm_vcpu *vcpu); 1220 void kvm_mmu_unload(struct kvm_vcpu *vcpu); 1221 void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu); 1222 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, 1223 struct x86_exception *exception); 1224 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, 1225 struct x86_exception *exception); 1226 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, 1227 struct x86_exception *exception); 1228 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, 1229 struct x86_exception *exception); 1230 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, 1231 struct x86_exception *exception); 1232 1233 void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu); 1234 1235 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu); 1236 1237 int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t gva, u64 error_code, 1238 void *insn, int insn_len); 1239 void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva); 1240 void kvm_mmu_new_cr3(struct kvm_vcpu *vcpu); 1241 1242 void kvm_enable_tdp(void); 1243 void kvm_disable_tdp(void); 1244 1245 static inline gpa_t translate_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, 1246 struct x86_exception *exception) 1247 { 1248 return gpa; 1249 } 1250 1251 static inline struct kvm_mmu_page *page_header(hpa_t shadow_page) 1252 { 1253 struct page *page = pfn_to_page(shadow_page >> PAGE_SHIFT); 1254 1255 return (struct kvm_mmu_page *)page_private(page); 1256 } 1257 1258 static inline u16 kvm_read_ldt(void) 1259 { 1260 u16 ldt; 1261 asm("sldt %0" : "=g"(ldt)); 1262 return ldt; 1263 } 1264 1265 static inline void kvm_load_ldt(u16 sel) 1266 { 1267 asm("lldt %0" : : "rm"(sel)); 1268 } 1269 1270 #ifdef CONFIG_X86_64 1271 static inline unsigned long read_msr(unsigned long msr) 1272 { 1273 u64 value; 1274 1275 rdmsrl(msr, value); 1276 return value; 1277 } 1278 #endif 1279 1280 static inline u32 get_rdx_init_val(void) 1281 { 1282 return 0x600; /* P6 family */ 1283 } 1284 1285 static inline void kvm_inject_gp(struct kvm_vcpu *vcpu, u32 error_code) 1286 { 1287 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code); 1288 } 1289 1290 static inline u64 get_canonical(u64 la) 1291 { 1292 return ((int64_t)la << 16) >> 16; 1293 } 1294 1295 static inline bool is_noncanonical_address(u64 la) 1296 { 1297 #ifdef CONFIG_X86_64 1298 return get_canonical(la) != la; 1299 #else 1300 return false; 1301 #endif 1302 } 1303 1304 #define TSS_IOPB_BASE_OFFSET 0x66 1305 #define TSS_BASE_SIZE 0x68 1306 #define TSS_IOPB_SIZE (65536 / 8) 1307 #define TSS_REDIRECTION_SIZE (256 / 8) 1308 #define RMODE_TSS_SIZE \ 1309 (TSS_BASE_SIZE + TSS_REDIRECTION_SIZE + TSS_IOPB_SIZE + 1) 1310 1311 enum { 1312 TASK_SWITCH_CALL = 0, 1313 TASK_SWITCH_IRET = 1, 1314 TASK_SWITCH_JMP = 2, 1315 TASK_SWITCH_GATE = 3, 1316 }; 1317 1318 #define HF_GIF_MASK (1 << 0) 1319 #define HF_HIF_MASK (1 << 1) 1320 #define HF_VINTR_MASK (1 << 2) 1321 #define HF_NMI_MASK (1 << 3) 1322 #define HF_IRET_MASK (1 << 4) 1323 #define HF_GUEST_MASK (1 << 5) /* VCPU is in guest-mode */ 1324 #define HF_SMM_MASK (1 << 6) 1325 #define HF_SMM_INSIDE_NMI_MASK (1 << 7) 1326 1327 #define __KVM_VCPU_MULTIPLE_ADDRESS_SPACE 1328 #define KVM_ADDRESS_SPACE_NUM 2 1329 1330 #define kvm_arch_vcpu_memslots_id(vcpu) ((vcpu)->arch.hflags & HF_SMM_MASK ? 1 : 0) 1331 #define kvm_memslots_for_spte_role(kvm, role) __kvm_memslots(kvm, (role).smm) 1332 1333 /* 1334 * Hardware virtualization extension instructions may fault if a 1335 * reboot turns off virtualization while processes are running. 1336 * Trap the fault and ignore the instruction if that happens. 1337 */ 1338 asmlinkage void kvm_spurious_fault(void); 1339 1340 #define ____kvm_handle_fault_on_reboot(insn, cleanup_insn) \ 1341 "666: " insn "\n\t" \ 1342 "668: \n\t" \ 1343 ".pushsection .fixup, \"ax\" \n" \ 1344 "667: \n\t" \ 1345 cleanup_insn "\n\t" \ 1346 "cmpb $0, kvm_rebooting \n\t" \ 1347 "jne 668b \n\t" \ 1348 __ASM_SIZE(push) " $666b \n\t" \ 1349 "call kvm_spurious_fault \n\t" \ 1350 ".popsection \n\t" \ 1351 _ASM_EXTABLE(666b, 667b) 1352 1353 #define __kvm_handle_fault_on_reboot(insn) \ 1354 ____kvm_handle_fault_on_reboot(insn, "") 1355 1356 #define KVM_ARCH_WANT_MMU_NOTIFIER 1357 int kvm_unmap_hva(struct kvm *kvm, unsigned long hva); 1358 int kvm_unmap_hva_range(struct kvm *kvm, unsigned long start, unsigned long end); 1359 int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end); 1360 int kvm_test_age_hva(struct kvm *kvm, unsigned long hva); 1361 void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte); 1362 int kvm_cpu_has_injectable_intr(struct kvm_vcpu *v); 1363 int kvm_cpu_has_interrupt(struct kvm_vcpu *vcpu); 1364 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu); 1365 int kvm_cpu_get_interrupt(struct kvm_vcpu *v); 1366 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event); 1367 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu); 1368 void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm, 1369 unsigned long address); 1370 1371 void kvm_define_shared_msr(unsigned index, u32 msr); 1372 int kvm_set_shared_msr(unsigned index, u64 val, u64 mask); 1373 1374 u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc); 1375 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc); 1376 1377 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu); 1378 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip); 1379 1380 void kvm_make_mclock_inprogress_request(struct kvm *kvm); 1381 void kvm_make_scan_ioapic_request(struct kvm *kvm); 1382 1383 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu, 1384 struct kvm_async_pf *work); 1385 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu, 1386 struct kvm_async_pf *work); 1387 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, 1388 struct kvm_async_pf *work); 1389 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu); 1390 extern bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn); 1391 1392 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu); 1393 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err); 1394 1395 int kvm_is_in_guest(void); 1396 1397 int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size); 1398 int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size); 1399 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu); 1400 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu); 1401 1402 bool kvm_intr_is_single_vcpu(struct kvm *kvm, struct kvm_lapic_irq *irq, 1403 struct kvm_vcpu **dest_vcpu); 1404 1405 void kvm_set_msi_irq(struct kvm *kvm, struct kvm_kernel_irq_routing_entry *e, 1406 struct kvm_lapic_irq *irq); 1407 1408 static inline void kvm_arch_vcpu_blocking(struct kvm_vcpu *vcpu) 1409 { 1410 if (kvm_x86_ops->vcpu_blocking) 1411 kvm_x86_ops->vcpu_blocking(vcpu); 1412 } 1413 1414 static inline void kvm_arch_vcpu_unblocking(struct kvm_vcpu *vcpu) 1415 { 1416 if (kvm_x86_ops->vcpu_unblocking) 1417 kvm_x86_ops->vcpu_unblocking(vcpu); 1418 } 1419 1420 static inline void kvm_arch_vcpu_block_finish(struct kvm_vcpu *vcpu) {} 1421 1422 static inline int kvm_cpu_get_apicid(int mps_cpu) 1423 { 1424 #ifdef CONFIG_X86_LOCAL_APIC 1425 return __default_cpu_present_to_apicid(mps_cpu); 1426 #else 1427 WARN_ON_ONCE(1); 1428 return BAD_APICID; 1429 #endif 1430 } 1431 1432 #endif /* _ASM_X86_KVM_HOST_H */ 1433