1 #ifndef _ASM_X86_IO_H 2 #define _ASM_X86_IO_H 3 4 /* 5 * This file contains the definitions for the x86 IO instructions 6 * inb/inw/inl/outb/outw/outl and the "string versions" of the same 7 * (insb/insw/insl/outsb/outsw/outsl). You can also use "pausing" 8 * versions of the single-IO instructions (inb_p/inw_p/..). 9 * 10 * This file is not meant to be obfuscating: it's just complicated 11 * to (a) handle it all in a way that makes gcc able to optimize it 12 * as well as possible and (b) trying to avoid writing the same thing 13 * over and over again with slight variations and possibly making a 14 * mistake somewhere. 15 */ 16 17 /* 18 * Thanks to James van Artsdalen for a better timing-fix than 19 * the two short jumps: using outb's to a nonexistent port seems 20 * to guarantee better timings even on fast machines. 21 * 22 * On the other hand, I'd like to be sure of a non-existent port: 23 * I feel a bit unsafe about using 0x80 (should be safe, though) 24 * 25 * Linus 26 */ 27 28 /* 29 * Bit simplified and optimized by Jan Hubicka 30 * Support of BIGMEM added by Gerhard Wichert, Siemens AG, July 1999. 31 * 32 * isa_memset_io, isa_memcpy_fromio, isa_memcpy_toio added, 33 * isa_read[wl] and isa_write[wl] fixed 34 * - Arnaldo Carvalho de Melo <acme@conectiva.com.br> 35 */ 36 37 #define ARCH_HAS_IOREMAP_WC 38 #define ARCH_HAS_IOREMAP_WT 39 40 #include <linux/string.h> 41 #include <linux/compiler.h> 42 #include <asm/page.h> 43 #include <asm/early_ioremap.h> 44 #include <asm/pgtable_types.h> 45 46 #define build_mmio_read(name, size, type, reg, barrier) \ 47 static inline type name(const volatile void __iomem *addr) \ 48 { type ret; asm volatile("mov" size " %1,%0":reg (ret) \ 49 :"m" (*(volatile type __force *)addr) barrier); return ret; } 50 51 #define build_mmio_write(name, size, type, reg, barrier) \ 52 static inline void name(type val, volatile void __iomem *addr) \ 53 { asm volatile("mov" size " %0,%1": :reg (val), \ 54 "m" (*(volatile type __force *)addr) barrier); } 55 56 build_mmio_read(readb, "b", unsigned char, "=q", :"memory") 57 build_mmio_read(readw, "w", unsigned short, "=r", :"memory") 58 build_mmio_read(readl, "l", unsigned int, "=r", :"memory") 59 60 build_mmio_read(__readb, "b", unsigned char, "=q", ) 61 build_mmio_read(__readw, "w", unsigned short, "=r", ) 62 build_mmio_read(__readl, "l", unsigned int, "=r", ) 63 64 build_mmio_write(writeb, "b", unsigned char, "q", :"memory") 65 build_mmio_write(writew, "w", unsigned short, "r", :"memory") 66 build_mmio_write(writel, "l", unsigned int, "r", :"memory") 67 68 build_mmio_write(__writeb, "b", unsigned char, "q", ) 69 build_mmio_write(__writew, "w", unsigned short, "r", ) 70 build_mmio_write(__writel, "l", unsigned int, "r", ) 71 72 #define readb readb 73 #define readw readw 74 #define readl readl 75 #define readb_relaxed(a) __readb(a) 76 #define readw_relaxed(a) __readw(a) 77 #define readl_relaxed(a) __readl(a) 78 #define __raw_readb __readb 79 #define __raw_readw __readw 80 #define __raw_readl __readl 81 82 #define writeb writeb 83 #define writew writew 84 #define writel writel 85 #define writeb_relaxed(v, a) __writeb(v, a) 86 #define writew_relaxed(v, a) __writew(v, a) 87 #define writel_relaxed(v, a) __writel(v, a) 88 #define __raw_writeb __writeb 89 #define __raw_writew __writew 90 #define __raw_writel __writel 91 92 #define mmiowb() barrier() 93 94 #ifdef CONFIG_X86_64 95 96 build_mmio_read(readq, "q", unsigned long, "=r", :"memory") 97 build_mmio_read(__readq, "q", unsigned long, "=r", ) 98 build_mmio_write(writeq, "q", unsigned long, "r", :"memory") 99 build_mmio_write(__writeq, "q", unsigned long, "r", ) 100 101 #define readq_relaxed(a) __readq(a) 102 #define writeq_relaxed(v, a) __writeq(v, a) 103 104 #define __raw_readq __readq 105 #define __raw_writeq __writeq 106 107 /* Let people know that we have them */ 108 #define readq readq 109 #define writeq writeq 110 111 #endif 112 113 #define ARCH_HAS_VALID_PHYS_ADDR_RANGE 114 extern int valid_phys_addr_range(phys_addr_t addr, size_t size); 115 extern int valid_mmap_phys_addr_range(unsigned long pfn, size_t size); 116 117 /** 118 * virt_to_phys - map virtual addresses to physical 119 * @address: address to remap 120 * 121 * The returned physical address is the physical (CPU) mapping for 122 * the memory address given. It is only valid to use this function on 123 * addresses directly mapped or allocated via kmalloc. 124 * 125 * This function does not give bus mappings for DMA transfers. In 126 * almost all conceivable cases a device driver should not be using 127 * this function 128 */ 129 130 static inline phys_addr_t virt_to_phys(volatile void *address) 131 { 132 return __pa(address); 133 } 134 #define virt_to_phys virt_to_phys 135 136 /** 137 * phys_to_virt - map physical address to virtual 138 * @address: address to remap 139 * 140 * The returned virtual address is a current CPU mapping for 141 * the memory address given. It is only valid to use this function on 142 * addresses that have a kernel mapping 143 * 144 * This function does not handle bus mappings for DMA transfers. In 145 * almost all conceivable cases a device driver should not be using 146 * this function 147 */ 148 149 static inline void *phys_to_virt(phys_addr_t address) 150 { 151 return __va(address); 152 } 153 #define phys_to_virt phys_to_virt 154 155 /* 156 * Change "struct page" to physical address. 157 */ 158 #define page_to_phys(page) ((dma_addr_t)page_to_pfn(page) << PAGE_SHIFT) 159 160 /* 161 * ISA I/O bus memory addresses are 1:1 with the physical address. 162 * However, we truncate the address to unsigned int to avoid undesirable 163 * promitions in legacy drivers. 164 */ 165 static inline unsigned int isa_virt_to_bus(volatile void *address) 166 { 167 return (unsigned int)virt_to_phys(address); 168 } 169 #define isa_page_to_bus(page) ((unsigned int)page_to_phys(page)) 170 #define isa_bus_to_virt phys_to_virt 171 172 /* 173 * However PCI ones are not necessarily 1:1 and therefore these interfaces 174 * are forbidden in portable PCI drivers. 175 * 176 * Allow them on x86 for legacy drivers, though. 177 */ 178 #define virt_to_bus virt_to_phys 179 #define bus_to_virt phys_to_virt 180 181 /* 182 * The default ioremap() behavior is non-cached; if you need something 183 * else, you probably want one of the following. 184 */ 185 extern void __iomem *ioremap_nocache(resource_size_t offset, unsigned long size); 186 #define ioremap_nocache ioremap_nocache 187 extern void __iomem *ioremap_uc(resource_size_t offset, unsigned long size); 188 #define ioremap_uc ioremap_uc 189 190 extern void __iomem *ioremap_cache(resource_size_t offset, unsigned long size); 191 #define ioremap_cache ioremap_cache 192 extern void __iomem *ioremap_prot(resource_size_t offset, unsigned long size, unsigned long prot_val); 193 #define ioremap_prot ioremap_prot 194 195 /** 196 * ioremap - map bus memory into CPU space 197 * @offset: bus address of the memory 198 * @size: size of the resource to map 199 * 200 * ioremap performs a platform specific sequence of operations to 201 * make bus memory CPU accessible via the readb/readw/readl/writeb/ 202 * writew/writel functions and the other mmio helpers. The returned 203 * address is not guaranteed to be usable directly as a virtual 204 * address. 205 * 206 * If the area you are trying to map is a PCI BAR you should have a 207 * look at pci_iomap(). 208 */ 209 static inline void __iomem *ioremap(resource_size_t offset, unsigned long size) 210 { 211 return ioremap_nocache(offset, size); 212 } 213 #define ioremap ioremap 214 215 extern void iounmap(volatile void __iomem *addr); 216 #define iounmap iounmap 217 218 extern void set_iounmap_nonlazy(void); 219 220 #ifdef __KERNEL__ 221 222 #include <asm-generic/iomap.h> 223 224 /* 225 * ISA space is 'always mapped' on a typical x86 system, no need to 226 * explicitly ioremap() it. The fact that the ISA IO space is mapped 227 * to PAGE_OFFSET is pure coincidence - it does not mean ISA values 228 * are physical addresses. The following constant pointer can be 229 * used as the IO-area pointer (it can be iounmapped as well, so the 230 * analogy with PCI is quite large): 231 */ 232 #define __ISA_IO_base ((char __iomem *)(PAGE_OFFSET)) 233 234 /* 235 * Cache management 236 * 237 * This needed for two cases 238 * 1. Out of order aware processors 239 * 2. Accidentally out of order processors (PPro errata #51) 240 */ 241 242 static inline void flush_write_buffers(void) 243 { 244 #if defined(CONFIG_X86_PPRO_FENCE) 245 asm volatile("lock; addl $0,0(%%esp)": : :"memory"); 246 #endif 247 } 248 249 #endif /* __KERNEL__ */ 250 251 extern void native_io_delay(void); 252 253 extern int io_delay_type; 254 extern void io_delay_init(void); 255 256 #if defined(CONFIG_PARAVIRT) 257 #include <asm/paravirt.h> 258 #else 259 260 static inline void slow_down_io(void) 261 { 262 native_io_delay(); 263 #ifdef REALLY_SLOW_IO 264 native_io_delay(); 265 native_io_delay(); 266 native_io_delay(); 267 #endif 268 } 269 270 #endif 271 272 #define BUILDIO(bwl, bw, type) \ 273 static inline void out##bwl(unsigned type value, int port) \ 274 { \ 275 asm volatile("out" #bwl " %" #bw "0, %w1" \ 276 : : "a"(value), "Nd"(port)); \ 277 } \ 278 \ 279 static inline unsigned type in##bwl(int port) \ 280 { \ 281 unsigned type value; \ 282 asm volatile("in" #bwl " %w1, %" #bw "0" \ 283 : "=a"(value) : "Nd"(port)); \ 284 return value; \ 285 } \ 286 \ 287 static inline void out##bwl##_p(unsigned type value, int port) \ 288 { \ 289 out##bwl(value, port); \ 290 slow_down_io(); \ 291 } \ 292 \ 293 static inline unsigned type in##bwl##_p(int port) \ 294 { \ 295 unsigned type value = in##bwl(port); \ 296 slow_down_io(); \ 297 return value; \ 298 } \ 299 \ 300 static inline void outs##bwl(int port, const void *addr, unsigned long count) \ 301 { \ 302 asm volatile("rep; outs" #bwl \ 303 : "+S"(addr), "+c"(count) : "d"(port) : "memory"); \ 304 } \ 305 \ 306 static inline void ins##bwl(int port, void *addr, unsigned long count) \ 307 { \ 308 asm volatile("rep; ins" #bwl \ 309 : "+D"(addr), "+c"(count) : "d"(port) : "memory"); \ 310 } 311 312 BUILDIO(b, b, char) 313 BUILDIO(w, w, short) 314 BUILDIO(l, , int) 315 316 #define inb inb 317 #define inw inw 318 #define inl inl 319 #define inb_p inb_p 320 #define inw_p inw_p 321 #define inl_p inl_p 322 #define insb insb 323 #define insw insw 324 #define insl insl 325 326 #define outb outb 327 #define outw outw 328 #define outl outl 329 #define outb_p outb_p 330 #define outw_p outw_p 331 #define outl_p outl_p 332 #define outsb outsb 333 #define outsw outsw 334 #define outsl outsl 335 336 extern void *xlate_dev_mem_ptr(phys_addr_t phys); 337 extern void unxlate_dev_mem_ptr(phys_addr_t phys, void *addr); 338 339 #define xlate_dev_mem_ptr xlate_dev_mem_ptr 340 #define unxlate_dev_mem_ptr unxlate_dev_mem_ptr 341 342 extern int ioremap_change_attr(unsigned long vaddr, unsigned long size, 343 enum page_cache_mode pcm); 344 extern void __iomem *ioremap_wc(resource_size_t offset, unsigned long size); 345 #define ioremap_wc ioremap_wc 346 extern void __iomem *ioremap_wt(resource_size_t offset, unsigned long size); 347 #define ioremap_wt ioremap_wt 348 349 extern bool is_early_ioremap_ptep(pte_t *ptep); 350 351 #ifdef CONFIG_XEN 352 #include <xen/xen.h> 353 struct bio_vec; 354 355 extern bool xen_biovec_phys_mergeable(const struct bio_vec *vec1, 356 const struct bio_vec *vec2); 357 358 #define BIOVEC_PHYS_MERGEABLE(vec1, vec2) \ 359 (__BIOVEC_PHYS_MERGEABLE(vec1, vec2) && \ 360 (!xen_domain() || xen_biovec_phys_mergeable(vec1, vec2))) 361 #endif /* CONFIG_XEN */ 362 363 #define IO_SPACE_LIMIT 0xffff 364 365 #include <asm-generic/io.h> 366 #undef PCI_IOBASE 367 368 #ifdef CONFIG_MTRR 369 extern int __must_check arch_phys_wc_index(int handle); 370 #define arch_phys_wc_index arch_phys_wc_index 371 372 extern int __must_check arch_phys_wc_add(unsigned long base, 373 unsigned long size); 374 extern void arch_phys_wc_del(int handle); 375 #define arch_phys_wc_add arch_phys_wc_add 376 #endif 377 378 #ifdef CONFIG_X86_PAT 379 extern int arch_io_reserve_memtype_wc(resource_size_t start, resource_size_t size); 380 extern void arch_io_free_memtype_wc(resource_size_t start, resource_size_t size); 381 #define arch_io_reserve_memtype_wc arch_io_reserve_memtype_wc 382 #endif 383 384 extern bool arch_memremap_can_ram_remap(resource_size_t offset, 385 unsigned long size, 386 unsigned long flags); 387 #define arch_memremap_can_ram_remap arch_memremap_can_ram_remap 388 389 extern bool phys_mem_access_encrypted(unsigned long phys_addr, 390 unsigned long size); 391 392 #endif /* _ASM_X86_IO_H */ 393