1 #ifndef _ASM_INTEL_DS_H 2 #define _ASM_INTEL_DS_H 3 4 #include <linux/percpu-defs.h> 5 6 #define BTS_BUFFER_SIZE (PAGE_SIZE << 4) 7 #define PEBS_BUFFER_SHIFT 4 8 #define PEBS_BUFFER_SIZE (PAGE_SIZE << PEBS_BUFFER_SHIFT) 9 10 /* 11 * The largest PEBS record could consume a page, ensure 12 * a record at least can be written after triggering PMI. 13 */ 14 #define ARCH_PEBS_THRESH_MULTI ((PEBS_BUFFER_SIZE - PAGE_SIZE) >> PEBS_BUFFER_SHIFT) 15 #define ARCH_PEBS_THRESH_SINGLE 1 16 17 /* The maximal number of PEBS events: */ 18 #define MAX_PEBS_EVENTS_FMT4 8 19 #define MAX_PEBS_EVENTS 32 20 #define MAX_PEBS_EVENTS_MASK GENMASK_ULL(MAX_PEBS_EVENTS - 1, 0) 21 #define MAX_FIXED_PEBS_EVENTS 16 22 23 /* 24 * A debug store configuration. 25 * 26 * We only support architectures that use 64bit fields. 27 */ 28 struct debug_store { 29 u64 bts_buffer_base; 30 u64 bts_index; 31 u64 bts_absolute_maximum; 32 u64 bts_interrupt_threshold; 33 u64 pebs_buffer_base; 34 u64 pebs_index; 35 u64 pebs_absolute_maximum; 36 u64 pebs_interrupt_threshold; 37 u64 pebs_event_reset[MAX_PEBS_EVENTS + MAX_FIXED_PEBS_EVENTS]; 38 } __aligned(PAGE_SIZE); 39 40 DECLARE_PER_CPU_PAGE_ALIGNED(struct debug_store, cpu_debug_store); 41 42 struct debug_store_buffers { 43 char bts_buffer[BTS_BUFFER_SIZE]; 44 char pebs_buffer[PEBS_BUFFER_SIZE]; 45 }; 46 47 #endif 48