1 #ifndef _ASM_X86_INSN_EVAL_H 2 #define _ASM_X86_INSN_EVAL_H 3 /* 4 * A collection of utility functions for x86 instruction analysis to be 5 * used in a kernel context. Useful when, for instance, making sense 6 * of the registers indicated by operands. 7 */ 8 9 #include <linux/compiler.h> 10 #include <linux/bug.h> 11 #include <linux/err.h> 12 #include <asm/insn.h> 13 #include <asm/ptrace.h> 14 15 #define INSN_CODE_SEG_ADDR_SZ(params) ((params >> 4) & 0xf) 16 #define INSN_CODE_SEG_OPND_SZ(params) (params & 0xf) 17 #define INSN_CODE_SEG_PARAMS(oper_sz, addr_sz) (oper_sz | (addr_sz << 4)) 18 19 int pt_regs_offset(struct pt_regs *regs, int regno); 20 21 bool insn_has_rep_prefix(struct insn *insn); 22 void __user *insn_get_addr_ref(struct insn *insn, struct pt_regs *regs); 23 int insn_get_modrm_rm_off(struct insn *insn, struct pt_regs *regs); 24 int insn_get_modrm_reg_off(struct insn *insn, struct pt_regs *regs); 25 unsigned long *insn_get_modrm_reg_ptr(struct insn *insn, struct pt_regs *regs); 26 unsigned long insn_get_seg_base(struct pt_regs *regs, int seg_reg_idx); 27 int insn_get_code_seg_params(struct pt_regs *regs); 28 int insn_get_effective_ip(struct pt_regs *regs, unsigned long *ip); 29 int insn_fetch_from_user(struct pt_regs *regs, 30 unsigned char buf[MAX_INSN_SIZE]); 31 int insn_fetch_from_user_inatomic(struct pt_regs *regs, 32 unsigned char buf[MAX_INSN_SIZE]); 33 bool insn_decode_from_regs(struct insn *insn, struct pt_regs *regs, 34 unsigned char buf[MAX_INSN_SIZE], int buf_size); 35 36 enum insn_mmio_type { 37 INSN_MMIO_DECODE_FAILED, 38 INSN_MMIO_WRITE, 39 INSN_MMIO_WRITE_IMM, 40 INSN_MMIO_READ, 41 INSN_MMIO_READ_ZERO_EXTEND, 42 INSN_MMIO_READ_SIGN_EXTEND, 43 INSN_MMIO_MOVS, 44 }; 45 46 enum insn_mmio_type insn_decode_mmio(struct insn *insn, int *bytes); 47 48 bool insn_is_nop(struct insn *insn); 49 50 /* 51 * Write @val into *@reg following the x86 rules for writes to 52 * general-purpose registers (Intel SDM Vol. 1, "General-Purpose 53 * Registers in 64-Bit Mode"): an 8- or 16-bit write leaves the rest of 54 * the register untouched, a 32-bit write zero-extends the result into 55 * the upper 32 bits, and a 64-bit write replaces the whole register. 56 * 57 * @bytes is the width of the write, not a property of the instruction: 58 * an instruction that, say, sign-extends a 32-bit immediate into a 59 * 64-bit register does a 64-bit write here. 60 * 61 * @reg need not be 8-byte aligned: KVM's instruction emulator offsets 62 * the pointer by one byte to address the high-byte registers (AH, CH, 63 * DH, BH). Use narrow stores for the sub-word cases so the access 64 * width matches @bytes and the adjacent bytes are left alone. 65 */ 66 static inline void insn_assign_reg(unsigned long *reg, u64 val, int bytes) 67 { 68 switch (bytes) { 69 case 1: 70 *(u8 *)reg = (u8)val; 71 break; 72 case 2: 73 *(u16 *)reg = (u16)val; 74 break; 75 case 4: 76 /* A 32-bit write zero-extends into the upper 32 bits. */ 77 *reg = (u32)val; 78 break; 79 case 8: 80 *reg = val; 81 break; 82 } 83 } 84 85 #endif /* _ASM_X86_INSN_EVAL_H */ 86