1 /* SPDX-License-Identifier: GPL-2.0 */ 2 3 /* 4 * This file contains definitions from Hyper-V Hypervisor Top-Level Functional 5 * Specification (TLFS): 6 * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs 7 */ 8 9 #ifndef _ASM_X86_HYPERV_TLFS_H 10 #define _ASM_X86_HYPERV_TLFS_H 11 12 #include <linux/types.h> 13 #include <asm/page.h> 14 /* 15 * The below CPUID leaves are present if VersionAndFeatures.HypervisorPresent 16 * is set by CPUID(HvCpuIdFunctionVersionAndFeatures). 17 */ 18 #define HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS 0x40000000 19 #define HYPERV_CPUID_INTERFACE 0x40000001 20 #define HYPERV_CPUID_VERSION 0x40000002 21 #define HYPERV_CPUID_FEATURES 0x40000003 22 #define HYPERV_CPUID_ENLIGHTMENT_INFO 0x40000004 23 #define HYPERV_CPUID_IMPLEMENT_LIMITS 0x40000005 24 #define HYPERV_CPUID_NESTED_FEATURES 0x4000000A 25 26 #define HYPERV_CPUID_VIRT_STACK_INTERFACE 0x40000081 27 #define HYPERV_VS_INTERFACE_EAX_SIGNATURE 0x31235356 /* "VS#1" */ 28 29 #define HYPERV_CPUID_VIRT_STACK_PROPERTIES 0x40000082 30 /* Support for the extended IOAPIC RTE format */ 31 #define HYPERV_VS_PROPERTIES_EAX_EXTENDED_IOAPIC_RTE BIT(2) 32 33 #define HYPERV_HYPERVISOR_PRESENT_BIT 0x80000000 34 #define HYPERV_CPUID_MIN 0x40000005 35 #define HYPERV_CPUID_MAX 0x4000ffff 36 37 /* 38 * Group D Features. The bit assignments are custom to each architecture. 39 * On x86/x64 these are HYPERV_CPUID_FEATURES.EDX bits. 40 */ 41 /* The MWAIT instruction is available (per section MONITOR / MWAIT) */ 42 #define HV_X64_MWAIT_AVAILABLE BIT(0) 43 /* Guest debugging support is available */ 44 #define HV_X64_GUEST_DEBUGGING_AVAILABLE BIT(1) 45 /* Performance Monitor support is available*/ 46 #define HV_X64_PERF_MONITOR_AVAILABLE BIT(2) 47 /* Support for physical CPU dynamic partitioning events is available*/ 48 #define HV_X64_CPU_DYNAMIC_PARTITIONING_AVAILABLE BIT(3) 49 /* 50 * Support for passing hypercall input parameter block via XMM 51 * registers is available 52 */ 53 #define HV_X64_HYPERCALL_PARAMS_XMM_AVAILABLE BIT(4) 54 /* Support for a virtual guest idle state is available */ 55 #define HV_X64_GUEST_IDLE_STATE_AVAILABLE BIT(5) 56 /* Frequency MSRs available */ 57 #define HV_FEATURE_FREQUENCY_MSRS_AVAILABLE BIT(8) 58 /* Crash MSR available */ 59 #define HV_FEATURE_GUEST_CRASH_MSR_AVAILABLE BIT(10) 60 /* Support for debug MSRs available */ 61 #define HV_FEATURE_DEBUG_MSRS_AVAILABLE BIT(11) 62 /* stimer Direct Mode is available */ 63 #define HV_STIMER_DIRECT_MODE_AVAILABLE BIT(19) 64 65 /* 66 * Implementation recommendations. Indicates which behaviors the hypervisor 67 * recommends the OS implement for optimal performance. 68 * These are HYPERV_CPUID_ENLIGHTMENT_INFO.EAX bits. 69 */ 70 /* 71 * Recommend using hypercall for address space switches rather 72 * than MOV to CR3 instruction 73 */ 74 #define HV_X64_AS_SWITCH_RECOMMENDED BIT(0) 75 /* Recommend using hypercall for local TLB flushes rather 76 * than INVLPG or MOV to CR3 instructions */ 77 #define HV_X64_LOCAL_TLB_FLUSH_RECOMMENDED BIT(1) 78 /* 79 * Recommend using hypercall for remote TLB flushes rather 80 * than inter-processor interrupts 81 */ 82 #define HV_X64_REMOTE_TLB_FLUSH_RECOMMENDED BIT(2) 83 /* 84 * Recommend using MSRs for accessing APIC registers 85 * EOI, ICR and TPR rather than their memory-mapped counterparts 86 */ 87 #define HV_X64_APIC_ACCESS_RECOMMENDED BIT(3) 88 /* Recommend using the hypervisor-provided MSR to initiate a system RESET */ 89 #define HV_X64_SYSTEM_RESET_RECOMMENDED BIT(4) 90 /* 91 * Recommend using relaxed timing for this partition. If used, 92 * the VM should disable any watchdog timeouts that rely on the 93 * timely delivery of external interrupts 94 */ 95 #define HV_X64_RELAXED_TIMING_RECOMMENDED BIT(5) 96 97 /* 98 * Recommend not using Auto End-Of-Interrupt feature 99 */ 100 #define HV_DEPRECATING_AEOI_RECOMMENDED BIT(9) 101 102 /* 103 * Recommend using cluster IPI hypercalls. 104 */ 105 #define HV_X64_CLUSTER_IPI_RECOMMENDED BIT(10) 106 107 /* Recommend using the newer ExProcessorMasks interface */ 108 #define HV_X64_EX_PROCESSOR_MASKS_RECOMMENDED BIT(11) 109 110 /* Recommend using enlightened VMCS */ 111 #define HV_X64_ENLIGHTENED_VMCS_RECOMMENDED BIT(14) 112 113 /* 114 * Virtual processor will never share a physical core with another virtual 115 * processor, except for virtual processors that are reported as sibling SMT 116 * threads. 117 */ 118 #define HV_X64_NO_NONARCH_CORESHARING BIT(18) 119 120 /* Nested features. These are HYPERV_CPUID_NESTED_FEATURES.EAX bits. */ 121 #define HV_X64_NESTED_DIRECT_FLUSH BIT(17) 122 #define HV_X64_NESTED_GUEST_MAPPING_FLUSH BIT(18) 123 #define HV_X64_NESTED_MSR_BITMAP BIT(19) 124 125 /* Hyper-V specific model specific registers (MSRs) */ 126 127 /* MSR used to identify the guest OS. */ 128 #define HV_X64_MSR_GUEST_OS_ID 0x40000000 129 130 /* MSR used to setup pages used to communicate with the hypervisor. */ 131 #define HV_X64_MSR_HYPERCALL 0x40000001 132 133 /* MSR used to provide vcpu index */ 134 #define HV_X64_MSR_VP_INDEX 0x40000002 135 136 /* MSR used to reset the guest OS. */ 137 #define HV_X64_MSR_RESET 0x40000003 138 139 /* MSR used to provide vcpu runtime in 100ns units */ 140 #define HV_X64_MSR_VP_RUNTIME 0x40000010 141 142 /* MSR used to read the per-partition time reference counter */ 143 #define HV_X64_MSR_TIME_REF_COUNT 0x40000020 144 145 /* A partition's reference time stamp counter (TSC) page */ 146 #define HV_X64_MSR_REFERENCE_TSC 0x40000021 147 148 /* MSR used to retrieve the TSC frequency */ 149 #define HV_X64_MSR_TSC_FREQUENCY 0x40000022 150 151 /* MSR used to retrieve the local APIC timer frequency */ 152 #define HV_X64_MSR_APIC_FREQUENCY 0x40000023 153 154 /* Define the virtual APIC registers */ 155 #define HV_X64_MSR_EOI 0x40000070 156 #define HV_X64_MSR_ICR 0x40000071 157 #define HV_X64_MSR_TPR 0x40000072 158 #define HV_X64_MSR_VP_ASSIST_PAGE 0x40000073 159 160 /* Define synthetic interrupt controller model specific registers. */ 161 #define HV_X64_MSR_SCONTROL 0x40000080 162 #define HV_X64_MSR_SVERSION 0x40000081 163 #define HV_X64_MSR_SIEFP 0x40000082 164 #define HV_X64_MSR_SIMP 0x40000083 165 #define HV_X64_MSR_EOM 0x40000084 166 #define HV_X64_MSR_SINT0 0x40000090 167 #define HV_X64_MSR_SINT1 0x40000091 168 #define HV_X64_MSR_SINT2 0x40000092 169 #define HV_X64_MSR_SINT3 0x40000093 170 #define HV_X64_MSR_SINT4 0x40000094 171 #define HV_X64_MSR_SINT5 0x40000095 172 #define HV_X64_MSR_SINT6 0x40000096 173 #define HV_X64_MSR_SINT7 0x40000097 174 #define HV_X64_MSR_SINT8 0x40000098 175 #define HV_X64_MSR_SINT9 0x40000099 176 #define HV_X64_MSR_SINT10 0x4000009A 177 #define HV_X64_MSR_SINT11 0x4000009B 178 #define HV_X64_MSR_SINT12 0x4000009C 179 #define HV_X64_MSR_SINT13 0x4000009D 180 #define HV_X64_MSR_SINT14 0x4000009E 181 #define HV_X64_MSR_SINT15 0x4000009F 182 183 /* 184 * Synthetic Timer MSRs. Four timers per vcpu. 185 */ 186 #define HV_X64_MSR_STIMER0_CONFIG 0x400000B0 187 #define HV_X64_MSR_STIMER0_COUNT 0x400000B1 188 #define HV_X64_MSR_STIMER1_CONFIG 0x400000B2 189 #define HV_X64_MSR_STIMER1_COUNT 0x400000B3 190 #define HV_X64_MSR_STIMER2_CONFIG 0x400000B4 191 #define HV_X64_MSR_STIMER2_COUNT 0x400000B5 192 #define HV_X64_MSR_STIMER3_CONFIG 0x400000B6 193 #define HV_X64_MSR_STIMER3_COUNT 0x400000B7 194 195 /* Hyper-V guest idle MSR */ 196 #define HV_X64_MSR_GUEST_IDLE 0x400000F0 197 198 /* Hyper-V guest crash notification MSR's */ 199 #define HV_X64_MSR_CRASH_P0 0x40000100 200 #define HV_X64_MSR_CRASH_P1 0x40000101 201 #define HV_X64_MSR_CRASH_P2 0x40000102 202 #define HV_X64_MSR_CRASH_P3 0x40000103 203 #define HV_X64_MSR_CRASH_P4 0x40000104 204 #define HV_X64_MSR_CRASH_CTL 0x40000105 205 206 /* TSC emulation after migration */ 207 #define HV_X64_MSR_REENLIGHTENMENT_CONTROL 0x40000106 208 #define HV_X64_MSR_TSC_EMULATION_CONTROL 0x40000107 209 #define HV_X64_MSR_TSC_EMULATION_STATUS 0x40000108 210 211 /* TSC invariant control */ 212 #define HV_X64_MSR_TSC_INVARIANT_CONTROL 0x40000118 213 214 /* 215 * Declare the MSR used to setup pages used to communicate with the hypervisor. 216 */ 217 union hv_x64_msr_hypercall_contents { 218 u64 as_uint64; 219 struct { 220 u64 enable:1; 221 u64 reserved:11; 222 u64 guest_physical_address:52; 223 } __packed; 224 }; 225 226 struct hv_reenlightenment_control { 227 __u64 vector:8; 228 __u64 reserved1:8; 229 __u64 enabled:1; 230 __u64 reserved2:15; 231 __u64 target_vp:32; 232 } __packed; 233 234 struct hv_tsc_emulation_control { 235 __u64 enabled:1; 236 __u64 reserved:63; 237 } __packed; 238 239 struct hv_tsc_emulation_status { 240 __u64 inprogress:1; 241 __u64 reserved:63; 242 } __packed; 243 244 #define HV_X64_MSR_HYPERCALL_ENABLE 0x00000001 245 #define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT 12 246 #define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_MASK \ 247 (~((1ull << HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT) - 1)) 248 249 #define HV_X64_MSR_CRASH_PARAMS \ 250 (1 + (HV_X64_MSR_CRASH_P4 - HV_X64_MSR_CRASH_P0)) 251 252 #define HV_IPI_LOW_VECTOR 0x10 253 #define HV_IPI_HIGH_VECTOR 0xff 254 255 #define HV_X64_MSR_VP_ASSIST_PAGE_ENABLE 0x00000001 256 #define HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_SHIFT 12 257 #define HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_MASK \ 258 (~((1ull << HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_SHIFT) - 1)) 259 260 /* Hyper-V Enlightened VMCS version mask in nested features CPUID */ 261 #define HV_X64_ENLIGHTENED_VMCS_VERSION 0xff 262 263 #define HV_X64_MSR_TSC_REFERENCE_ENABLE 0x00000001 264 #define HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT 12 265 266 267 /* Define hypervisor message types. */ 268 enum hv_message_type { 269 HVMSG_NONE = 0x00000000, 270 271 /* Memory access messages. */ 272 HVMSG_UNMAPPED_GPA = 0x80000000, 273 HVMSG_GPA_INTERCEPT = 0x80000001, 274 275 /* Timer notification messages. */ 276 HVMSG_TIMER_EXPIRED = 0x80000010, 277 278 /* Error messages. */ 279 HVMSG_INVALID_VP_REGISTER_VALUE = 0x80000020, 280 HVMSG_UNRECOVERABLE_EXCEPTION = 0x80000021, 281 HVMSG_UNSUPPORTED_FEATURE = 0x80000022, 282 283 /* Trace buffer complete messages. */ 284 HVMSG_EVENTLOG_BUFFERCOMPLETE = 0x80000040, 285 286 /* Platform-specific processor intercept messages. */ 287 HVMSG_X64_IOPORT_INTERCEPT = 0x80010000, 288 HVMSG_X64_MSR_INTERCEPT = 0x80010001, 289 HVMSG_X64_CPUID_INTERCEPT = 0x80010002, 290 HVMSG_X64_EXCEPTION_INTERCEPT = 0x80010003, 291 HVMSG_X64_APIC_EOI = 0x80010004, 292 HVMSG_X64_LEGACY_FP_ERROR = 0x80010005 293 }; 294 295 struct hv_nested_enlightenments_control { 296 struct { 297 __u32 directhypercall:1; 298 __u32 reserved:31; 299 } features; 300 struct { 301 __u32 reserved; 302 } hypercallControls; 303 } __packed; 304 305 /* Define virtual processor assist page structure. */ 306 struct hv_vp_assist_page { 307 __u32 apic_assist; 308 __u32 reserved1; 309 __u64 vtl_control[3]; 310 struct hv_nested_enlightenments_control nested_control; 311 __u8 enlighten_vmentry; 312 __u8 reserved2[7]; 313 __u64 current_nested_vmcs; 314 } __packed; 315 316 struct hv_enlightened_vmcs { 317 u32 revision_id; 318 u32 abort; 319 320 u16 host_es_selector; 321 u16 host_cs_selector; 322 u16 host_ss_selector; 323 u16 host_ds_selector; 324 u16 host_fs_selector; 325 u16 host_gs_selector; 326 u16 host_tr_selector; 327 328 u16 padding16_1; 329 330 u64 host_ia32_pat; 331 u64 host_ia32_efer; 332 333 u64 host_cr0; 334 u64 host_cr3; 335 u64 host_cr4; 336 337 u64 host_ia32_sysenter_esp; 338 u64 host_ia32_sysenter_eip; 339 u64 host_rip; 340 u32 host_ia32_sysenter_cs; 341 342 u32 pin_based_vm_exec_control; 343 u32 vm_exit_controls; 344 u32 secondary_vm_exec_control; 345 346 u64 io_bitmap_a; 347 u64 io_bitmap_b; 348 u64 msr_bitmap; 349 350 u16 guest_es_selector; 351 u16 guest_cs_selector; 352 u16 guest_ss_selector; 353 u16 guest_ds_selector; 354 u16 guest_fs_selector; 355 u16 guest_gs_selector; 356 u16 guest_ldtr_selector; 357 u16 guest_tr_selector; 358 359 u32 guest_es_limit; 360 u32 guest_cs_limit; 361 u32 guest_ss_limit; 362 u32 guest_ds_limit; 363 u32 guest_fs_limit; 364 u32 guest_gs_limit; 365 u32 guest_ldtr_limit; 366 u32 guest_tr_limit; 367 u32 guest_gdtr_limit; 368 u32 guest_idtr_limit; 369 370 u32 guest_es_ar_bytes; 371 u32 guest_cs_ar_bytes; 372 u32 guest_ss_ar_bytes; 373 u32 guest_ds_ar_bytes; 374 u32 guest_fs_ar_bytes; 375 u32 guest_gs_ar_bytes; 376 u32 guest_ldtr_ar_bytes; 377 u32 guest_tr_ar_bytes; 378 379 u64 guest_es_base; 380 u64 guest_cs_base; 381 u64 guest_ss_base; 382 u64 guest_ds_base; 383 u64 guest_fs_base; 384 u64 guest_gs_base; 385 u64 guest_ldtr_base; 386 u64 guest_tr_base; 387 u64 guest_gdtr_base; 388 u64 guest_idtr_base; 389 390 u64 padding64_1[3]; 391 392 u64 vm_exit_msr_store_addr; 393 u64 vm_exit_msr_load_addr; 394 u64 vm_entry_msr_load_addr; 395 396 u64 cr3_target_value0; 397 u64 cr3_target_value1; 398 u64 cr3_target_value2; 399 u64 cr3_target_value3; 400 401 u32 page_fault_error_code_mask; 402 u32 page_fault_error_code_match; 403 404 u32 cr3_target_count; 405 u32 vm_exit_msr_store_count; 406 u32 vm_exit_msr_load_count; 407 u32 vm_entry_msr_load_count; 408 409 u64 tsc_offset; 410 u64 virtual_apic_page_addr; 411 u64 vmcs_link_pointer; 412 413 u64 guest_ia32_debugctl; 414 u64 guest_ia32_pat; 415 u64 guest_ia32_efer; 416 417 u64 guest_pdptr0; 418 u64 guest_pdptr1; 419 u64 guest_pdptr2; 420 u64 guest_pdptr3; 421 422 u64 guest_pending_dbg_exceptions; 423 u64 guest_sysenter_esp; 424 u64 guest_sysenter_eip; 425 426 u32 guest_activity_state; 427 u32 guest_sysenter_cs; 428 429 u64 cr0_guest_host_mask; 430 u64 cr4_guest_host_mask; 431 u64 cr0_read_shadow; 432 u64 cr4_read_shadow; 433 u64 guest_cr0; 434 u64 guest_cr3; 435 u64 guest_cr4; 436 u64 guest_dr7; 437 438 u64 host_fs_base; 439 u64 host_gs_base; 440 u64 host_tr_base; 441 u64 host_gdtr_base; 442 u64 host_idtr_base; 443 u64 host_rsp; 444 445 u64 ept_pointer; 446 447 u16 virtual_processor_id; 448 u16 padding16_2[3]; 449 450 u64 padding64_2[5]; 451 u64 guest_physical_address; 452 453 u32 vm_instruction_error; 454 u32 vm_exit_reason; 455 u32 vm_exit_intr_info; 456 u32 vm_exit_intr_error_code; 457 u32 idt_vectoring_info_field; 458 u32 idt_vectoring_error_code; 459 u32 vm_exit_instruction_len; 460 u32 vmx_instruction_info; 461 462 u64 exit_qualification; 463 u64 exit_io_instruction_ecx; 464 u64 exit_io_instruction_esi; 465 u64 exit_io_instruction_edi; 466 u64 exit_io_instruction_eip; 467 468 u64 guest_linear_address; 469 u64 guest_rsp; 470 u64 guest_rflags; 471 472 u32 guest_interruptibility_info; 473 u32 cpu_based_vm_exec_control; 474 u32 exception_bitmap; 475 u32 vm_entry_controls; 476 u32 vm_entry_intr_info_field; 477 u32 vm_entry_exception_error_code; 478 u32 vm_entry_instruction_len; 479 u32 tpr_threshold; 480 481 u64 guest_rip; 482 483 u32 hv_clean_fields; 484 u32 hv_padding_32; 485 u32 hv_synthetic_controls; 486 struct { 487 u32 nested_flush_hypercall:1; 488 u32 msr_bitmap:1; 489 u32 reserved:30; 490 } __packed hv_enlightenments_control; 491 u32 hv_vp_id; 492 493 u64 hv_vm_id; 494 u64 partition_assist_page; 495 u64 padding64_4[4]; 496 u64 guest_bndcfgs; 497 u64 padding64_5[7]; 498 u64 xss_exit_bitmap; 499 u64 padding64_6[7]; 500 } __packed; 501 502 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_NONE 0 503 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_IO_BITMAP BIT(0) 504 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_MSR_BITMAP BIT(1) 505 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_GRP2 BIT(2) 506 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_GRP1 BIT(3) 507 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_PROC BIT(4) 508 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_EVENT BIT(5) 509 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_ENTRY BIT(6) 510 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_EXCPN BIT(7) 511 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CRDR BIT(8) 512 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_XLAT BIT(9) 513 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_BASIC BIT(10) 514 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_GRP1 BIT(11) 515 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_GRP2 BIT(12) 516 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_HOST_POINTER BIT(13) 517 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_HOST_GRP1 BIT(14) 518 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_ENLIGHTENMENTSCONTROL BIT(15) 519 520 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL 0xFFFF 521 522 struct hv_partition_assist_pg { 523 u32 tlb_lock_count; 524 }; 525 526 527 #include <asm-generic/hyperv-tlfs.h> 528 529 #endif 530