1 /* SPDX-License-Identifier: GPL-2.0 */ 2 3 /* 4 * This file contains definitions from Hyper-V Hypervisor Top-Level Functional 5 * Specification (TLFS): 6 * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs 7 */ 8 9 #ifndef _ASM_X86_HYPERV_TLFS_H 10 #define _ASM_X86_HYPERV_TLFS_H 11 12 #include <linux/types.h> 13 #include <asm/page.h> 14 /* 15 * The below CPUID leaves are present if VersionAndFeatures.HypervisorPresent 16 * is set by CPUID(HvCpuIdFunctionVersionAndFeatures). 17 */ 18 #define HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS 0x40000000 19 #define HYPERV_CPUID_INTERFACE 0x40000001 20 #define HYPERV_CPUID_VERSION 0x40000002 21 #define HYPERV_CPUID_FEATURES 0x40000003 22 #define HYPERV_CPUID_ENLIGHTMENT_INFO 0x40000004 23 #define HYPERV_CPUID_IMPLEMENT_LIMITS 0x40000005 24 #define HYPERV_CPUID_CPU_MANAGEMENT_FEATURES 0x40000007 25 #define HYPERV_CPUID_NESTED_FEATURES 0x4000000A 26 #define HYPERV_CPUID_ISOLATION_CONFIG 0x4000000C 27 28 #define HYPERV_CPUID_VIRT_STACK_INTERFACE 0x40000081 29 #define HYPERV_VS_INTERFACE_EAX_SIGNATURE 0x31235356 /* "VS#1" */ 30 31 #define HYPERV_CPUID_VIRT_STACK_PROPERTIES 0x40000082 32 /* Support for the extended IOAPIC RTE format */ 33 #define HYPERV_VS_PROPERTIES_EAX_EXTENDED_IOAPIC_RTE BIT(2) 34 35 #define HYPERV_HYPERVISOR_PRESENT_BIT 0x80000000 36 #define HYPERV_CPUID_MIN 0x40000005 37 #define HYPERV_CPUID_MAX 0x4000ffff 38 39 /* 40 * Group D Features. The bit assignments are custom to each architecture. 41 * On x86/x64 these are HYPERV_CPUID_FEATURES.EDX bits. 42 */ 43 /* The MWAIT instruction is available (per section MONITOR / MWAIT) */ 44 #define HV_X64_MWAIT_AVAILABLE BIT(0) 45 /* Guest debugging support is available */ 46 #define HV_X64_GUEST_DEBUGGING_AVAILABLE BIT(1) 47 /* Performance Monitor support is available*/ 48 #define HV_X64_PERF_MONITOR_AVAILABLE BIT(2) 49 /* Support for physical CPU dynamic partitioning events is available*/ 50 #define HV_X64_CPU_DYNAMIC_PARTITIONING_AVAILABLE BIT(3) 51 /* 52 * Support for passing hypercall input parameter block via XMM 53 * registers is available 54 */ 55 #define HV_X64_HYPERCALL_XMM_INPUT_AVAILABLE BIT(4) 56 /* Support for a virtual guest idle state is available */ 57 #define HV_X64_GUEST_IDLE_STATE_AVAILABLE BIT(5) 58 /* Frequency MSRs available */ 59 #define HV_FEATURE_FREQUENCY_MSRS_AVAILABLE BIT(8) 60 /* Crash MSR available */ 61 #define HV_FEATURE_GUEST_CRASH_MSR_AVAILABLE BIT(10) 62 /* Support for debug MSRs available */ 63 #define HV_FEATURE_DEBUG_MSRS_AVAILABLE BIT(11) 64 /* Support for extended gva ranges for flush hypercalls available */ 65 #define HV_FEATURE_EXT_GVA_RANGES_FLUSH BIT(14) 66 /* 67 * Support for returning hypercall output block via XMM 68 * registers is available 69 */ 70 #define HV_X64_HYPERCALL_XMM_OUTPUT_AVAILABLE BIT(15) 71 /* stimer Direct Mode is available */ 72 #define HV_STIMER_DIRECT_MODE_AVAILABLE BIT(19) 73 74 /* 75 * Implementation recommendations. Indicates which behaviors the hypervisor 76 * recommends the OS implement for optimal performance. 77 * These are HYPERV_CPUID_ENLIGHTMENT_INFO.EAX bits. 78 */ 79 /* 80 * Recommend using hypercall for address space switches rather 81 * than MOV to CR3 instruction 82 */ 83 #define HV_X64_AS_SWITCH_RECOMMENDED BIT(0) 84 /* Recommend using hypercall for local TLB flushes rather 85 * than INVLPG or MOV to CR3 instructions */ 86 #define HV_X64_LOCAL_TLB_FLUSH_RECOMMENDED BIT(1) 87 /* 88 * Recommend using hypercall for remote TLB flushes rather 89 * than inter-processor interrupts 90 */ 91 #define HV_X64_REMOTE_TLB_FLUSH_RECOMMENDED BIT(2) 92 /* 93 * Recommend using MSRs for accessing APIC registers 94 * EOI, ICR and TPR rather than their memory-mapped counterparts 95 */ 96 #define HV_X64_APIC_ACCESS_RECOMMENDED BIT(3) 97 /* Recommend using the hypervisor-provided MSR to initiate a system RESET */ 98 #define HV_X64_SYSTEM_RESET_RECOMMENDED BIT(4) 99 /* 100 * Recommend using relaxed timing for this partition. If used, 101 * the VM should disable any watchdog timeouts that rely on the 102 * timely delivery of external interrupts 103 */ 104 #define HV_X64_RELAXED_TIMING_RECOMMENDED BIT(5) 105 106 /* 107 * Recommend not using Auto End-Of-Interrupt feature 108 */ 109 #define HV_DEPRECATING_AEOI_RECOMMENDED BIT(9) 110 111 /* 112 * Recommend using cluster IPI hypercalls. 113 */ 114 #define HV_X64_CLUSTER_IPI_RECOMMENDED BIT(10) 115 116 /* Recommend using the newer ExProcessorMasks interface */ 117 #define HV_X64_EX_PROCESSOR_MASKS_RECOMMENDED BIT(11) 118 119 /* Indicates that the hypervisor is nested within a Hyper-V partition. */ 120 #define HV_X64_HYPERV_NESTED BIT(12) 121 122 /* Recommend using enlightened VMCS */ 123 #define HV_X64_ENLIGHTENED_VMCS_RECOMMENDED BIT(14) 124 125 /* Use hypercalls for MMIO config space access */ 126 #define HV_X64_USE_MMIO_HYPERCALLS BIT(21) 127 128 /* 129 * CPU management features identification. 130 * These are HYPERV_CPUID_CPU_MANAGEMENT_FEATURES.EAX bits. 131 */ 132 #define HV_X64_START_LOGICAL_PROCESSOR BIT(0) 133 #define HV_X64_CREATE_ROOT_VIRTUAL_PROCESSOR BIT(1) 134 #define HV_X64_PERFORMANCE_COUNTER_SYNC BIT(2) 135 #define HV_X64_RESERVED_IDENTITY_BIT BIT(31) 136 137 /* 138 * Virtual processor will never share a physical core with another virtual 139 * processor, except for virtual processors that are reported as sibling SMT 140 * threads. 141 */ 142 #define HV_X64_NO_NONARCH_CORESHARING BIT(18) 143 144 /* Nested features. These are HYPERV_CPUID_NESTED_FEATURES.EAX bits. */ 145 #define HV_X64_NESTED_DIRECT_FLUSH BIT(17) 146 #define HV_X64_NESTED_GUEST_MAPPING_FLUSH BIT(18) 147 #define HV_X64_NESTED_MSR_BITMAP BIT(19) 148 149 /* Nested features #2. These are HYPERV_CPUID_NESTED_FEATURES.EBX bits. */ 150 #define HV_X64_NESTED_EVMCS1_PERF_GLOBAL_CTRL BIT(0) 151 152 /* 153 * This is specific to AMD and specifies that enlightened TLB flush is 154 * supported. If guest opts in to this feature, ASID invalidations only 155 * flushes gva -> hpa mapping entries. To flush the TLB entries derived 156 * from NPT, hypercalls should be used (HvFlushGuestPhysicalAddressSpace 157 * or HvFlushGuestPhysicalAddressList). 158 */ 159 #define HV_X64_NESTED_ENLIGHTENED_TLB BIT(22) 160 161 /* HYPERV_CPUID_ISOLATION_CONFIG.EAX bits. */ 162 #define HV_PARAVISOR_PRESENT BIT(0) 163 164 /* HYPERV_CPUID_ISOLATION_CONFIG.EBX bits. */ 165 #define HV_ISOLATION_TYPE GENMASK(3, 0) 166 #define HV_SHARED_GPA_BOUNDARY_ACTIVE BIT(5) 167 #define HV_SHARED_GPA_BOUNDARY_BITS GENMASK(11, 6) 168 169 enum hv_isolation_type { 170 HV_ISOLATION_TYPE_NONE = 0, 171 HV_ISOLATION_TYPE_VBS = 1, 172 HV_ISOLATION_TYPE_SNP = 2, 173 HV_ISOLATION_TYPE_TDX = 3 174 }; 175 176 /* Hyper-V specific model specific registers (MSRs) */ 177 178 /* MSR used to identify the guest OS. */ 179 #define HV_X64_MSR_GUEST_OS_ID 0x40000000 180 181 /* MSR used to setup pages used to communicate with the hypervisor. */ 182 #define HV_X64_MSR_HYPERCALL 0x40000001 183 184 /* MSR used to provide vcpu index */ 185 #define HV_X64_MSR_VP_INDEX 0x40000002 186 187 /* MSR used to reset the guest OS. */ 188 #define HV_X64_MSR_RESET 0x40000003 189 190 /* MSR used to provide vcpu runtime in 100ns units */ 191 #define HV_X64_MSR_VP_RUNTIME 0x40000010 192 193 /* MSR used to read the per-partition time reference counter */ 194 #define HV_X64_MSR_TIME_REF_COUNT 0x40000020 195 196 /* A partition's reference time stamp counter (TSC) page */ 197 #define HV_X64_MSR_REFERENCE_TSC 0x40000021 198 199 /* MSR used to retrieve the TSC frequency */ 200 #define HV_X64_MSR_TSC_FREQUENCY 0x40000022 201 202 /* MSR used to retrieve the local APIC timer frequency */ 203 #define HV_X64_MSR_APIC_FREQUENCY 0x40000023 204 205 /* Define the virtual APIC registers */ 206 #define HV_X64_MSR_EOI 0x40000070 207 #define HV_X64_MSR_ICR 0x40000071 208 #define HV_X64_MSR_TPR 0x40000072 209 #define HV_X64_MSR_VP_ASSIST_PAGE 0x40000073 210 211 /* Define synthetic interrupt controller model specific registers. */ 212 #define HV_X64_MSR_SCONTROL 0x40000080 213 #define HV_X64_MSR_SVERSION 0x40000081 214 #define HV_X64_MSR_SIEFP 0x40000082 215 #define HV_X64_MSR_SIMP 0x40000083 216 #define HV_X64_MSR_EOM 0x40000084 217 #define HV_X64_MSR_SINT0 0x40000090 218 #define HV_X64_MSR_SINT1 0x40000091 219 #define HV_X64_MSR_SINT2 0x40000092 220 #define HV_X64_MSR_SINT3 0x40000093 221 #define HV_X64_MSR_SINT4 0x40000094 222 #define HV_X64_MSR_SINT5 0x40000095 223 #define HV_X64_MSR_SINT6 0x40000096 224 #define HV_X64_MSR_SINT7 0x40000097 225 #define HV_X64_MSR_SINT8 0x40000098 226 #define HV_X64_MSR_SINT9 0x40000099 227 #define HV_X64_MSR_SINT10 0x4000009A 228 #define HV_X64_MSR_SINT11 0x4000009B 229 #define HV_X64_MSR_SINT12 0x4000009C 230 #define HV_X64_MSR_SINT13 0x4000009D 231 #define HV_X64_MSR_SINT14 0x4000009E 232 #define HV_X64_MSR_SINT15 0x4000009F 233 234 /* 235 * Define synthetic interrupt controller model specific registers for 236 * nested hypervisor. 237 */ 238 #define HV_X64_MSR_NESTED_SCONTROL 0x40001080 239 #define HV_X64_MSR_NESTED_SVERSION 0x40001081 240 #define HV_X64_MSR_NESTED_SIEFP 0x40001082 241 #define HV_X64_MSR_NESTED_SIMP 0x40001083 242 #define HV_X64_MSR_NESTED_EOM 0x40001084 243 #define HV_X64_MSR_NESTED_SINT0 0x40001090 244 245 /* 246 * Synthetic Timer MSRs. Four timers per vcpu. 247 */ 248 #define HV_X64_MSR_STIMER0_CONFIG 0x400000B0 249 #define HV_X64_MSR_STIMER0_COUNT 0x400000B1 250 #define HV_X64_MSR_STIMER1_CONFIG 0x400000B2 251 #define HV_X64_MSR_STIMER1_COUNT 0x400000B3 252 #define HV_X64_MSR_STIMER2_CONFIG 0x400000B4 253 #define HV_X64_MSR_STIMER2_COUNT 0x400000B5 254 #define HV_X64_MSR_STIMER3_CONFIG 0x400000B6 255 #define HV_X64_MSR_STIMER3_COUNT 0x400000B7 256 257 /* Hyper-V guest idle MSR */ 258 #define HV_X64_MSR_GUEST_IDLE 0x400000F0 259 260 /* Hyper-V guest crash notification MSR's */ 261 #define HV_X64_MSR_CRASH_P0 0x40000100 262 #define HV_X64_MSR_CRASH_P1 0x40000101 263 #define HV_X64_MSR_CRASH_P2 0x40000102 264 #define HV_X64_MSR_CRASH_P3 0x40000103 265 #define HV_X64_MSR_CRASH_P4 0x40000104 266 #define HV_X64_MSR_CRASH_CTL 0x40000105 267 268 /* TSC emulation after migration */ 269 #define HV_X64_MSR_REENLIGHTENMENT_CONTROL 0x40000106 270 #define HV_X64_MSR_TSC_EMULATION_CONTROL 0x40000107 271 #define HV_X64_MSR_TSC_EMULATION_STATUS 0x40000108 272 273 /* TSC invariant control */ 274 #define HV_X64_MSR_TSC_INVARIANT_CONTROL 0x40000118 275 276 /* HV_X64_MSR_TSC_INVARIANT_CONTROL bits */ 277 #define HV_EXPOSE_INVARIANT_TSC BIT_ULL(0) 278 279 /* 280 * To support arch-generic code calling hv_set/get_register: 281 * - On x86, HV_MSR_ indicates an MSR accessed via rdmsrl/wrmsrl 282 * - On ARM, HV_MSR_ indicates a VP register accessed via hypercall 283 */ 284 #define HV_MSR_CRASH_P0 (HV_X64_MSR_CRASH_P0) 285 #define HV_MSR_CRASH_P1 (HV_X64_MSR_CRASH_P1) 286 #define HV_MSR_CRASH_P2 (HV_X64_MSR_CRASH_P2) 287 #define HV_MSR_CRASH_P3 (HV_X64_MSR_CRASH_P3) 288 #define HV_MSR_CRASH_P4 (HV_X64_MSR_CRASH_P4) 289 #define HV_MSR_CRASH_CTL (HV_X64_MSR_CRASH_CTL) 290 291 #define HV_MSR_VP_INDEX (HV_X64_MSR_VP_INDEX) 292 #define HV_MSR_TIME_REF_COUNT (HV_X64_MSR_TIME_REF_COUNT) 293 #define HV_MSR_REFERENCE_TSC (HV_X64_MSR_REFERENCE_TSC) 294 295 #define HV_MSR_SINT0 (HV_X64_MSR_SINT0) 296 #define HV_MSR_SVERSION (HV_X64_MSR_SVERSION) 297 #define HV_MSR_SCONTROL (HV_X64_MSR_SCONTROL) 298 #define HV_MSR_SIEFP (HV_X64_MSR_SIEFP) 299 #define HV_MSR_SIMP (HV_X64_MSR_SIMP) 300 #define HV_MSR_EOM (HV_X64_MSR_EOM) 301 302 #define HV_MSR_NESTED_SCONTROL (HV_X64_MSR_NESTED_SCONTROL) 303 #define HV_MSR_NESTED_SVERSION (HV_X64_MSR_NESTED_SVERSION) 304 #define HV_MSR_NESTED_SIEFP (HV_X64_MSR_NESTED_SIEFP) 305 #define HV_MSR_NESTED_SIMP (HV_X64_MSR_NESTED_SIMP) 306 #define HV_MSR_NESTED_EOM (HV_X64_MSR_NESTED_EOM) 307 #define HV_MSR_NESTED_SINT0 (HV_X64_MSR_NESTED_SINT0) 308 309 #define HV_MSR_STIMER0_CONFIG (HV_X64_MSR_STIMER0_CONFIG) 310 #define HV_MSR_STIMER0_COUNT (HV_X64_MSR_STIMER0_COUNT) 311 312 /* 313 * Registers are only accessible via HVCALL_GET_VP_REGISTERS hvcall and 314 * there is not associated MSR address. 315 */ 316 #define HV_X64_REGISTER_VSM_VP_STATUS 0x000D0003 317 #define HV_X64_VTL_MASK GENMASK(3, 0) 318 319 /* Hyper-V memory host visibility */ 320 enum hv_mem_host_visibility { 321 VMBUS_PAGE_NOT_VISIBLE = 0, 322 VMBUS_PAGE_VISIBLE_READ_ONLY = 1, 323 VMBUS_PAGE_VISIBLE_READ_WRITE = 3 324 }; 325 326 /* HvCallModifySparseGpaPageHostVisibility hypercall */ 327 #define HV_MAX_MODIFY_GPA_REP_COUNT ((PAGE_SIZE / sizeof(u64)) - 2) 328 struct hv_gpa_range_for_visibility { 329 u64 partition_id; 330 u32 host_visibility:2; 331 u32 reserved0:30; 332 u32 reserved1; 333 u64 gpa_page_list[HV_MAX_MODIFY_GPA_REP_COUNT]; 334 } __packed; 335 336 /* 337 * Declare the MSR used to setup pages used to communicate with the hypervisor. 338 */ 339 union hv_x64_msr_hypercall_contents { 340 u64 as_uint64; 341 struct { 342 u64 enable:1; 343 u64 reserved:11; 344 u64 guest_physical_address:52; 345 } __packed; 346 }; 347 348 union hv_vp_assist_msr_contents { 349 u64 as_uint64; 350 struct { 351 u64 enable:1; 352 u64 reserved:11; 353 u64 pfn:52; 354 } __packed; 355 }; 356 357 struct hv_reenlightenment_control { 358 __u64 vector:8; 359 __u64 reserved1:8; 360 __u64 enabled:1; 361 __u64 reserved2:15; 362 __u64 target_vp:32; 363 } __packed; 364 365 struct hv_tsc_emulation_control { 366 __u64 enabled:1; 367 __u64 reserved:63; 368 } __packed; 369 370 struct hv_tsc_emulation_status { 371 __u64 inprogress:1; 372 __u64 reserved:63; 373 } __packed; 374 375 #define HV_X64_MSR_HYPERCALL_ENABLE 0x00000001 376 #define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT 12 377 #define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_MASK \ 378 (~((1ull << HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT) - 1)) 379 380 #define HV_X64_MSR_CRASH_PARAMS \ 381 (1 + (HV_X64_MSR_CRASH_P4 - HV_X64_MSR_CRASH_P0)) 382 383 #define HV_IPI_LOW_VECTOR 0x10 384 #define HV_IPI_HIGH_VECTOR 0xff 385 386 #define HV_X64_MSR_VP_ASSIST_PAGE_ENABLE 0x00000001 387 #define HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_SHIFT 12 388 #define HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_MASK \ 389 (~((1ull << HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_SHIFT) - 1)) 390 391 /* Hyper-V Enlightened VMCS version mask in nested features CPUID */ 392 #define HV_X64_ENLIGHTENED_VMCS_VERSION 0xff 393 394 #define HV_X64_MSR_TSC_REFERENCE_ENABLE 0x00000001 395 #define HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT 12 396 397 /* Number of XMM registers used in hypercall input/output */ 398 #define HV_HYPERCALL_MAX_XMM_REGISTERS 6 399 400 struct hv_nested_enlightenments_control { 401 struct { 402 __u32 directhypercall:1; 403 __u32 reserved:31; 404 } features; 405 struct { 406 __u32 inter_partition_comm:1; 407 __u32 reserved:31; 408 } hypercallControls; 409 } __packed; 410 411 /* Define virtual processor assist page structure. */ 412 struct hv_vp_assist_page { 413 __u32 apic_assist; 414 __u32 reserved1; 415 __u32 vtl_entry_reason; 416 __u32 vtl_reserved; 417 __u64 vtl_ret_x64rax; 418 __u64 vtl_ret_x64rcx; 419 struct hv_nested_enlightenments_control nested_control; 420 __u8 enlighten_vmentry; 421 __u8 reserved2[7]; 422 __u64 current_nested_vmcs; 423 __u8 synthetic_time_unhalted_timer_expired; 424 __u8 reserved3[7]; 425 __u8 virtualization_fault_information[40]; 426 __u8 reserved4[8]; 427 __u8 intercept_message[256]; 428 __u8 vtl_ret_actions[256]; 429 } __packed; 430 431 struct hv_enlightened_vmcs { 432 u32 revision_id; 433 u32 abort; 434 435 u16 host_es_selector; 436 u16 host_cs_selector; 437 u16 host_ss_selector; 438 u16 host_ds_selector; 439 u16 host_fs_selector; 440 u16 host_gs_selector; 441 u16 host_tr_selector; 442 443 u16 padding16_1; 444 445 u64 host_ia32_pat; 446 u64 host_ia32_efer; 447 448 u64 host_cr0; 449 u64 host_cr3; 450 u64 host_cr4; 451 452 u64 host_ia32_sysenter_esp; 453 u64 host_ia32_sysenter_eip; 454 u64 host_rip; 455 u32 host_ia32_sysenter_cs; 456 457 u32 pin_based_vm_exec_control; 458 u32 vm_exit_controls; 459 u32 secondary_vm_exec_control; 460 461 u64 io_bitmap_a; 462 u64 io_bitmap_b; 463 u64 msr_bitmap; 464 465 u16 guest_es_selector; 466 u16 guest_cs_selector; 467 u16 guest_ss_selector; 468 u16 guest_ds_selector; 469 u16 guest_fs_selector; 470 u16 guest_gs_selector; 471 u16 guest_ldtr_selector; 472 u16 guest_tr_selector; 473 474 u32 guest_es_limit; 475 u32 guest_cs_limit; 476 u32 guest_ss_limit; 477 u32 guest_ds_limit; 478 u32 guest_fs_limit; 479 u32 guest_gs_limit; 480 u32 guest_ldtr_limit; 481 u32 guest_tr_limit; 482 u32 guest_gdtr_limit; 483 u32 guest_idtr_limit; 484 485 u32 guest_es_ar_bytes; 486 u32 guest_cs_ar_bytes; 487 u32 guest_ss_ar_bytes; 488 u32 guest_ds_ar_bytes; 489 u32 guest_fs_ar_bytes; 490 u32 guest_gs_ar_bytes; 491 u32 guest_ldtr_ar_bytes; 492 u32 guest_tr_ar_bytes; 493 494 u64 guest_es_base; 495 u64 guest_cs_base; 496 u64 guest_ss_base; 497 u64 guest_ds_base; 498 u64 guest_fs_base; 499 u64 guest_gs_base; 500 u64 guest_ldtr_base; 501 u64 guest_tr_base; 502 u64 guest_gdtr_base; 503 u64 guest_idtr_base; 504 505 u64 padding64_1[3]; 506 507 u64 vm_exit_msr_store_addr; 508 u64 vm_exit_msr_load_addr; 509 u64 vm_entry_msr_load_addr; 510 511 u64 cr3_target_value0; 512 u64 cr3_target_value1; 513 u64 cr3_target_value2; 514 u64 cr3_target_value3; 515 516 u32 page_fault_error_code_mask; 517 u32 page_fault_error_code_match; 518 519 u32 cr3_target_count; 520 u32 vm_exit_msr_store_count; 521 u32 vm_exit_msr_load_count; 522 u32 vm_entry_msr_load_count; 523 524 u64 tsc_offset; 525 u64 virtual_apic_page_addr; 526 u64 vmcs_link_pointer; 527 528 u64 guest_ia32_debugctl; 529 u64 guest_ia32_pat; 530 u64 guest_ia32_efer; 531 532 u64 guest_pdptr0; 533 u64 guest_pdptr1; 534 u64 guest_pdptr2; 535 u64 guest_pdptr3; 536 537 u64 guest_pending_dbg_exceptions; 538 u64 guest_sysenter_esp; 539 u64 guest_sysenter_eip; 540 541 u32 guest_activity_state; 542 u32 guest_sysenter_cs; 543 544 u64 cr0_guest_host_mask; 545 u64 cr4_guest_host_mask; 546 u64 cr0_read_shadow; 547 u64 cr4_read_shadow; 548 u64 guest_cr0; 549 u64 guest_cr3; 550 u64 guest_cr4; 551 u64 guest_dr7; 552 553 u64 host_fs_base; 554 u64 host_gs_base; 555 u64 host_tr_base; 556 u64 host_gdtr_base; 557 u64 host_idtr_base; 558 u64 host_rsp; 559 560 u64 ept_pointer; 561 562 u16 virtual_processor_id; 563 u16 padding16_2[3]; 564 565 u64 padding64_2[5]; 566 u64 guest_physical_address; 567 568 u32 vm_instruction_error; 569 u32 vm_exit_reason; 570 u32 vm_exit_intr_info; 571 u32 vm_exit_intr_error_code; 572 u32 idt_vectoring_info_field; 573 u32 idt_vectoring_error_code; 574 u32 vm_exit_instruction_len; 575 u32 vmx_instruction_info; 576 577 u64 exit_qualification; 578 u64 exit_io_instruction_ecx; 579 u64 exit_io_instruction_esi; 580 u64 exit_io_instruction_edi; 581 u64 exit_io_instruction_eip; 582 583 u64 guest_linear_address; 584 u64 guest_rsp; 585 u64 guest_rflags; 586 587 u32 guest_interruptibility_info; 588 u32 cpu_based_vm_exec_control; 589 u32 exception_bitmap; 590 u32 vm_entry_controls; 591 u32 vm_entry_intr_info_field; 592 u32 vm_entry_exception_error_code; 593 u32 vm_entry_instruction_len; 594 u32 tpr_threshold; 595 596 u64 guest_rip; 597 598 u32 hv_clean_fields; 599 u32 padding32_1; 600 u32 hv_synthetic_controls; 601 struct { 602 u32 nested_flush_hypercall:1; 603 u32 msr_bitmap:1; 604 u32 reserved:30; 605 } __packed hv_enlightenments_control; 606 u32 hv_vp_id; 607 u32 padding32_2; 608 u64 hv_vm_id; 609 u64 partition_assist_page; 610 u64 padding64_4[4]; 611 u64 guest_bndcfgs; 612 u64 guest_ia32_perf_global_ctrl; 613 u64 guest_ia32_s_cet; 614 u64 guest_ssp; 615 u64 guest_ia32_int_ssp_table_addr; 616 u64 guest_ia32_lbr_ctl; 617 u64 padding64_5[2]; 618 u64 xss_exit_bitmap; 619 u64 encls_exiting_bitmap; 620 u64 host_ia32_perf_global_ctrl; 621 u64 tsc_multiplier; 622 u64 host_ia32_s_cet; 623 u64 host_ssp; 624 u64 host_ia32_int_ssp_table_addr; 625 u64 padding64_6; 626 } __packed; 627 628 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_NONE 0 629 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_IO_BITMAP BIT(0) 630 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_MSR_BITMAP BIT(1) 631 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_GRP2 BIT(2) 632 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_GRP1 BIT(3) 633 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_PROC BIT(4) 634 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_EVENT BIT(5) 635 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_ENTRY BIT(6) 636 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_EXCPN BIT(7) 637 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CRDR BIT(8) 638 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_XLAT BIT(9) 639 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_BASIC BIT(10) 640 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_GRP1 BIT(11) 641 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_GRP2 BIT(12) 642 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_HOST_POINTER BIT(13) 643 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_HOST_GRP1 BIT(14) 644 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_ENLIGHTENMENTSCONTROL BIT(15) 645 646 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL 0xFFFF 647 648 /* 649 * Note, Hyper-V isn't actually stealing bit 28 from Intel, just abusing it by 650 * pairing it with architecturally impossible exit reasons. Bit 28 is set only 651 * on SMI exits to a SMI transfer monitor (STM) and if and only if a MTF VM-Exit 652 * is pending. I.e. it will never be set by hardware for non-SMI exits (there 653 * are only three), nor will it ever be set unless the VMM is an STM. 654 */ 655 #define HV_VMX_SYNTHETIC_EXIT_REASON_TRAP_AFTER_FLUSH 0x10000031 656 657 /* 658 * Hyper-V uses the software reserved 32 bytes in VMCB control area to expose 659 * SVM enlightenments to guests. 660 */ 661 struct hv_vmcb_enlightenments { 662 struct __packed hv_enlightenments_control { 663 u32 nested_flush_hypercall:1; 664 u32 msr_bitmap:1; 665 u32 enlightened_npt_tlb: 1; 666 u32 reserved:29; 667 } __packed hv_enlightenments_control; 668 u32 hv_vp_id; 669 u64 hv_vm_id; 670 u64 partition_assist_page; 671 u64 reserved; 672 } __packed; 673 674 /* 675 * Hyper-V uses the software reserved clean bit in VMCB. 676 */ 677 #define HV_VMCB_NESTED_ENLIGHTENMENTS 31 678 679 /* Synthetic VM-Exit */ 680 #define HV_SVM_EXITCODE_ENL 0xf0000000 681 #define HV_SVM_ENL_EXITCODE_TRAP_AFTER_FLUSH (1) 682 683 struct hv_partition_assist_pg { 684 u32 tlb_lock_count; 685 }; 686 687 enum hv_interrupt_type { 688 HV_X64_INTERRUPT_TYPE_FIXED = 0x0000, 689 HV_X64_INTERRUPT_TYPE_LOWESTPRIORITY = 0x0001, 690 HV_X64_INTERRUPT_TYPE_SMI = 0x0002, 691 HV_X64_INTERRUPT_TYPE_REMOTEREAD = 0x0003, 692 HV_X64_INTERRUPT_TYPE_NMI = 0x0004, 693 HV_X64_INTERRUPT_TYPE_INIT = 0x0005, 694 HV_X64_INTERRUPT_TYPE_SIPI = 0x0006, 695 HV_X64_INTERRUPT_TYPE_EXTINT = 0x0007, 696 HV_X64_INTERRUPT_TYPE_LOCALINT0 = 0x0008, 697 HV_X64_INTERRUPT_TYPE_LOCALINT1 = 0x0009, 698 HV_X64_INTERRUPT_TYPE_MAXIMUM = 0x000A, 699 }; 700 701 union hv_msi_address_register { 702 u32 as_uint32; 703 struct { 704 u32 reserved1:2; 705 u32 destination_mode:1; 706 u32 redirection_hint:1; 707 u32 reserved2:8; 708 u32 destination_id:8; 709 u32 msi_base:12; 710 }; 711 } __packed; 712 713 union hv_msi_data_register { 714 u32 as_uint32; 715 struct { 716 u32 vector:8; 717 u32 delivery_mode:3; 718 u32 reserved1:3; 719 u32 level_assert:1; 720 u32 trigger_mode:1; 721 u32 reserved2:16; 722 }; 723 } __packed; 724 725 /* HvRetargetDeviceInterrupt hypercall */ 726 union hv_msi_entry { 727 u64 as_uint64; 728 struct { 729 union hv_msi_address_register address; 730 union hv_msi_data_register data; 731 } __packed; 732 }; 733 734 struct hv_x64_segment_register { 735 u64 base; 736 u32 limit; 737 u16 selector; 738 union { 739 struct { 740 u16 segment_type : 4; 741 u16 non_system_segment : 1; 742 u16 descriptor_privilege_level : 2; 743 u16 present : 1; 744 u16 reserved : 4; 745 u16 available : 1; 746 u16 _long : 1; 747 u16 _default : 1; 748 u16 granularity : 1; 749 } __packed; 750 u16 attributes; 751 }; 752 } __packed; 753 754 struct hv_x64_table_register { 755 u16 pad[3]; 756 u16 limit; 757 u64 base; 758 } __packed; 759 760 struct hv_init_vp_context { 761 u64 rip; 762 u64 rsp; 763 u64 rflags; 764 765 struct hv_x64_segment_register cs; 766 struct hv_x64_segment_register ds; 767 struct hv_x64_segment_register es; 768 struct hv_x64_segment_register fs; 769 struct hv_x64_segment_register gs; 770 struct hv_x64_segment_register ss; 771 struct hv_x64_segment_register tr; 772 struct hv_x64_segment_register ldtr; 773 774 struct hv_x64_table_register idtr; 775 struct hv_x64_table_register gdtr; 776 777 u64 efer; 778 u64 cr0; 779 u64 cr3; 780 u64 cr4; 781 u64 msr_cr_pat; 782 } __packed; 783 784 union hv_input_vtl { 785 u8 as_uint8; 786 struct { 787 u8 target_vtl: 4; 788 u8 use_target_vtl: 1; 789 u8 reserved_z: 3; 790 }; 791 } __packed; 792 793 struct hv_enable_vp_vtl { 794 u64 partition_id; 795 u32 vp_index; 796 union hv_input_vtl target_vtl; 797 u8 mbz0; 798 u16 mbz1; 799 struct hv_init_vp_context vp_context; 800 } __packed; 801 802 struct hv_get_vp_from_apic_id_in { 803 u64 partition_id; 804 union hv_input_vtl target_vtl; 805 u8 res[7]; 806 u32 apic_ids[]; 807 } __packed; 808 809 #include <asm-generic/hyperv-tlfs.h> 810 811 #endif 812