xref: /linux/arch/x86/include/asm/futex.h (revision 03ab8e6297acd1bc0eedaa050e2a1635c576fd11)
1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */
21965aae3SH. Peter Anvin #ifndef _ASM_X86_FUTEX_H
31965aae3SH. Peter Anvin #define _ASM_X86_FUTEX_H
4bb898558SAl Viro 
5bb898558SAl Viro #ifdef __KERNEL__
6bb898558SAl Viro 
7bb898558SAl Viro #include <linux/futex.h>
8bb898558SAl Viro #include <linux/uaccess.h>
9bb898558SAl Viro 
10bb898558SAl Viro #include <asm/asm.h>
11bb898558SAl Viro #include <asm/errno.h>
12bb898558SAl Viro #include <asm/processor.h>
1363bcff2aSH. Peter Anvin #include <asm/smap.h>
14bb898558SAl Viro 
150ec33c01SAl Viro #define unsafe_atomic_op1(insn, oval, uaddr, oparg, label)	\
160ec33c01SAl Viro do {								\
170ec33c01SAl Viro 	int oldval = 0, ret;					\
180ec33c01SAl Viro 	asm volatile("1:\t" insn "\n"				\
190ec33c01SAl Viro 		     "2:\n"					\
20*4c132d1dSPeter Zijlstra 		     _ASM_EXTABLE_TYPE_REG(1b, 2b, EX_TYPE_EFAULT_REG, %1) \
21bb898558SAl Viro 		     : "=r" (oldval), "=r" (ret), "+m" (*uaddr)	\
22*4c132d1dSPeter Zijlstra 		     : "0" (oparg), "1" (0));	\
230ec33c01SAl Viro 	if (ret)						\
240ec33c01SAl Viro 		goto label;					\
250ec33c01SAl Viro 	*oval = oldval;						\
260ec33c01SAl Viro } while(0)
27bb898558SAl Viro 
280ec33c01SAl Viro 
290ec33c01SAl Viro #define unsafe_atomic_op2(insn, oval, uaddr, oparg, label)	\
300ec33c01SAl Viro do {								\
310ec33c01SAl Viro 	int oldval = 0, ret, tem;				\
320ec33c01SAl Viro 	asm volatile("1:\tmovl	%2, %0\n"			\
338aef36daSAl Viro 		     "2:\tmovl\t%0, %3\n"			\
34bb898558SAl Viro 		     "\t" insn "\n"				\
358aef36daSAl Viro 		     "3:\t" LOCK_PREFIX "cmpxchgl %3, %2\n"	\
368aef36daSAl Viro 		     "\tjnz\t2b\n"				\
378aef36daSAl Viro 		     "4:\n"					\
38*4c132d1dSPeter Zijlstra 		     _ASM_EXTABLE_TYPE_REG(1b, 4b, EX_TYPE_EFAULT_REG, %1) \
39*4c132d1dSPeter Zijlstra 		     _ASM_EXTABLE_TYPE_REG(3b, 4b, EX_TYPE_EFAULT_REG, %1) \
40bb898558SAl Viro 		     : "=&a" (oldval), "=&r" (ret),		\
41bb898558SAl Viro 		       "+m" (*uaddr), "=&r" (tem)		\
42*4c132d1dSPeter Zijlstra 		     : "r" (oparg), "1" (0));			\
430ec33c01SAl Viro 	if (ret)						\
440ec33c01SAl Viro 		goto label;					\
450ec33c01SAl Viro 	*oval = oldval;						\
460ec33c01SAl Viro } while(0)
47bb898558SAl Viro 
arch_futex_atomic_op_inuser(int op,int oparg,int * oval,u32 __user * uaddr)480ec33c01SAl Viro static __always_inline int arch_futex_atomic_op_inuser(int op, int oparg, int *oval,
4930d6e0a4SJiri Slaby 		u32 __user *uaddr)
50bb898558SAl Viro {
510ec33c01SAl Viro 	if (!user_access_begin(uaddr, sizeof(u32)))
52a08971e9SAl Viro 		return -EFAULT;
53bb898558SAl Viro 
54bb898558SAl Viro 	switch (op) {
55bb898558SAl Viro 	case FUTEX_OP_SET:
560ec33c01SAl Viro 		unsafe_atomic_op1("xchgl %0, %2", oval, uaddr, oparg, Efault);
57bb898558SAl Viro 		break;
58bb898558SAl Viro 	case FUTEX_OP_ADD:
590ec33c01SAl Viro 		unsafe_atomic_op1(LOCK_PREFIX "xaddl %0, %2", oval,
600ec33c01SAl Viro 				   uaddr, oparg, Efault);
61bb898558SAl Viro 		break;
62bb898558SAl Viro 	case FUTEX_OP_OR:
630ec33c01SAl Viro 		unsafe_atomic_op2("orl %4, %3", oval, uaddr, oparg, Efault);
64bb898558SAl Viro 		break;
65bb898558SAl Viro 	case FUTEX_OP_ANDN:
660ec33c01SAl Viro 		unsafe_atomic_op2("andl %4, %3", oval, uaddr, ~oparg, Efault);
67bb898558SAl Viro 		break;
68bb898558SAl Viro 	case FUTEX_OP_XOR:
690ec33c01SAl Viro 		unsafe_atomic_op2("xorl %4, %3", oval, uaddr, oparg, Efault);
70bb898558SAl Viro 		break;
71bb898558SAl Viro 	default:
720ec33c01SAl Viro 		user_access_end();
730ec33c01SAl Viro 		return -ENOSYS;
74bb898558SAl Viro 	}
750ec33c01SAl Viro 	user_access_end();
760ec33c01SAl Viro 	return 0;
770ec33c01SAl Viro Efault:
780ec33c01SAl Viro 	user_access_end();
790ec33c01SAl Viro 	return -EFAULT;
80bb898558SAl Viro }
81bb898558SAl Viro 
futex_atomic_cmpxchg_inatomic(u32 * uval,u32 __user * uaddr,u32 oldval,u32 newval)828d7718aaSMichel Lespinasse static inline int futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
838d7718aaSMichel Lespinasse 						u32 oldval, u32 newval)
84bb898558SAl Viro {
85f5544ba7SAl Viro 	int ret = 0;
86f5544ba7SAl Viro 
87f5544ba7SAl Viro 	if (!user_access_begin(uaddr, sizeof(u32)))
88f5544ba7SAl Viro 		return -EFAULT;
89f5544ba7SAl Viro 	asm volatile("\n"
90*4c132d1dSPeter Zijlstra 		"1:\t" LOCK_PREFIX "cmpxchgl %3, %2\n"
91f5544ba7SAl Viro 		"2:\n"
92*4c132d1dSPeter Zijlstra 		_ASM_EXTABLE_TYPE_REG(1b, 2b, EX_TYPE_EFAULT_REG, %0) \
93f5544ba7SAl Viro 		: "+r" (ret), "=a" (oldval), "+m" (*uaddr)
94*4c132d1dSPeter Zijlstra 		: "r" (newval), "1" (oldval)
95f5544ba7SAl Viro 		: "memory"
96f5544ba7SAl Viro 	);
97f5544ba7SAl Viro 	user_access_end();
98f5544ba7SAl Viro 	*uval = oldval;
99f5544ba7SAl Viro 	return ret;
100bb898558SAl Viro }
101bb898558SAl Viro 
102bb898558SAl Viro #endif
1031965aae3SH. Peter Anvin #endif /* _ASM_X86_FUTEX_H */
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